WO2020075235A1 - Clock generation device and clock generation method - Google Patents

Clock generation device and clock generation method Download PDF

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Publication number
WO2020075235A1
WO2020075235A1 PCT/JP2018/037703 JP2018037703W WO2020075235A1 WO 2020075235 A1 WO2020075235 A1 WO 2020075235A1 JP 2018037703 W JP2018037703 W JP 2018037703W WO 2020075235 A1 WO2020075235 A1 WO 2020075235A1
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Prior art keywords
clock
time
clock generation
media
synchronization signal
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PCT/JP2018/037703
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French (fr)
Japanese (ja)
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兼司 福田
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株式会社メディアリンクス エルエスアイラボ
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Priority to PCT/JP2018/037703 priority Critical patent/WO2020075235A1/en
Publication of WO2020075235A1 publication Critical patent/WO2020075235A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Definitions

  • the present invention relates to a clock generation device and a clock generation method, and more particularly to a clock generation device used in a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network. And a clock generation method.
  • PTP precision time protocol
  • IEEE1588 Precision time protocol
  • a master device and a slave device connected via a network transmit and receive a synchronization signal in which time information is superimposed, and calculate an error of an internal clock between the master device and the slave device. To enable. Then, by correcting the time in the slave device based on the calculated error, it is possible to accurately synchronize the time in the master device and the slave device (see Patent Document 1, for example).
  • SMPTE Socity of Motion Picture and Television Engineers 2059/2110 as a standard for transmitting media information such as broadcasting between devices connected via a network. According to these standards, it is possible to transmit media information such as broadcasting from a time-synchronized media transmission device to a media reception device via a network using PTP of IEEE1588 (for example, refer to Patent Document 2).
  • the present invention has been made in order to solve the above-described problems, and is intended for a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network.
  • An object of the present invention is to perform clock generation with higher synchronization accuracy in a clock generation device used.
  • the clock generation device made to achieve the above object is a device that performs time synchronization by transmitting and receiving a synchronization signal on which time information is superimposed with a master device connected via a network.
  • the clock generator used is characterized by generating a media clock for superimposing media information using a phase-locked loop that is in phase with the phase of the synchronization signal.
  • a time clock generator that generates a time clock for reading time information from the synchronization signal by performing phase synchronization with the phase of the synchronization signal, and frequency conversion of the time clock generated by the time clock generation unit.
  • a media clock generation unit that generates a media clock for superimposing media information by phase-locking with the phase of the synchronization signal, and frequency conversion of the media clock generated by the media clock generation unit It is desirable to provide a time clock generation unit that generates a time clock for reading time information from the synchronization signal.
  • the phase lock loop includes a filter that excludes, from the synchronization signals transmitted and received to and from the master device, a synchronization signal that is delayed due to the condition of the transmission path in the network.
  • the filter performs statistical processing independently on the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device, thereby transmitting the transmission line in the network. It is desirable to judge whether or not the delay has occurred depending on the situation. Further, it is preferable that the statistical processing selects a minimum value among delay times in the synchronization signal transmitted and received a predetermined number of times.
  • the clock generation method according to the present invention made to achieve the above object performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network.
  • a clock generation method used in a device characterized by generating a media clock for superimposing media information using a phase-locked loop that is phase-locked with the phase of the synchronization signal.
  • a media clock generation step of generating a media clock for superimposing media information by performing phase synchronization with the phase of the frequency-converted signal is a media clock generation step of generating a media clock for superimposing media information by phase-locking with the phase of the synchronization signal, and a frequency of the media clock generated in the media clock generation step
  • the filtering step it is desirable to perform a filtering process in the phase-locked loop process, which excludes, from among the synchronization signals transmitted / received to / from the master device, a synchronization signal delayed due to the condition of the transmission path in the network. .
  • the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device are statistically processed independently of each other in the transmission path in the network. It is desirable to judge whether or not the delay has occurred depending on the situation. Further, it is preferable that the statistical processing selects a minimum value among delay times in the synchronization signal transmitted and received a predetermined number of times.
  • the synchronization accuracy is higher. Clock generation can be performed.
  • FIG. 1 is a diagram showing a schematic configuration of a media transmission system.
  • FIG. 2 is a diagram showing a state of a synchronization signal transmitted / received between the master node and the slave node.
  • FIG. 3 is a diagram showing a clock generation device according to the first embodiment.
  • FIG. 4 is a diagram illustrating a configuration example of the time clock generation unit.
  • FIG. 5 is a diagram illustrating a configuration example of the media clock generation unit.
  • FIG. 6 is a diagram showing a clock generation device according to the second embodiment.
  • FIG. 7 is a diagram illustrating a configuration example of the media clock generation unit.
  • FIG. 8 is a diagram showing a configuration example of the time clock generation unit.
  • FIG. 9 is a diagram showing a clock generation device according to the third embodiment.
  • FIG. 10 is a diagram showing a clock generation device according to the fourth embodiment.
  • FIG. 11 is a simplified flowchart for explaining the function of the filter.
  • FIG. 12 is a diagram
  • the media transmission system 100 includes a media transmission device 200, a media reception device 300, and a master clock device 400.
  • the media transmitting device 200, the media receiving device 300, and the master clock device 400 are connected to a so-called network called the Internet, and are configured to be capable of mutual communication according to the Internet protocol.
  • the media transmission device 200 inputs video data, audio data, auxiliary data, and the like, and performs data processing for transmitting the data to the media reception device 300 as data according to the Internet protocol.
  • the media receiving device 300 receives the data according to the Internet protocol transmitted from the media transmitting device 200, restores this to video data, audio data, auxiliary data, etc., and outputs it.
  • the media transmitting apparatus 200 receives video data, audio data, auxiliary data, etc. from the SDI cable, for example, by the serial receiving unit 201, and clock-receives the received video data, audio data, auxiliary data, etc. by the clock synchronizing unit 202.
  • the clock synchronization used here is synchronized with the clock in the media receiving device 300, as described later in detail.
  • the packetizing unit 203 encapsulates the received video data, audio data, auxiliary data, and the like, and the time stamp unit 204 stamps a time stamp on the encapsulated packet.
  • a packet containing video data, audio data, auxiliary data, etc. is transmitted to the network via the network transmission / reception unit 205.
  • the media receiving device 300 receives at the network transmission / reception unit 301 a packet containing video data, audio data, auxiliary data, etc. transmitted via the network. Then, the received packet is depacketized by the depacket unit 302 and buffered in the buffer 303. The packets that reach the media receiving device 300 do not always arrive in the correct order, and the intervals at which they arrive are not constant. Therefore, the buffer reading unit 304 reads the buffered data by matching the time synchronized with the clock in the media receiving device 300 and the time stamped in the packet, and further, the clock synchronized with the clock in the media receiving device 300. To synchronize the clock.
  • video data, audio data, auxiliary data, etc. are output from the serial transmission unit 305 via, for example, an SDI cable.
  • the media transmission device 200 and the media reception device 300 transmit and receive data via the network. Therefore, in order to properly process the transmitted / received data, the media transmitting device 200 and the media receiving device 300 need to share the highly synchronized time.
  • the media transmitting device 200 and the media receiving device 300 do not directly synchronize the time, but transmit a synchronization signal in which the time information is superimposed with the master clock device 400 connected via the network.
  • Time synchronization is indirectly performed by sending and receiving. That is, the media transmitting device 200 performs time synchronization by transmitting and receiving a synchronization signal in which time information is superposed to and from the master clock device 400 connected via the network, and the media receiving device 300 transmits via the network.
  • Time synchronization is performed by transmitting and receiving a synchronization signal on which time information is superposed to and from the master clock device 400 that is connected with the media clock device 400.
  • the media transmission device 200 and the media reception device 300 perform time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network
  • the clock generation device 10 is provided for generating a media clock for superimposing media information by using a phase lock loop that is phase-locked with the phase of the synchronization signal.
  • the clock generation device 10 included in the media transmission device 200 and the media reception device 300 can adopt a plurality of modified examples having different internal configurations as described later, but substantially the same can be used. Therefore, in the following, the clock generation device 10 included in the media transmission device 200 and the media reception device 300 will be described without distinction.
  • the clock generation device 10 calculates the error of the internal clock between the master clock device 400 and the clock generation device 10 by transmitting and receiving the synchronization signal in which the time information is superimposed with the master clock device 400. By correcting the time in the clock generation device 10 based on the error, the times in the master clock device 400 and the clock generation device 10 are synchronized with each other with high accuracy.
  • the clock generation device 10 also generates a media clock for superimposing media information by using a phase-locked loop that is phase-locked with the phase of this synchronization signal.
  • a phase-locked loop that is phase-locked with the synchronization signal transmitted from the master clock device 400 some variations can be adopted, but these examples will be described later.
  • FIG. 2 is a diagram showing a state of synchronization signals transmitted and received between the master node and the slave nodes.
  • PTP defined by IEEE 1588
  • the internal clock error between the master device and the slave device is increased.
  • the master clock device 400 and the clock generation device 10 shown in FIG. 1 correspond to the master node M and the slave node S, respectively.
  • synchronization messages The roles of the synchronization signals transmitted and received between the master node M and the slave nodes S are specified, and are also called synchronization messages (Sync messages).
  • the Sync message transmitted from the master node M to the slave node S includes the time (T1) at which the Sync message is transmitted from the master node M.
  • the FollowUp message sent from the master node M to the slave node S after the Sync message also includes the time (T1) at which the Sync message is sent from the master node M. This is to address the problem that the Sync message can include the measured value at time (T1) and is only a predicted value. Since the Follow Up message is sent after the Sync message, it is possible to include the measured value at time (T1), and the time (T1) included in the Follow Up message is more accurate.
  • the slave node S that receives the Sync message records the time (T2), and at the same time, predicts the time (T1) included in the Sync message or actually measures the time (T1) included in the Follow Up message. To record. This allows the slave node S to acquire the time (T1) and the time (T2) and calculate the time difference (T2-T1).
  • the slave node S receiving the Sync message sends the Delay Request message to the master node M and records the time (T3) of the sending.
  • the master node M that received the Delay Request message sends the received time (T4) to the slave node S by including it in the Delay Response message.
  • the slave node S that has received the Delay Response message records the time (T4) included in it. Thereby, the slave node S can acquire the time (T3) and the time (T4) and calculate the time difference (T4-T3).
  • the internal clock of the master node M is The internal clock difference (OFS: offset) of the slave node S can be calculated by the following formula.
  • OFS ⁇ (T2-T1)-(T4-T3) ⁇ / 2
  • Dely ⁇ (T2-T1) + (T4-T3) ⁇ / 2
  • Dely is a one-way portion of the delay time required for the synchronization signal to be transmitted between the master node M and the slave node S.
  • the internal clock error (OFS) between the master clock device 400 and the clock generation device 10 can be calculated, and the clock generation device is calculated based on the calculated error.
  • the clock generator 10 can also use the time synchronized with the internal clock of the master clock device 400.
  • the clock generation device 10 also generates a media clock for superimposing media information using a phase lock loop that is phase-locked with the phase of the synchronization signal described above.
  • a configuration example of the clock generation device for generating this media clock will be described.
  • FIG. 3 is a diagram showing a clock generation device according to the first embodiment.
  • the clock generation device 20 receives a synchronization signal (PTP) according to PTP defined by IEEE1588 and superimposes the synchronized media information on the master clock device 400.
  • the media clocks (Video-CLK, SDI-CLK) are generated.
  • the clock generation device 20 synchronizes with the phase of the synchronization signal (PTP) to obtain time information (Time) for reading time information from the synchronization signal (PTP).
  • -CLK time information
  • Time-CLK time clock
  • a media clock generation unit 22 for generating media clocks (Video-CLK, SDI-CLK) for superimposing information is provided.
  • the clock generation device 20 includes the data reproduction unit 23 that reads the data superimposed on the synchronization signal (PTP) using the time clock (Time-CLK) generated by the time clock generation unit 21. I have it.
  • the data reproducing unit 23 not only reads the times (T1, T2, T3, T4) as data superimposed on the synchronization signal (PTP), but also reads the master times from these times (T1, T2, T3, T4). It is configured to calculate and output the aforementioned offset (OFS) corresponding to the difference between the internal clock of the clock generation device 20 and the internal clock of the clock device 400.
  • OFFS aforementioned offset
  • the time clock generation unit 21 can generate the time clock (Time-CLK) from the offset (OFS) by adopting the configuration shown in FIG. 4, for example.
  • the offset (OFS) is an amount corresponding to the difference between the internal clock of the master clock device 400 and the internal clock of the clock generation device 20. Therefore, if the clock generation is controlled so that the offset (OFS) approaches 0, it becomes possible to use the clock that is highly accurately synchronized with the clock in the master clock device 400.
  • the time clock (Time-CLK) generated by the time clock generation unit 21 is returned to the data reproduction unit 23 and reflected in the calculation of the offset (OFS), so that the offset (OFS) approaches 0.
  • the time clock generation unit 21 and the data reproduction unit 23 function as a phase lock loop (phase synchronization circuit).
  • the time clock generation unit 21 includes a PID control unit (PID) and a fractional PLL (fPLL), and uses the offset (OFS) transmitted from the data reproduction unit 23 as an input signal. Then, the time clock (Time-CLK) synchronized with the master clock device 400 can be generated by correcting and outputting the reference clock (Ref-CLK) so that the offset (OFS) approaches zero. It is preferable that the offset (OFS) as an input signal is appropriately PID-controlled and then passed to the fractional PLL (fPLL).
  • a fractional PLL is a PLL that has a frequency division number (fractional number) that is not an integer using a method such as ⁇ modulation and that allows the oscillation frequency to be continuously changed.
  • the media clock generation unit 22 can generate media clocks (Video-CLK, SDI-CLK) from the time clock (Time-CLK) by adopting the configuration shown in FIG. 5, for example.
  • the media clock (Video-CLK) is a clock used when transmitting an image via the Internet, and is, for example, 148.5 MHz.
  • the media clock (SDI-CLK) is a clock used when transmitting an image by the serial digital interface standard represented by the SDI cable, and is 2.97 GHz, for example.
  • the media clock generation unit 22 includes a phase comparator (PFD), a low-pass filter (LPF), and a fractional PLL (fPLL), and a frequency divider (Div) is arranged at each position. There is. As a result, the media clock generation unit 22 can generate the media clocks (Video-CLK, SDI-CLK) using the time clock (Time-CLK) generated by the time clock generation unit 21 as an input signal.
  • PFD phase comparator
  • LPF low-pass filter
  • fPLL fractional PLL
  • Div frequency divider
  • the clock generation device 20 receives the synchronization signal (PTP), and thereby the media clock (Video-Video) for superimposing the synchronized media information on the master clock device 400.
  • CLK, SDI-CLK can be generated.
  • FIG. 6 is a diagram showing a clock generation device according to the second embodiment.
  • the clock generation device 30 according to the second embodiment receives the synchronization signal (PTP) according to the PTP defined by IEEE1588, and superimposes the synchronized media information on the master clock device 400.
  • the media clocks (Video-CLK, SDI-CLK) are generated.
  • the clock generation device 30 uses media clocks (Video-CLK, SDI) for superimposing media information by phase synchronization with the phase of the synchronization signal (PTP).
  • -CLK media clocks
  • a time for reading time information from the synchronization signal (PTP) by frequency-converting the media clock (Video-CLK) generated by the media clock generator 31 and the media clock generator 31.
  • a time clock generator 32 that generates a clock (Time-CLK) is provided.
  • the clock generation device 30 uses the time clock (Time-CLK) generated by the time clock generation unit 32 to read the data superimposed on the synchronization signal (PTP) and to perform the offset (
  • the data reproducing unit 33 that calculates and outputs the OFS) is provided.
  • the media clock (Video-CLK) generated by the media clock generation unit 31 is fed back to the data reproduction unit 33 as the time clock (Time-CLK) via the time clock generation unit 32 and offset (OFS).
  • the media clock generation unit 31 and the data reproduction unit 33 function as a phase lock loop (phase synchronization circuit) by controlling the offset (OFS) to approach 0.
  • the media clock generation unit 31 can generate the media clocks (Video-CLK, SDI-CLK) from the offset (OFS) by adopting the configuration shown in FIG. 7, for example.
  • the media clock generation unit 31 includes a PID control unit (PID) and a fractional PLL (fPLL), and uses an offset (OFS) transmitted from the data reproduction unit 33 as an input signal and an offset ( By correcting and outputting the reference clock (Ref-CLK) so that OFS) approaches zero, media clocks (Video-CLK, SDI-CLK) synchronized with the master clock device 400 can be generated. .
  • PID PID control unit
  • fPLL fractional PLL
  • the output from the fractional PLL (fPLL) is, for example, a 2.97 GHz media clock (SDI-CLK), and, for example, the 148.5 MHz media clock (Video-CLK) is transmitted via a frequency divider (Div) to the media.
  • SDI-CLK 2.97 GHz media clock
  • Video-CLK 148.5 MHz media clock
  • Div frequency divider
  • the clock (SDI-CLK) for use may be output.
  • the time clock generation unit 32 frequency-converts the media clock (Video-CLK) generated by the media clock generation unit 31 by adopting the configuration shown in FIG. 8, for example.
  • the time clock generation unit 32 combines a multiplier (Mul) and a frequency divider (Div) to generate a time clock (Time-CLK) of 125 MHz from a media clock (Video-CLK) of 148.5 MHz, for example. .
  • the clock generation device 30 receives the synchronization signal (PTP), and thereby the media clock (Video-Video) for superimposing the synchronized media information on the master clock device 400.
  • CLK, SDI-CLK can be generated.
  • FIG. 9 is a diagram showing a clock generation device according to the third embodiment
  • FIG. 10 is a diagram showing a clock generation device according to the fourth embodiment.
  • the clock generation device 40 according to the third embodiment like the clock generation device 20 according to the first embodiment, has a time clock generation unit 41, a media clock generation unit 42, and a data reproduction unit 43.
  • a filter 44 is provided inside the data reproducing unit 43.
  • the clock generation device 50 according to the fourth embodiment like the clock generation device 30 according to the second embodiment, has a media clock generation unit 51, a time clock generation unit 52, and data reproduction. And a filter 54 inside the data reproducing unit 53.
  • the clock generation device 40 according to the third embodiment and the clock generation device 50 according to the fourth embodiment are the clock generation device 20 according to the first embodiment and the clock generation device 30 according to the second embodiment, respectively.
  • This is the inside of the phase-locked loop in, specifically, the configuration in which the filters 44 and 54 are added inside the data reproducing units 43 and 53. Therefore, hereinafter, only matters related to the configurations of the filters 44 and 54 will be described.
  • the filters 44 and 54 are for removing, from the synchronization signals (PTP) transmitted / received to / from the master clock device 400, the synchronization signals delayed due to the condition of the transmission path in the network.
  • PTP synchronization signals
  • the method of calculating the error (offset) of the internal clock between the master clock device 400 and the clock generation device 10 according to PTP defined by IEEE1588 is such that the synchronization signal (PTP) is disturbed in the middle of the network. Instead, it is assumed that the data was transmitted in an ideal situation. Therefore, the filters 44 and 54 exclude the synchronization signal delayed due to the condition of the transmission path in the network in order to create the condition where this assumption is satisfied as much as possible.
  • the filters 44 and 54 independently perform statistical processing on the delay time of the synchronization signal (PTP) transmitted from the master clock device 400 and the delay time of the synchronization signal (PTP) transmitted to the master clock device 400. Therefore, it is preferable to judge whether or not the delay has occurred depending on the condition of the transmission path in the network. Since the synchronization signal (PTP) transmitted through the network does not always cause a delay due to the same factor in the forward path and the backward path, the delay time in the forward path and the backward path are statistically processed independently to make a more accurate determination. It can be performed.
  • a method such as a moving average can be adopted, but it is necessary to select the one having the minimum value among the delay times in the synchronization signal (PTP) transmitted and received a predetermined number of times. Is preferred. This is because when the delay time of the synchronization signal (PTP) has the minimum value, it is considered that the synchronization signal (PTP) was transmitted in an ideal state without being disturbed in the middle of the network.
  • the filters 44 and 54 select the filter 44 from the synchronization signals (PTP) received from the master clock device 400 based on the information of the times (T1, T2, T3, T4) acquired by the data reproducing units 43 and 44. , 54 are selected.
  • the filters 44 and 54 are provided with a register for temporarily storing the internally received synchronizing signal (PTP) and a selector for selecting the synchronizing signal (PTP) to pass through the filters 44 and 54.
  • FIG. 11 is a simplified flowchart for explaining the function of the filter.
  • the data reproducing units 43 and 44 acquire the time (T1) and the time (T2) (S1). . This makes it possible to calculate the time difference (T2-T1). Further, it becomes possible to acquire the time (T3) and the time (T4) (S2) and calculate the time difference (T4-T3).
  • At least a predetermined number of times (for example, three times) are temporarily stored, and after repeating the steps S1 and S2 by the predetermined number of times, the process proceeds to the next process (S3). .
  • the minimum value of the time difference (T2-T1) is selected from the times or time differences temporarily stored for a predetermined number of times. (S4). Furthermore, in the clock generation devices 40 and 50 according to the third and fourth embodiments, the minimum value of the time difference (T4 ⁇ T3) is selected from the times or time differences temporarily stored for the predetermined number of times ( S5).
  • the selection of the minimum value in step S4 and step S5 is performed independently. In other words, the acquisition times of the times selected as the minimum value are allowed to be different.
  • OFS ⁇ (T2-T1)-(T4-T3) ⁇ / 2
  • Dely ⁇ (T2-T1) + (T4-T3) ⁇ / 2
  • FIG. 12 is a diagram for explaining an example of the effect of the above minimum value calculation.
  • FIG. 12 illustrates the times (T1, T2, T3, T4) when the synchronization signal is transmitted / received between the master node and the slave node for 1 to 6 times.
  • the time (T1) at which the Sync message is transmitted from the master node is 1000, 2000, 3000, 4000, 5000, 6000, and the time at which the Sync message is transmitted by the slave node corresponding to this (T1) ( T2) is 1030, 2030, 3090, 4060, 5070, 6030.
  • the number of times 3, 4, and 5 causes an unexpected delay, and the time difference (T2-T1) becomes 90, 60, and 70, respectively.
  • the time difference (Filtered T2-T1) at the times 3, 4 and 5 of unexpected delays is applied.
  • the time difference (Filtered T2-T1) at the times 3, 4 and 5 of unexpected delays is applied.
  • the time (T3) is 1100, 2100, 3100, 4100, 5100, 6100
  • the corresponding time (T4) is 1130, 2130. , 3180, 4130, 5130, 6170.
  • an unexpected delay occurs in the numbers 3 and 6, and the time difference (T4 ⁇ T3) becomes 80 and 70, respectively.
  • the time difference (Filtered T4-T3) at the times 3 and 6 at which an unexpected delay occurs are 30 and 30, respectively, and it is possible to reduce the influence caused by the unexpected delay.
  • the clock generators 40 and 50 select the status of the transmission path in the network from among the synchronization signals (PTP) transmitted / received to / from the master clock device 400. Since the phase lock loop is provided with a filter that excludes the synchronization signal delayed by the above, even if an unexpected delay occurs due to congestion in the network, the effect can be suppressed to a small level.

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Abstract

This clock generation device, which is used for a device performing time synchronization by transmitting and receiving a synchronization signal on which time information is superimposed to and from a master device connected via a network, performs clock generation with higher synchronization accuracy. The clock generation device is a clock generation device used for a device performing time synchronization by transmitting and receiving a synchronization signal on which time information is superimposed to and from a master device connected via a network, and is characterized by generating a media clock for superimposing media information, by using a phase-locked loop that is phase-synchronized with the phase of the synchronization signal, thereby performing clock generation with higher synchronization accuracy.

Description

クロック生成装置およびクロック生成方法Clock generation device and clock generation method
　本発明はクロック生成装置およびクロック生成方法に関し、特にネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行う機器に用いられるクロック生成装置およびクロック生成方法に関する。 The present invention relates to a clock generation device and a clock generation method, and more particularly to a clock generation device used in a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network. And a clock generation method.
　従来、ネットワークを介して接続されている装置間の時刻を同期させる仕組みとして、ＩＥＥＥ１５８８にて規定されているＰＴＰ（ｐｒｅｃｉｓｉｏｎ　ｔｉｍｅ　ｐｒｏｔｏｃｏｌ）が知られている。このＩＥＥＥ１５８８のＰＴＰでは、ネットワークを介して接続されているマスタ機器とスレーブ機器との間で時刻情報が重畳された同期信号を送受信し、マスタ機器とスレーブ機器とにおける内部時計の誤差を算出することを可能にする。そして、算出された誤差に基づいてスレーブ機器における時刻を補正することで、マスタ機器とスレーブ機器とにおける時刻を高精度に同期させることができる（例えば特許文献１参照）。 Conventionally, as a mechanism for synchronizing the time between devices connected via a network, PTP (precision time protocol) defined by IEEE1588 is known. In the IEEE 1588 PTP, a master device and a slave device connected via a network transmit and receive a synchronization signal in which time information is superimposed, and calculate an error of an internal clock between the master device and the slave device. To enable. Then, by correcting the time in the slave device based on the calculated error, it is possible to accurately synchronize the time in the master device and the slave device (see Patent Document 1, for example).
　一方、ネットワークを介して接続されている装置間で放送等のメディア情報を伝送するための標準規格としてＳＭＰＴＥ（Ｓｏｃｉｅｔｙ　ｏｆ　Ｍｏｔｉｏｎ　Ｐｉｃｔｕｒｅ　ａｎｄ　Ｔｅｌｅｖｉｓｉｏｎ　Ｅｎｇｉｎｅｅｒｓ）２０５９／２１１０がある。これらの規格では、ＩＥＥＥ１５８８のＰＴＰを用いて時刻同期されたメディア送信装置からメディア受信装置へネットワークを介して放送等のメディア情報を伝送することを可能にする（例えば特許文献２参照）。 On the other hand, there is SMPTE (Socity of Motion Picture and Television Engineers) 2059/2110 as a standard for transmitting media information such as broadcasting between devices connected via a network. According to these standards, it is possible to transmit media information such as broadcasting from a time-synchronized media transmission device to a media reception device via a network using PTP of IEEE1588 (for example, refer to Patent Document 2).
特開２０１３－１５２０９５号公報JP, 2013-152095, A 特開２０１８－３７８８５号公報JP, 2018-37885, A
　ところで、ＩＥＥＥ１５８８とＳＭＰＴＥ２０５９／２１１０の規格は、策定された時期も異なり、これらに関する技術開発も独立に行われてきた。これによって、両者の規格の関係は必ずしも効率的なものとはいえない状況にある。例えば、ＩＥＥＥ１５８８のＰＴＰを用いてＳＭＰＴＥ２０５９／２１１０の伝送をする場合、通常、ＩＥＥＥ１５８８のＰＴＰを用いた技術ではマスタ機器とスレーブ機器とにおける内部時計の誤差を算出するまでにとどまり、算出された誤差を補正した局所発振器のクロックがマスタ機器と同期しているものと仮定してＳＭＰＴＥ２０５９／２１１０の伝送をするのが一般的である。しかしながら、この同期しているとの仮定にも少なからず誤差が存在しており、放送向けの映像データの伝送等の高精度の同期を必要とする場面では、その誤差が無視できない問題となってしまう。 By the way, the standards of IEEE1588 and SMPTE2059 / 2110 were different at the time they were established, and the technical development related to them was carried out independently. As a result, the relationship between the two standards is not always efficient. For example, in the case of transmitting SMPTE2059 / 2110 using PTP of IEEE1588, usually, in the technology using PTP of IEEE1588, it remains until the error of the internal clock between the master device and the slave device is calculated, and the calculated error is Transmission of SMPTE 2059/2110 is generally performed assuming that the clock of the corrected local oscillator is synchronized with the master device. However, there are some errors in the assumption that they are synchronized, and in a scene that requires high-precision synchronization such as transmission of video data for broadcasting, the error becomes a problem that cannot be ignored. I will end up.
　本発明は、前記した課題を解決するためになされたものであり、ネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行う機器に用いられるクロック生成装置において、より同期精度の高いクロック生成を行うことを目的とする。 The present invention has been made in order to solve the above-described problems, and is intended for a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network. An object of the present invention is to perform clock generation with higher synchronization accuracy in a clock generation device used.
　上記目的を達成するためになされた本発明に係るクロック生成装置は、ネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行う機器に用いられるクロック生成装置であって、前記同期信号の位相に対して位相同期するフェイズロックループを用いてメディア情報を重畳するためのメディア用クロックを生成することを特徴とする。 The clock generation device according to the present invention made to achieve the above object is a device that performs time synchronization by transmitting and receiving a synchronization signal on which time information is superimposed with a master device connected via a network. The clock generator used is characterized by generating a media clock for superimposing media information using a phase-locked loop that is in phase with the phase of the synchronization signal.
　尚、前記同期信号の位相に対して位相同期することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成部と、前記時刻クロック生成部が生成した時刻クロックを周波数変換すると共に、前記周波数変換された信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成部と、を備えることが望ましい。
　或いは、前記同期信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成部と、前記メディア用クロック生成部が生成したメディア用クロックを周波数変換することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成部と、を備えることが望ましい。
　また、前記マスタ機器との間で送受信される同期信号の中から、前記ネットワークにおける伝送路の状況によって遅延が生じた同期信号を除外するフィルタを、前記フェイズロックループに備えることが望ましい。
その場合、前記フィルタは、前記マスタ機器から送信された同期信号における遅延時間と、前記マスタ機器に送信された同期信号における遅延時間とを、それぞれ独立に統計処理を行うことで前記ネットワークにおける伝送路の状況によって遅延が生じたか否かを判断することが望ましい。
また、前記統計処理は、所定回数送受信した同期信号における遅延時間の内で最小値となるものを選択するものであることが望ましい。 A time clock generator that generates a time clock for reading time information from the synchronization signal by performing phase synchronization with the phase of the synchronization signal, and frequency conversion of the time clock generated by the time clock generation unit. At the same time, it is preferable to include a media clock generation unit that generates a media clock for superimposing media information by phase synchronization with the phase of the frequency-converted signal.
Alternatively, a media clock generation unit that generates a media clock for superimposing media information by phase-locking with the phase of the synchronization signal, and frequency conversion of the media clock generated by the media clock generation unit It is desirable to provide a time clock generation unit that generates a time clock for reading time information from the synchronization signal.
Further, it is preferable that the phase lock loop includes a filter that excludes, from the synchronization signals transmitted and received to and from the master device, a synchronization signal that is delayed due to the condition of the transmission path in the network.
In that case, the filter performs statistical processing independently on the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device, thereby transmitting the transmission line in the network. It is desirable to judge whether or not the delay has occurred depending on the situation.
Further, it is preferable that the statistical processing selects a minimum value among delay times in the synchronization signal transmitted and received a predetermined number of times.
また、上記目的を達成するためになされた本発明に係るクロック生成方法は、ネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行う機器で用いられるクロック生成方法であって、前記同期信号の位相に対して位相同期するフェイズロックループを用いてメディア情報を重畳するためのメディア用クロックを生成することに特徴を有する。 Further, the clock generation method according to the present invention made to achieve the above object performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network. A clock generation method used in a device, characterized by generating a media clock for superimposing media information using a phase-locked loop that is phase-locked with the phase of the synchronization signal.
　尚、前記同期信号の位相に対して位相同期することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成工程と、前記時刻クロック生成工程にて生成した時刻クロックを周波数変換すると共に、前記周波数変換された信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成工程と、を備えることが望ましい。
　或いは、前記同期信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成工程と、前記メディア用クロック生成工程にて生成したメディア用クロックを周波数変換することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成工程と、を備えることが望ましい。
　また、前記マスタ機器との間で送受信される同期信号の中から、前記ネットワークにおける伝送路の状況によって遅延が生じた同期信号を除外するフィルタ工程を、前記フェイズロックループ工程にて行うことが望ましい。
　また、前記フィルタ工程は、前記マスタ機器から送信された同期信号における遅延時間と、前記マスタ機器に送信された同期信号における遅延時間とを、それぞれ独立に統計処理を行うことで前記ネットワークにおける伝送路の状況によって遅延が生じたか否かを判断することが望ましい。
　また、前記統計処理は、所定回数送受信した同期信号における遅延時間の内で最小値となるものを選択するものであることが望ましい。 A time clock generating step of generating a time clock for reading time information from the synchronization signal by performing phase synchronization with the phase of the synchronization signal, and a frequency conversion of the time clock generated in the time clock generating step. And a media clock generation step of generating a media clock for superimposing media information by performing phase synchronization with the phase of the frequency-converted signal.
Alternatively, a media clock generation step of generating a media clock for superimposing media information by phase-locking with the phase of the synchronization signal, and a frequency of the media clock generated in the media clock generation step And a time clock generating step of generating a time clock for reading time information from the synchronization signal by converting.
Further, it is desirable to perform a filtering process in the phase-locked loop process, which excludes, from among the synchronization signals transmitted / received to / from the master device, a synchronization signal delayed due to the condition of the transmission path in the network. .
In the filtering step, the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device are statistically processed independently of each other in the transmission path in the network. It is desirable to judge whether or not the delay has occurred depending on the situation.
Further, it is preferable that the statistical processing selects a minimum value among delay times in the synchronization signal transmitted and received a predetermined number of times.
　本発明によれば、ネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行う機器に用いられるクロック生成装置において、より同期精度の高いクロック生成を行うことができる。 According to the present invention, in a clock generation device used in a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network, the synchronization accuracy is higher. Clock generation can be performed.
図１は、メディア伝送システムの概略構成を示す図である。FIG. 1 is a diagram showing a schematic configuration of a media transmission system. 図２は、マスタノードとスレーブノードとの間で送受信される同期信号の様子を示す図である。FIG. 2 is a diagram showing a state of a synchronization signal transmitted / received between the master node and the slave node. 図３は、第１実施例にかかるクロック生成装置を示す図である。FIG. 3 is a diagram showing a clock generation device according to the first embodiment. 図４は、時刻クロック生成部の構成例を示す図である。FIG. 4 is a diagram illustrating a configuration example of the time clock generation unit. 図５は、メディア用クロック生成部の構成例を示す図である。FIG. 5 is a diagram illustrating a configuration example of the media clock generation unit. 図６は、第２実施例にかかるクロック生成装置を示す図である。FIG. 6 is a diagram showing a clock generation device according to the second embodiment. 図７は、メディア用クロック生成部の構成例を示す図である。FIG. 7 is a diagram illustrating a configuration example of the media clock generation unit. 図８は、時刻クロック生成部の構成例を示す図である。FIG. 8 is a diagram showing a configuration example of the time clock generation unit. 図９は、第３実施例にかかるクロック生成装置を示す図であるFIG. 9 is a diagram showing a clock generation device according to the third embodiment. 図１０は、第４実施例にかかるクロック生成装置を示す図である。FIG. 10 is a diagram showing a clock generation device according to the fourth embodiment. 図１１は、フィルタの機能を説明するための簡略フローチャートである。FIG. 11 is a simplified flowchart for explaining the function of the filter. 図１２は、最小値計算の効果の例を説明する図である。FIG. 12 is a diagram illustrating an example of the effect of the minimum value calculation.
　以下、図面を参照しながら、本発明の実施形態にかかるクロック生成装置およびクロック生成方法を詳細に説明する。ただし、以下の説明で参照される図面は模式的なものであり、寸法またはその比率が実際のものとは異なる場合がある。 Hereinafter, a clock generation device and a clock generation method according to an embodiment of the present invention will be described in detail with reference to the drawings. However, the drawings referred to in the following description are schematic, and the dimensions or the ratio thereof may differ from the actual ones.
　図１は、メディア伝送システムの概略構成を示す図である。図１に示すように、このメディア伝送システム１００は、メディア送信装置２００とメディア受信装置３００とマスタクロック装置４００とを備えている。メディア送信装置２００、メディア受信装置３００、およびマスタクロック装置４００は、いわゆるインターネットと呼ばれるネットワークに接続されており、インターネットプロトコルに従った通信を相互に行うことが可能に構成されている。 1 is a diagram showing a schematic configuration of a media transmission system. As shown in FIG. 1, the media transmission system 100 includes a media transmission device 200, a media reception device 300, and a master clock device 400. The media transmitting device 200, the media receiving device 300, and the master clock device 400 are connected to a so-called network called the Internet, and are configured to be capable of mutual communication according to the Internet protocol.
　メディア送信装置２００は、映像データや音声データや補助データ等を入力し、これをインターネットプロトコルに従ったデータでメディア受信装置３００へ送信するためのデータ処理を行う。一方、メディア受信装置３００は、メディア送信装置２００から送信されたインターネットプロトコルに従ったデータを受信し、これを映像データや音声データや補助データ等に復元して出力する。 The media transmission device 200 inputs video data, audio data, auxiliary data, and the like, and performs data processing for transmitting the data to the media reception device 300 as data according to the Internet protocol. On the other hand, the media receiving device 300 receives the data according to the Internet protocol transmitted from the media transmitting device 200, restores this to video data, audio data, auxiliary data, etc., and outputs it.
　メディア送信装置２００は、映像データや音声データや補助データ等を例えばＳＤＩケーブルからシリアル受信部２０１で受信し、受信した映像データや音声データや補助データ等をクロック同期部２０２でクロック同期する。ここでのクロック同期は、後に詳述するように、メディア受信装置３００におけるクロックと同期したものを用いる。その後、受信した映像データや音声データや補助データ等をパケット化部２０３でカプセル化し、タイムスタンプ部２０４にてカプセル化したパケットにタイムスタンプを打刻する。最後に、映像データや音声データや補助データ等を内包したパケットがネットワーク送受部２０５を介してネットワークへ送信される。 The media transmitting apparatus 200 receives video data, audio data, auxiliary data, etc. from the SDI cable, for example, by the serial receiving unit 201, and clock-receives the received video data, audio data, auxiliary data, etc. by the clock synchronizing unit 202. The clock synchronization used here is synchronized with the clock in the media receiving device 300, as described later in detail. Thereafter, the packetizing unit 203 encapsulates the received video data, audio data, auxiliary data, and the like, and the time stamp unit 204 stamps a time stamp on the encapsulated packet. Finally, a packet containing video data, audio data, auxiliary data, etc. is transmitted to the network via the network transmission / reception unit 205.
　一方、メディア受信装置３００は、ネットワークを介して送信された映像データや音声データや補助データ等を内包したパケットをネットワーク送受部３０１にて受信する。そして、受信したパケットは逆パケット部３０２にて逆パケット化され、バッファ３０３にバッファリングされる。メディア受信装置３００に到達するパケットは、必ずしも正しい順序で到達せず、到達する間隔も一定ではない。そこで、バッファ読み出し部３０４では、メディア受信装置３００におけるクロックと同期した時刻とパケットに打刻された時刻とを整合させてバッファされたデータを読み出し、さらに、メディア受信装置３００におけるクロックと同期したクロックでクロック同期を行う。なお、ここで用いるメディア受信装置３００におけるクロックとの同期方法は後に詳述する方法を用いる。その後、映像データや音声データや補助データ等は、シリアル送信部３０５から例えばＳＤＩケーブルを介して出力される。 On the other hand, the media receiving device 300 receives at the network transmission / reception unit 301 a packet containing video data, audio data, auxiliary data, etc. transmitted via the network. Then, the received packet is depacketized by the depacket unit 302 and buffered in the buffer 303. The packets that reach the media receiving device 300 do not always arrive in the correct order, and the intervals at which they arrive are not constant. Therefore, the buffer reading unit 304 reads the buffered data by matching the time synchronized with the clock in the media receiving device 300 and the time stamped in the packet, and further, the clock synchronized with the clock in the media receiving device 300. To synchronize the clock. It should be noted that the method of synchronizing with the clock in the media receiving apparatus 300 used here uses the method described in detail later. After that, video data, audio data, auxiliary data, etc. are output from the serial transmission unit 305 via, for example, an SDI cable.
　上記のようにメディア送信装置２００とメディア受信装置３００は、ネットワークを介してデータの送受信を行う。したがって、送受信したデータを適切に処理するためには、メディア送信装置２００とメディア受信装置３００が高精度に同期された時刻を共有している必要がある。 As described above, the media transmission device 200 and the media reception device 300 transmit and receive data via the network. Therefore, in order to properly process the transmitted / received data, the media transmitting device 200 and the media receiving device 300 need to share the highly synchronized time.
　このために、メディア送信装置２００とメディア受信装置３００は、直接的に時刻同期をするのではなく、ネットワークを介して接続されたマスタクロック装置４００との間で時刻情報が重畳された同期信号を送受信することで間接的に時刻同期を行う。すなわち、メディア送信装置２００は、ネットワークを介して接続されたマスタクロック装置４００との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行い、メディア受信装置３００は、ネットワークを介して接続されたマスタクロック装置４００との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行い、結果的にメディア送信装置２００とメディア受信装置３００が高精度に同期された時刻を共有する。 For this reason, the media transmitting device 200 and the media receiving device 300 do not directly synchronize the time, but transmit a synchronization signal in which the time information is superimposed with the master clock device 400 connected via the network. Time synchronization is indirectly performed by sending and receiving. That is, the media transmitting device 200 performs time synchronization by transmitting and receiving a synchronization signal in which time information is superposed to and from the master clock device 400 connected via the network, and the media receiving device 300 transmits via the network. Time synchronization is performed by transmitting and receiving a synchronization signal on which time information is superposed to and from the master clock device 400 that is connected with the media clock device 400. As a result, the time when the media transmission device 200 and the media reception device 300 are highly accurately synchronized. To share.
　この時刻同期を行うために、メディア送信装置２００およびメディア受信装置３００は、ネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行い、当該同期信号の位相に対して位相同期するフェイズロックループを用いてメディア情報を重畳するためのメディア用クロックを生成するためのクロック生成装置１０を備えている。なお、メディア送信装置２００とメディア受信装置３００が備えるクロック生成装置１０は、後に説明するように内部構成が異なる複数の変形例を採用し得るが、実質的に同じものを用いることが可能であるので、以下では、メディア送信装置２００とメディア受信装置３００が備えるクロック生成装置１０を区別せずに説明するものとする。 In order to perform this time synchronization, the media transmission device 200 and the media reception device 300 perform time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network, The clock generation device 10 is provided for generating a media clock for superimposing media information by using a phase lock loop that is phase-locked with the phase of the synchronization signal. Note that the clock generation device 10 included in the media transmission device 200 and the media reception device 300 can adopt a plurality of modified examples having different internal configurations as described later, but substantially the same can be used. Therefore, in the following, the clock generation device 10 included in the media transmission device 200 and the media reception device 300 will be described without distinction.
　クロック生成装置１０は、マスタクロック装置４００との間で時刻情報が重畳された同期信号を送受信することで、マスタクロック装置４００とクロック生成装置１０とにおける内部時計の誤差を算出し、算出された誤差に基づいてクロック生成装置１０における時刻を補正することで、マスタクロック装置４００とクロック生成装置１０とにおける時刻を高精度に同期させる。 The clock generation device 10 calculates the error of the internal clock between the master clock device 400 and the clock generation device 10 by transmitting and receiving the synchronization signal in which the time information is superimposed with the master clock device 400. By correcting the time in the clock generation device 10 based on the error, the times in the master clock device 400 and the clock generation device 10 are synchronized with each other with high accuracy.
　これに加え、クロック生成装置１０は、この同期信号の位相に対して位相同期するフェイズロックループを用いてメディア情報を重畳するためのメディア用クロックを生成することも行う。なお、マスタクロック装置４００から送信される同期信号に対して位相同期するフェイズロックループの構成に関しては、幾つかのバリエーションが採用され得るが、これらの例に関しては後に説明するものとする。 In addition to this, the clock generation device 10 also generates a media clock for superimposing media information by using a phase-locked loop that is phase-locked with the phase of this synchronization signal. Regarding the configuration of the phase-locked loop that is phase-locked with the synchronization signal transmitted from the master clock device 400, some variations can be adopted, but these examples will be described later.
　図２は、マスタノードとスレーブノードとの間で送受信される同期信号の様子を示す図である。図２に示されるように、ＩＥＥＥ１５８８にて規定されるＰＴＰでは、マスタノードＭとスレーブノードＳとの間で、相互に同期信号を送受信することで、マスタ機器とスレーブ機器とにおける内部時計の誤差を算出することを可能にする。図１に示したマスタクロック装置４００およびクロック生成装置１０は、それぞれマスタノードＭとスレーブノードＳに対応している。 FIG. 2 is a diagram showing a state of synchronization signals transmitted and received between the master node and the slave nodes. As shown in FIG. 2, in PTP defined by IEEE 1588, by transmitting and receiving a synchronization signal between the master node M and the slave node S, the internal clock error between the master device and the slave device is increased. Makes it possible to calculate The master clock device 400 and the clock generation device 10 shown in FIG. 1 correspond to the master node M and the slave node S, respectively.
　マスタノードＭとスレーブノードＳとの間で送受信される同期信号には、それぞれ役割が規定されており、同期メッセージ（Ｓｙｎｃメッセージ）とも呼ばれている。 The roles of the synchronization signals transmitted and received between the master node M and the slave nodes S are specified, and are also called synchronization messages (Sync messages).
　図２においてマスタノードＭからスレーブノードＳへ送信されるＳｙｎｃメッセージには、ＳｙｎｃメッセージがマスタノードＭから送信される時刻（Ｔ１）が含まれている。また、Ｓｙｎｃメッセージの後に、マスタノードＭからスレーブノードＳへ送信されるＦｏｌｌｏｗ　Ｕｐメッセージにも、ＳｙｎｃメッセージがマスタノードＭから送信される時刻（Ｔ１）が含まれている。これは、Ｓｙｎｃメッセージには、時刻（Ｔ１）の実測値を含ませることができ、予測値でしかない問題に対処するためのものである。Ｆｏｌｌｏｗ　Ｕｐメッセージは、Ｓｙｎｃメッセージの後に送信されるので、時刻（Ｔ１）の実測値を含ませることが可能であり、Ｆｏｌｌｏｗ　Ｕｐメッセージに含まれる時刻（Ｔ１）の方が精度が高い。 In FIG. 2, the Sync message transmitted from the master node M to the slave node S includes the time (T1) at which the Sync message is transmitted from the master node M. Further, the FollowUp message sent from the master node M to the slave node S after the Sync message also includes the time (T1) at which the Sync message is sent from the master node M. This is to address the problem that the Sync message can include the measured value at time (T1) and is only a predicted value. Since the Follow Up message is sent after the Sync message, it is possible to include the measured value at time (T1), and the time (T1) included in the Follow Up message is more accurate.
　Ｓｙｎｃメッセージを受信したスレーブノードＳは、その時刻（Ｔ２）を記録すると共に、Ｓｙｎｃメッセージに含まれている時刻（Ｔ１）の予測値またはＦｏｌｌｏｗ　Ｕｐメッセージに含まれている時刻（Ｔ１）の実測値を記録する。これにより、スレーブノードＳは、時刻（Ｔ１）および時刻（Ｔ２）を取得し、その時刻差（Ｔ２－Ｔ１）を計算することが可能になる。 The slave node S that receives the Sync message records the time (T2), and at the same time, predicts the time (T1) included in the Sync message or actually measures the time (T1) included in the Follow Up message. To record. This allows the slave node S to acquire the time (T1) and the time (T2) and calculate the time difference (T2-T1).
　その後、Ｓｙｎｃメッセージを受信したスレーブノードＳは、Ｄｅｌａｙ　ＲｅｑｕｅｓｔメッセージをマスタノードＭへ送信すると共に、その送信した時刻（Ｔ３）を記録する。一方、Ｄｅｌａｙ　Ｒｅｑｕｅｓｔメッセージを受信したマスタノードＭは、その受信した時刻（Ｔ４）をＤｅｌａｙ　Ｒｅｓｐｏｎｓｅメッセージに含ませてスレーブノードＳに送信する。Ｄｅｌａｙ　Ｒｅｓｐｏｎｓｅメッセージを受信したスレーブノードＳは、これに含まれる時刻（Ｔ４）を記録する。これにより、スレーブノードＳは、時刻（Ｔ３）および時刻（Ｔ４）を取得し、その時刻差（Ｔ４－Ｔ３）を計算することが可能になる。 After that, the slave node S receiving the Sync message sends the Delay Request message to the master node M and records the time (T3) of the sending. On the other hand, the master node M that received the Delay Request message sends the received time (T4) to the slave node S by including it in the Delay Response message. The slave node S that has received the Delay Response message records the time (T4) included in it. Thereby, the slave node S can acquire the time (T3) and the time (T4) and calculate the time difference (T4-T3).
　ここで、マスタノードＭとスレーブノードＳとの間で送受信される同期信号が、ネットワークの途中で妨害等を受けずに、理想的な状況で伝送されたと仮定すると、マスタノードＭの内部時計に対するスレーブノードＳの内部時計の差（ＯＦＳ：オフセット）は、以下の式で算出することができる。
　　ＯＦＳ＝｛（Ｔ２－Ｔ１）－（Ｔ４－Ｔ３）｝／２
　　Ｄｅｌｙ＝｛（Ｔ２－Ｔ１）＋（Ｔ４－Ｔ３）｝／２
ここで、Ｄｅｌｙは、同期信号がマスタノードＭとスレーブノードＳとの間を伝送するために要する遅延時間の片道分である。 Here, assuming that the synchronization signal transmitted / received between the master node M and the slave node S is transmitted in an ideal situation without being disturbed in the middle of the network, the internal clock of the master node M is The internal clock difference (OFS: offset) of the slave node S can be calculated by the following formula.
OFS = {(T2-T1)-(T4-T3)} / 2
Dely = {(T2-T1) + (T4-T3)} / 2
Here, "Dely" is a one-way portion of the delay time required for the synchronization signal to be transmitted between the master node M and the slave node S.
　このように、ＩＥＥＥ１５８８にて規定されるＰＴＰに従えば、マスタクロック装置４００とクロック生成装置１０とにおける内部時計の誤差（ＯＦＳ）を算出することができ、算出された誤差に基づいてクロック生成装置１０における内部時刻を補正することで、クロック生成装置１０でもマスタクロック装置４００の内部時計に同期した時刻を用いることが可能になる。 As described above, according to the PTP defined by IEEE 1588, the internal clock error (OFS) between the master clock device 400 and the clock generation device 10 can be calculated, and the clock generation device is calculated based on the calculated error. By correcting the internal time in 10, the clock generator 10 can also use the time synchronized with the internal clock of the master clock device 400.
　さらに、これに加え、クロック生成装置１０は、上記説明した同期信号の位相に対して位相同期するフェイズロックループを用いてメディア情報を重畳するためのメディア用クロックを生成することも行う。以下、このメディア用クロックを生成するためのクロック生成装置の構成例を説明する。 Furthermore, in addition to this, the clock generation device 10 also generates a media clock for superimposing media information using a phase lock loop that is phase-locked with the phase of the synchronization signal described above. Hereinafter, a configuration example of the clock generation device for generating this media clock will be described.
　図３は、第１実施例にかかるクロック生成装置を示す図である。図３に示すように、第１実施例にかかるクロック生成装置２０は、ＩＥＥＥ１５８８にて規定されるＰＴＰに従う同期信号（ＰＴＰ）を受信し、マスタクロック装置４００に同期されたメディア情報を重畳するためのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成する。 FIG. 3 is a diagram showing a clock generation device according to the first embodiment. As shown in FIG. 3, the clock generation device 20 according to the first embodiment receives a synchronization signal (PTP) according to PTP defined by IEEE1588 and superimposes the synchronized media information on the master clock device 400. The media clocks (Video-CLK, SDI-CLK) are generated.
　図３に示すように、第１実施例にかかるクロック生成装置２０は、同期信号（ＰＴＰ）の位相に対して位相同期することで同期信号（ＰＴＰ）から時刻情報を読み取るための時刻クロック（Ｔｉｍｅ－ＣＬＫ）を生成する時刻クロック生成部２１と、時刻クロック生成部２１が生成した時刻クロック（Ｔｉｍｅ－ＣＬＫ）を周波数変換すると共に、周波数変換された信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成するメディア用クロック生成部２２とを備えている。 As shown in FIG. 3, the clock generation device 20 according to the first embodiment synchronizes with the phase of the synchronization signal (PTP) to obtain time information (Time) for reading time information from the synchronization signal (PTP). -CLK) and the time clock (Time-CLK) generated by the time clock generation unit 21 are frequency-converted, and phase synchronization is performed with respect to the phase of the frequency-converted signal. A media clock generation unit 22 for generating media clocks (Video-CLK, SDI-CLK) for superimposing information is provided.
　また、第１実施例にかかるクロック生成装置２０は、時刻クロック生成部２１が生成した時刻クロック（Ｔｉｍｅ－ＣＬＫ）を用いて、同期信号（ＰＴＰ）に重畳されたデータを読み取るデータ再生部２３を備えている。なお、データ再生部２３は、同期信号（ＰＴＰ）に重畳されたデータとしての時刻（Ｔ１，Ｔ２，Ｔ３，Ｔ４）を読み取るだけではなく、これら時刻（Ｔ１，Ｔ２，Ｔ３，Ｔ４）から、マスタクロック装置４００の内部時計に対するクロック生成装置２０の内部時計の差に相当する先述のオフセット（ＯＦＳ）を算出して出力するように構成されている。 Further, the clock generation device 20 according to the first embodiment includes the data reproduction unit 23 that reads the data superimposed on the synchronization signal (PTP) using the time clock (Time-CLK) generated by the time clock generation unit 21. I have it. The data reproducing unit 23 not only reads the times (T1, T2, T3, T4) as data superimposed on the synchronization signal (PTP), but also reads the master times from these times (T1, T2, T3, T4). It is configured to calculate and output the aforementioned offset (OFS) corresponding to the difference between the internal clock of the clock generation device 20 and the internal clock of the clock device 400.
　時刻クロック生成部２１は、例えば図４に示すような構成を採用することで、オフセット（ＯＦＳ）から時刻クロック（Ｔｉｍｅ－ＣＬＫ）を生成することができる。先述したように、オフセット（ＯＦＳ）は、マスタクロック装置４００の内部時計に対するクロック生成装置２０の内部時計の差に相当する量である。したがって、オフセット（ＯＦＳ）が０に近づくようにクロック生成を制御すれば、マスタクロック装置４００におけるクロックと高精度に同期されたクロックを利用することが可能になる。このとき、時刻クロック生成部２１が生成した時刻クロック（Ｔｉｍｅ－ＣＬＫ）は、データ再生部２３に帰還されてオフセット（ＯＦＳ）の算出に反映されるので、オフセット（ＯＦＳ）が０に近づくような制御をすることで、時刻クロック生成部２１とデータ再生部２３とがフェイズロックループ（位相同期回路）として機能する。 The time clock generation unit 21 can generate the time clock (Time-CLK) from the offset (OFS) by adopting the configuration shown in FIG. 4, for example. As described above, the offset (OFS) is an amount corresponding to the difference between the internal clock of the master clock device 400 and the internal clock of the clock generation device 20. Therefore, if the clock generation is controlled so that the offset (OFS) approaches 0, it becomes possible to use the clock that is highly accurately synchronized with the clock in the master clock device 400. At this time, the time clock (Time-CLK) generated by the time clock generation unit 21 is returned to the data reproduction unit 23 and reflected in the calculation of the offset (OFS), so that the offset (OFS) approaches 0. By performing the control, the time clock generation unit 21 and the data reproduction unit 23 function as a phase lock loop (phase synchronization circuit).
　具体的には、図４に示すように、時刻クロック生成部２１は、ＰＩＤ制御部（ＰＩＤ）とフラクショナルＰＬＬ（ｆＰＬＬ）とを備え、データ再生部２３から送信されたオフセット（ＯＦＳ）を入力信号とし、オフセット（ＯＦＳ）がゼロに近づくように参照クロック（Ｒｅｆ－ＣＬＫ）を補正して出力することで、マスタクロック装置４００に同期された時刻クロック（Ｔｉｍｅ－ＣＬＫ）を生成することができる。なお、入力信号としてのオフセット（ＯＦＳ）は、適切にＰＩＤ制御したものをフラクショナルＰＬＬ（ｆＰＬＬ）へ受け渡すことが好ましい。フラクショナルＰＬＬとは、ΣΔ変調などの手法を用いて整数ではない分周数（分数）とし、発振周波数を連続的に変化できるようにしたＰＬＬである。 Specifically, as shown in FIG. 4, the time clock generation unit 21 includes a PID control unit (PID) and a fractional PLL (fPLL), and uses the offset (OFS) transmitted from the data reproduction unit 23 as an input signal. Then, the time clock (Time-CLK) synchronized with the master clock device 400 can be generated by correcting and outputting the reference clock (Ref-CLK) so that the offset (OFS) approaches zero. It is preferable that the offset (OFS) as an input signal is appropriately PID-controlled and then passed to the fractional PLL (fPLL). A fractional PLL is a PLL that has a frequency division number (fractional number) that is not an integer using a method such as ΣΔ modulation and that allows the oscillation frequency to be continuously changed.
　メディア用クロック生成部２２は、例えば図５に示すような構成を採用することで、時刻クロック（Ｔｉｍｅ－ＣＬＫ）からメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成することができる。メディア用クロック（Ｖｉｄｅｏ－ＣＬＫ）とは、インターネットを介して映像を伝送する際に用いられるクロックであり、例えば１４８．５ＭＨｚである。一方、メディア用クロック（ＳＤＩ－ＣＬＫ）とは、ＳＤＩケーブルに代表されるシリアルデジタルインタフェース規格で映像を伝送する際に用いられるクロックであり、例えば２．９７ＧＨｚである。 The media clock generation unit 22 can generate media clocks (Video-CLK, SDI-CLK) from the time clock (Time-CLK) by adopting the configuration shown in FIG. 5, for example. The media clock (Video-CLK) is a clock used when transmitting an image via the Internet, and is, for example, 148.5 MHz. On the other hand, the media clock (SDI-CLK) is a clock used when transmitting an image by the serial digital interface standard represented by the SDI cable, and is 2.97 GHz, for example.
　図５に示すように、メディア用クロック生成部２２は、位相比較器（ＰＦＤ）とローパスフィルタ（ＬＰＦ）とフラクショナルＰＬＬ（ｆＰＬＬ）とを備えると共に、各所に分周器（Ｄｉｖ）を配置している。これにより、メディア用クロック生成部２２は、時刻クロック生成部２１が生成した時刻クロック（Ｔｉｍｅ－ＣＬＫ）を入力信号として、メディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成することができる。 As shown in FIG. 5, the media clock generation unit 22 includes a phase comparator (PFD), a low-pass filter (LPF), and a fractional PLL (fPLL), and a frequency divider (Div) is arranged at each position. There is. As a result, the media clock generation unit 22 can generate the media clocks (Video-CLK, SDI-CLK) using the time clock (Time-CLK) generated by the time clock generation unit 21 as an input signal.
　以上説明した構成によって、第１実施例にかかるクロック生成装置２０は、同期信号（ＰＴＰ）を受信することで、マスタクロック装置４００に同期されたメディア情報を重畳するためのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成することができる。 With the configuration described above, the clock generation device 20 according to the first embodiment receives the synchronization signal (PTP), and thereby the media clock (Video-Video) for superimposing the synchronized media information on the master clock device 400. CLK, SDI-CLK) can be generated.
　図６は、第２実施例にかかるクロック生成装置を示す図である。図６に示すように、第２実施例にかかるクロック生成装置３０は、ＩＥＥＥ１５８８にて規定されるＰＴＰに従う同期信号（ＰＴＰ）を受信し、マスタクロック装置４００に同期されたメディア情報を重畳するためのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成する。 FIG. 6 is a diagram showing a clock generation device according to the second embodiment. As shown in FIG. 6, the clock generation device 30 according to the second embodiment receives the synchronization signal (PTP) according to the PTP defined by IEEE1588, and superimposes the synchronized media information on the master clock device 400. The media clocks (Video-CLK, SDI-CLK) are generated.
　図６に示すように、第２実施例にかかるクロック生成装置３０は、同期信号（ＰＴＰ）の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成するメディア用クロック生成部３１と、メディア用クロック生成部３１が生成したメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ）を周波数変換することで同期信号（ＰＴＰ）から時刻情報を読み取るための時刻クロック（Ｔｉｍｅ－ＣＬＫ）を生成する時刻クロック生成部３２とを備えている。
　また、第２実施例にかかるクロック生成装置３０は、時刻クロック生成部３２が生成した時刻クロック（Ｔｉｍｅ－ＣＬＫ）を用いて、同期信号（ＰＴＰ）に重畳されたデータを読み取り、先述のオフセット（ＯＦＳ）を算出して出力するデータ再生部３３を備えている。このとき、メディア用クロック生成部３１が生成したメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ）は、時刻クロック生成部３２を介して時刻クロック（Ｔｉｍｅ－ＣＬＫ）としてデータ再生部３３に帰還されてオフセット（ＯＦＳ）の算出に反映されるので、オフセット（ＯＦＳ）が０に近づくような制御をすることで、メディア用クロック生成部３１とデータ再生部３３がフェイズロックループ（位相同期回路）として機能する。 As shown in FIG. 6, the clock generation device 30 according to the second embodiment uses media clocks (Video-CLK, SDI) for superimposing media information by phase synchronization with the phase of the synchronization signal (PTP). -CLK) and a time for reading time information from the synchronization signal (PTP) by frequency-converting the media clock (Video-CLK) generated by the media clock generator 31 and the media clock generator 31. A time clock generator 32 that generates a clock (Time-CLK) is provided.
Further, the clock generation device 30 according to the second embodiment uses the time clock (Time-CLK) generated by the time clock generation unit 32 to read the data superimposed on the synchronization signal (PTP) and to perform the offset ( The data reproducing unit 33 that calculates and outputs the OFS) is provided. At this time, the media clock (Video-CLK) generated by the media clock generation unit 31 is fed back to the data reproduction unit 33 as the time clock (Time-CLK) via the time clock generation unit 32 and offset (OFS). Is reflected in the calculation of (1), the media clock generation unit 31 and the data reproduction unit 33 function as a phase lock loop (phase synchronization circuit) by controlling the offset (OFS) to approach 0.
　メディア用クロック生成部３１は、例えば図７に示すような構成を採用することで、オフセット（ＯＦＳ）からメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成することができる。図７に示すように、メディア用クロック生成部３１は、ＰＩＤ制御部（ＰＩＤ）とフラクショナルＰＬＬ（ｆＰＬＬ）とを備え、データ再生部３３から送信されたオフセット（ＯＦＳ）を入力信号とし、オフセット（ＯＦＳ）がゼロに近づくように参照クロック（Ｒｅｆ－ＣＬＫ）を補正して出力することで、マスタクロック装置４００に同期されたメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成することができる。フラクショナルＰＬＬ（ｆＰＬＬ）からの出力は、例えば２．９７ＧＨｚのメディア用クロック（ＳＤＩ－ＣＬＫ）とし、例えば１４８．５ＭＨｚのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ）は、分周器（Ｄｉｖ）を介してメディア用クロック（ＳＤＩ－ＣＬＫ）を出力すればよい。 The media clock generation unit 31 can generate the media clocks (Video-CLK, SDI-CLK) from the offset (OFS) by adopting the configuration shown in FIG. 7, for example. As shown in FIG. 7, the media clock generation unit 31 includes a PID control unit (PID) and a fractional PLL (fPLL), and uses an offset (OFS) transmitted from the data reproduction unit 33 as an input signal and an offset ( By correcting and outputting the reference clock (Ref-CLK) so that OFS) approaches zero, media clocks (Video-CLK, SDI-CLK) synchronized with the master clock device 400 can be generated. . The output from the fractional PLL (fPLL) is, for example, a 2.97 GHz media clock (SDI-CLK), and, for example, the 148.5 MHz media clock (Video-CLK) is transmitted via a frequency divider (Div) to the media. The clock (SDI-CLK) for use may be output.
　時刻クロック生成部３２は、例えば図８に示すように構成を採用することで、メディア用クロック生成部３１が生成したメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ）を周波数変換する。時刻クロック生成部３２は、逓倍器（Ｍｕｌ）と分周器（Ｄｉｖ）とを組合せ、例えば１４８．５ＭＨｚのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ）から例えば１２５ＭＨｚの時刻クロック（Ｔｉｍｅ－ＣＬＫ）を生成する。 The time clock generation unit 32 frequency-converts the media clock (Video-CLK) generated by the media clock generation unit 31 by adopting the configuration shown in FIG. 8, for example. The time clock generation unit 32 combines a multiplier (Mul) and a frequency divider (Div) to generate a time clock (Time-CLK) of 125 MHz from a media clock (Video-CLK) of 148.5 MHz, for example. .
　以上説明した構成によって、第２実施例にかかるクロック生成装置３０は、同期信号（ＰＴＰ）を受信することで、マスタクロック装置４００に同期されたメディア情報を重畳するためのメディア用クロック（Ｖｉｄｅｏ－ＣＬＫ，ＳＤＩ－ＣＬＫ）を生成することができる。 With the configuration described above, the clock generation device 30 according to the second embodiment receives the synchronization signal (PTP), and thereby the media clock (Video-Video) for superimposing the synchronized media information on the master clock device 400. CLK, SDI-CLK) can be generated.
　図９は、第３実施例にかかるクロック生成装置を示す図であり、図１０は、第４実施例にかかるクロック生成装置を示す図である。図９に示すように、第３実施例にかかるクロック生成装置４０は、第１実施例にかかるクロック生成装置２０と同様に、時刻クロック生成部４１とメディア用クロック生成部４２とデータ再生部４３とを備え、それに加えて、データ再生部４３の内部にフィルタ４４を備えている。また、図１０に示すように、第４実施例にかかるクロック生成装置５０は、第２実施例にかかるクロック生成装置３０と同様に、メディア用クロック生成部５１と時刻クロック生成部５２とデータ再生部５３とを備え、それに加えて、データ再生部５３の内部にフィルタ５４を備えている。 FIG. 9 is a diagram showing a clock generation device according to the third embodiment, and FIG. 10 is a diagram showing a clock generation device according to the fourth embodiment. As shown in FIG. 9, the clock generation device 40 according to the third embodiment, like the clock generation device 20 according to the first embodiment, has a time clock generation unit 41, a media clock generation unit 42, and a data reproduction unit 43. In addition to that, a filter 44 is provided inside the data reproducing unit 43. Further, as shown in FIG. 10, the clock generation device 50 according to the fourth embodiment, like the clock generation device 30 according to the second embodiment, has a media clock generation unit 51, a time clock generation unit 52, and data reproduction. And a filter 54 inside the data reproducing unit 53.
　上記のように、第３実施例にかかるクロック生成装置４０および第４実施例にかかるクロック生成装置５０は、それぞれ第１実施例にかかるクロック生成装置２０および第２実施例にかかるクロック生成装置３０におけるフェイズロックループの内部であり、具体的にはデータ再生部４３，５３の内部にフィルタ４４，５４を追加した構成である。したがって、以下では、このフィルタ４４，５４の構成に関連する事項のみ説明するものとする。 As described above, the clock generation device 40 according to the third embodiment and the clock generation device 50 according to the fourth embodiment are the clock generation device 20 according to the first embodiment and the clock generation device 30 according to the second embodiment, respectively. This is the inside of the phase-locked loop in, specifically, the configuration in which the filters 44 and 54 are added inside the data reproducing units 43 and 53. Therefore, hereinafter, only matters related to the configurations of the filters 44 and 54 will be described.
　フィルタ４４，５４は、マスタクロック装置４００との間で送受信される同期信号（ＰＴＰ）の中から、ネットワークにおける伝送路の状況によって遅延が生じた同期信号を除外するためのものである。上述したように、ＩＥＥＥ１５８８にて規定されるＰＴＰに従うマスタクロック装置４００とクロック生成装置１０とにおける内部時計の誤差（オフセット）の算出方法は、同期信号（ＰＴＰ）がネットワークの途中で妨害等を受けずに、理想的な状況で伝送されたと仮定したものである。そこで、フィルタ４４，５４は、この仮定が充たされる状況を可能な限り作り出すために、ネットワークにおける伝送路の状況によって遅延が生じた同期信号を除外する。 The filters 44 and 54 are for removing, from the synchronization signals (PTP) transmitted / received to / from the master clock device 400, the synchronization signals delayed due to the condition of the transmission path in the network. As described above, the method of calculating the error (offset) of the internal clock between the master clock device 400 and the clock generation device 10 according to PTP defined by IEEE1588 is such that the synchronization signal (PTP) is disturbed in the middle of the network. Instead, it is assumed that the data was transmitted in an ideal situation. Therefore, the filters 44 and 54 exclude the synchronization signal delayed due to the condition of the transmission path in the network in order to create the condition where this assumption is satisfied as much as possible.
　フィルタ４４，５４は、マスタクロック装置４００から送信された同期信号（ＰＴＰ）における遅延時間と、マスタクロック装置４００に送信された同期信号（ＰＴＰ）における遅延時間とを、それぞれ独立に統計処理を行うことでネットワークにおける伝送路の状況によって遅延が生じたか否かを判断することが好ましい。ネットワークを伝送される同期信号（ＰＴＰ）は、往路と復路で必ずしも同じ要因で遅延が発生するとは限らないので、往路と復路における遅延時間をそれぞれ独立に統計処理を行うことでより精度の高い判断を行うことができる。 The filters 44 and 54 independently perform statistical processing on the delay time of the synchronization signal (PTP) transmitted from the master clock device 400 and the delay time of the synchronization signal (PTP) transmitted to the master clock device 400. Therefore, it is preferable to judge whether or not the delay has occurred depending on the condition of the transmission path in the network. Since the synchronization signal (PTP) transmitted through the network does not always cause a delay due to the same factor in the forward path and the backward path, the delay time in the forward path and the backward path are statistically processed independently to make a more accurate determination. It can be performed.
　ここで、遅延時間に関する統計処理としては、移動平均などの方法を採用することも可能であるが、所定回数送受信した同期信号（ＰＴＰ）における遅延時間の内で最小値となるものを選択することが好ましい。同期信号（ＰＴＰ）における遅延時間が最小値となる場合は、同期信号（ＰＴＰ）がネットワークの途中で妨害等を受けずに理想的な状況で伝送されたと考えられるからである。 Here, as the statistical processing regarding the delay time, a method such as a moving average can be adopted, but it is necessary to select the one having the minimum value among the delay times in the synchronization signal (PTP) transmitted and received a predetermined number of times. Is preferred. This is because when the delay time of the synchronization signal (PTP) has the minimum value, it is considered that the synchronization signal (PTP) was transmitted in an ideal state without being disturbed in the middle of the network.
　以下、遅延時間に関する統計処理として所定回数として３回送受信した同期信号（ＰＴＰ）における遅延時間の内で最小値となるものを選択する方法を採用した例を用いて、フィルタ４４，５４の構成および機能を説明する。 In the following, as a statistical process regarding the delay time, the configuration of the filters 44 and 54 and Describe the function.
　フィルタ４４，５４は、データ再生部４３，４４によって取得された時刻（Ｔ１，Ｔ２，Ｔ３，Ｔ４）の情報に基づいて、マスタクロック装置４００から受信される同期信号（ＰＴＰ）の中からフィルタ４４，５４を通過させるものを選択する。そのために、フィルタ４４，５４は、内部に受信した同期信号（ＰＴＰ）を一次記憶するレジスタとフィルタ４４，５４を通過させる同期信号（ＰＴＰ）を選択するセレクタとを備えている。 The filters 44 and 54 select the filter 44 from the synchronization signals (PTP) received from the master clock device 400 based on the information of the times (T1, T2, T3, T4) acquired by the data reproducing units 43 and 44. , 54 are selected. For that purpose, the filters 44 and 54 are provided with a register for temporarily storing the internally received synchronizing signal (PTP) and a selector for selecting the synchronizing signal (PTP) to pass through the filters 44 and 54.
　図１１は、フィルタの機能を説明するための簡略フローチャートである。図１１に示すように、第３実施例および第４実施例にかかるクロック生成装置４０，５０では、データ再生部４３，４４にて、時刻（Ｔ１）および時刻（Ｔ２）を取得する（Ｓ１）。これにより、その時刻差（Ｔ２－Ｔ１）を計算することが可能になる。さらに、時刻（Ｔ３）および時刻（Ｔ４）を取得し（Ｓ２）、その時刻差（Ｔ４－Ｔ３）を計算することが可能になる。 FIG. 11 is a simplified flowchart for explaining the function of the filter. As shown in FIG. 11, in the clock generation devices 40 and 50 according to the third and fourth embodiments, the data reproducing units 43 and 44 acquire the time (T1) and the time (T2) (S1). . This makes it possible to calculate the time difference (T2-T1). Further, it becomes possible to acquire the time (T3) and the time (T4) (S2) and calculate the time difference (T4-T3).
　これら処理において取得された時刻ないし時刻差は、少なくとも所定回数（例えば３回）分を一次記憶しておき、当該所定回数分ステップＳ１およびステップＳ２を繰り返したのちに次の処理へ進む（Ｓ３）。 As for the time or time difference acquired in these processes, at least a predetermined number of times (for example, three times) are temporarily stored, and after repeating the steps S1 and S2 by the predetermined number of times, the process proceeds to the next process (S3). .
　次に、第３実施例および第４実施例にかかるクロック生成装置４０，５０では、所定回数分を一次記憶されている時刻ないし時刻差から、時刻差（Ｔ２－Ｔ１）の最小値を選択する（Ｓ４）。さらに、第３実施例および第４実施例にかかるクロック生成装置４０，５０では、所定回数分を一次記憶されている時刻ないし時刻差から、時刻差（Ｔ４－Ｔ３）の最小値を選択する（Ｓ５）。ここで、ステップＳ４とステップＳ５における最小値の選択は、それぞれ独立に行われる。すなわち、最小値として選択する時刻の取得回が異なることを許容する。 Next, in the clock generation devices 40 and 50 according to the third and fourth embodiments, the minimum value of the time difference (T2-T1) is selected from the times or time differences temporarily stored for a predetermined number of times. (S4). Furthermore, in the clock generation devices 40 and 50 according to the third and fourth embodiments, the minimum value of the time difference (T4−T3) is selected from the times or time differences temporarily stored for the predetermined number of times ( S5). Here, the selection of the minimum value in step S4 and step S5 is performed independently. In other words, the acquisition times of the times selected as the minimum value are allowed to be different.
　最後に、第３実施例および第４実施例にかかるクロック生成装置４０，５０では、ステップＳ４とステップＳ５にて選択された時刻差（Ｔ２－Ｔ１）の最小値と時刻差（Ｔ４－Ｔ３）の最小値とを用いて、先述したマスタノードとスレーブノードとの間における内部時計の差（ＯＦＳ）および同期信号が伝送するために要する遅延時間の片道分（Ｄｅｌｙ）の計算を行う。
　　ＯＦＳ＝｛（Ｔ２－Ｔ１）－（Ｔ４－Ｔ３）｝／２
　　Ｄｅｌｙ＝｛（Ｔ２－Ｔ１）＋（Ｔ４－Ｔ３）｝／２ Finally, in the clock generation devices 40 and 50 according to the third and fourth embodiments, the minimum value of the time difference (T2-T1) and the time difference (T4-T3) selected in step S4 and step S5. Of the delay time required for transmission of the synchronization signal (OFS) and the synchronization signal between the master node and the slave node described above is calculated by using the minimum value of the above.
OFS = {(T2-T1)-(T4-T3)} / 2
Dely = {(T2-T1) + (T4-T3)} / 2
　図１２は、上記最小値計算の効果の例を説明する図である。図１２には、マスタノードとスレーブノードとの間で同期信号が送受信された時刻（Ｔ１，Ｔ２，Ｔ３，Ｔ４）を１から６回分例示されている。 FIG. 12 is a diagram for explaining an example of the effect of the above minimum value calculation. FIG. 12 illustrates the times (T1, T2, T3, T4) when the synchronization signal is transmitted / received between the master node and the slave node for 1 to 6 times.
　図１２に示すように、マスタノードからＳｙｎｃメッセージが送信された時刻（Ｔ１）は、１０００，２０００，３０００，４０００，５０００，６０００であり、これに対応するスレーブノードでＳｙｎｃメッセージを送信した時刻（Ｔ２）は、１０３０，２０３０，３０９０，４０６０，５０７０，６０３０であるとする。この場合、回数３、４、５では不測の遅延が生じていることになり、時刻差（Ｔ２－Ｔ１）は、それぞれ９０，６０，７０となってしまう。 As shown in FIG. 12, the time (T1) at which the Sync message is transmitted from the master node is 1000, 2000, 3000, 4000, 5000, 6000, and the time at which the Sync message is transmitted by the slave node corresponding to this (T1) ( T2) is 1030, 2030, 3090, 4060, 5070, 6030. In this case, the number of times 3, 4, and 5 causes an unexpected delay, and the time difference (T2-T1) becomes 90, 60, and 70, respectively.
　そこで、上記説明した所定回数送受信した同期信号における遅延時間の内で最小値となるものを選択する方法を適用すると、不測の遅延が生じた回数３，４，５における時刻差（Ｆｉｌｔｅｒｅｄ　Ｔ２－Ｔ１）は、それぞれ３０，３０，６０となり、不測の遅延に起因する影響を少なくすることが可能になる。 Therefore, if the method of selecting the minimum value among the delay times of the synchronization signals transmitted and received a predetermined number of times as described above is applied, the time difference (Filtered T2-T1) at the times 3, 4 and 5 of unexpected delays is applied. ) Are 30, 30, and 60, respectively, and it is possible to reduce the influence caused by the unexpected delay.
　同様に、Ｄｅｌａｙ　Ｒｅｑｕｅｓｔメッセージについても考え、図１２に示すように、時刻（Ｔ３）は、１１００，２１００，３１００，４１００，５１００，６１００であり、これに対応する時刻（Ｔ４）は、１１３０，２１３０，３１８０，４１３０，５１３０，６１７０であるとする。この場合、回数３，６では不測の遅延が生じていることになり、時刻差（Ｔ４－Ｔ３）は、それぞれ８０，７０となってしまう。 Similarly, considering the Delay Request message, as shown in FIG. 12, the time (T3) is 1100, 2100, 3100, 4100, 5100, 6100, and the corresponding time (T4) is 1130, 2130. , 3180, 4130, 5130, 6170. In this case, an unexpected delay occurs in the numbers 3 and 6, and the time difference (T4−T3) becomes 80 and 70, respectively.
　同様に、上記説明した所定回数送受信した同期信号における遅延時間の内で最小値となるものを選択する方法を適用すると、不測の遅延が生じた回数３，６における時刻差（Ｆｉｌｔｅｒｅｄ　Ｔ４－Ｔ３）は、それぞれ３０，３０となり、不測の遅延に起因する影響を少なくすることが可能になる。 Similarly, when the method of selecting the minimum delay time among the synchronization signals transmitted / received a predetermined number of times as described above is applied, the time difference (Filtered T4-T3) at the times 3 and 6 at which an unexpected delay occurs Are 30 and 30, respectively, and it is possible to reduce the influence caused by the unexpected delay.
　さらに、時刻差（Ｔ２－Ｔ１）の最小値と時刻差（Ｔ４－Ｔ３）の最小値とを用いて、｛（Ｔ２－Ｔ１）＋（Ｔ４－Ｔ３）｝／２を計算すると、回数５のみが４５となっているが、その他の回数では、不測の遅延が生じていな場合の数値となり、回数５に関しても誤差は少なく抑えることができている。 Further, when {(T2-T1) + (T4-T3)} / 2 is calculated using the minimum value of the time difference (T2-T1) and the minimum value of the time difference (T4-T3), only the number of times 5 is obtained. Is 45, but at other times, it is a numerical value when an unexpected delay does not occur, and the error can be suppressed to be small even for the number of times 5.
　上記のように、第３実施例および第４実施例にかかるクロック生成装置４０，５０は、マスタクロック装置４００との間で送受信される同期信号（ＰＴＰ）の中から、ネットワークにおける伝送路の状況によって遅延が生じた同期信号を除外するフィルタを、フェイズロックループに備えているので、ネットワークにおける輻輳などに起因する不測の遅延が生じた場合でも、その影響を少なく抑えることが可能である。 As described above, the clock generators 40 and 50 according to the third and fourth embodiments select the status of the transmission path in the network from among the synchronization signals (PTP) transmitted / received to / from the master clock device 400. Since the phase lock loop is provided with a filter that excludes the synchronization signal delayed by the above, even if an unexpected delay occurs due to congestion in the network, the effect can be suppressed to a small level.
　以上、図面を参照しながら本発明を実施形態に基づいて説明してきたが、本発明は上記の実施形態よって限定されるものではない。 Although the present invention has been described based on the embodiments with reference to the drawings, the present invention is not limited to the above embodiments.
　１０，２０，３０，４０，５０　クロック生成装置
　２１，３２，４１，５２　時刻クロック生成部
　２２，３１，４２，５１　メディア用クロック生成部
　２３，３３，４３，５３　データ再生部
　４４，５４　フィルタ
　１００　メディア伝送システム
　２００　メディア送信装置
　２０１　シリアル受信部
　２０２　クロック同期部
　２０３　パケット化部
　２０４　タイムスタンプ部
　２０５　ネットワーク送受部
　３００　メディア受信装置
　３０１　ネットワーク送受部
　３０２　逆パケット部
　３０３　バッファ
　３０４　バッファ読み出し部
　３０５　シリアル送信部
　４００　マスタクロック装置

  10, 20, 30, 40, 50 Clock generation device 21, 32, 41, 52 Time clock generation unit 22, 31, 42, 51 Media clock generation unit 23, 33, 43, 53 Data reproduction unit 44, 54 Filter 100 Media transmission system 200 Media transmission device 201 Serial reception unit 202 Clock synchronization unit 203 Packetization unit 204 Time stamp unit 205 Network transmission / reception unit 300 Media reception device 301 Network transmission / reception unit 302 Reverse packet unit 303 Buffer 304 Buffer reading unit 305 Serial transmission unit 400 Master clock device

Claims (12)

  1. 　ネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行う機器に用いられるクロック生成装置であって、
    　前記同期信号の位相に対して位相同期するフェイズロックループを用いてメディア情報を重畳するためのメディア用クロックを生成することを特徴とするクロック生成装置。     A clock generation device used for a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network,
    A clock generation device for generating a media clock for superimposing media information using a phase-locked loop that is in phase with the phase of the synchronization signal.
  2. 　前記同期信号の位相に対して位相同期することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成部と、
    　前記時刻クロック生成部が生成した時刻クロックを周波数変換すると共に、前記周波数変換された信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成部と、
    　を備えることを特徴とする請求項１に記載のクロック生成装置。     A time clock generation unit that generates a time clock for reading time information from the synchronization signal by performing phase synchronization with the phase of the synchronization signal;
    A media clock generation unit that frequency-converts the time clock generated by the time clock generation unit and generates a media clock for superimposing media information by phase synchronization with the phase of the frequency-converted signal. When,
    The clock generation device according to claim 1, further comprising:
  3. 　前記同期信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成部と、
    　前記メディア用クロック生成部が生成したメディア用クロックを周波数変換することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成部と、
    　を備えることを特徴とする請求項１に記載のクロック生成装置。     A media clock generation unit that generates a media clock for superimposing media information by phase synchronization with the phase of the synchronization signal;
    A time clock generation unit that generates a time clock for reading time information from the synchronization signal by frequency-converting the media clock generated by the media clock generation unit;
    The clock generation device according to claim 1, further comprising:
  4. 　前記マスタ機器との間で送受信される同期信号の中から、前記ネットワークにおける伝送路の状況によって遅延が生じた同期信号を除外するフィルタを、前記フェイズロックループに備えることを特徴とする請求項１から請求項３の何れか１項に記載のクロック生成装置。 The phase-locked loop is provided with a filter that excludes a synchronization signal delayed due to a situation of a transmission line in the network from among synchronization signals transmitted and received to and from the master device. 4. The clock generation device according to claim 3.
  5. 　前記フィルタは、前記マスタ機器から送信された同期信号における遅延時間と、前記マスタ機器に送信された同期信号における遅延時間とを、それぞれ独立に統計処理を行うことで前記ネットワークにおける伝送路の状況によって遅延が生じたか否かを判断することを特徴とする請求項４に記載のクロック生成装置。 The filter performs statistical processing independently on the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device, depending on the situation of the transmission path in the network. The clock generation device according to claim 4, wherein it is determined whether or not a delay has occurred.
  6. 　前記統計処理は、所定回数送受信した同期信号における遅延時間の内で最小値となるものを選択するものであることを特徴とする請求項５に記載のクロック生成装置。 6. The clock generation device according to claim 5, wherein the statistical processing selects a minimum value among delay times in the synchronization signal transmitted and received a predetermined number of times.
  7. 　ネットワークを介して接続されたマスタ機器との間で時刻情報が重畳された同期信号を送受信することで時刻同期を行う機器で用いられるクロック生成方法であって、
    　前記同期信号の位相に対して位相同期するフェイズロックループを用いてメディア情報を重畳するためのメディア用クロックを生成することを特徴とするクロック生成方法。     A clock generation method used in a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network,
    A clock generation method for generating a media clock for superimposing media information using a phase-locked loop that is in phase with the phase of the synchronization signal.
  8. 　前記同期信号の位相に対して位相同期することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成工程と、
    　前記時刻クロック生成工程にて生成した時刻クロックを周波数変換すると共に、前記周波数変換された信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成工程と、
    　を備えることを特徴とする請求項７に記載のクロック生成方法。     A time clock generating step of generating a time clock for reading time information from the synchronization signal by performing phase synchronization with the phase of the synchronization signal;
    Media clock generation for generating a media clock for superimposing media information by frequency-converting the time clock generated in the time-clock generating step and phase-synchronizing with the phase of the frequency-converted signal Process,
    The clock generation method according to claim 7, further comprising:
  9. 　前記同期信号の位相に対して位相同期することでメディア情報を重畳するためのメディア用クロックを生成するメディア用クロック生成工程と、
    　前記メディア用クロック生成工程にて生成したメディア用クロックを周波数変換することで前記同期信号から時刻情報を読み取るための時刻クロックを生成する時刻クロック生成工程と、
    　を備えることを特徴とする請求項７に記載のクロック生成方法。     A media clock generating step of generating a media clock for superimposing media information by phase-synchronizing with the phase of the synchronization signal;
    A time clock generation step of generating a time clock for reading time information from the synchronization signal by frequency-converting the media clock generated in the media clock generation step;
    The clock generation method according to claim 7, further comprising:
  10. 　前記マスタ機器との間で送受信される同期信号の中から、前記ネットワークにおける伝送路の状況によって遅延が生じた同期信号を除外するフィルタ工程を、前記フェイズロックループにて行うことを特徴とする請求項７から請求項９の何れか１項に記載のクロック生成方法。 The phase-locked loop is used to perform a filtering step of excluding, from the synchronization signals transmitted / received to / from the master device, a synchronization signal having a delay due to a condition of a transmission line in the network. The clock generation method according to any one of claims 7 to 9.
  11. 　前記フィルタ工程は、前記マスタ機器から送信された同期信号における遅延時間と、前記マスタ機器に送信された同期信号における遅延時間とを、それぞれ独立に統計処理を行うことで前記ネットワークにおける伝送路の状況によって遅延が生じたか否かを判断することを特徴とする請求項１０に記載のクロック生成方法。 In the filtering step, the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device are statistically processed independently of each other to determine the status of the transmission path in the network. 11. The clock generation method according to claim 10, wherein it is determined whether or not a delay has occurred.
  12. 　前記統計処理は、所定回数送受信した同期信号における遅延時間の内で最小値となるものを選択するものであることを特徴とする請求項１１に記載のクロック生成方法。 12. The clock generation method according to claim 11, wherein the statistical processing is to select a minimum value among delay times in a synchronization signal transmitted and received a predetermined number of times.
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