WO2020075235A1 - Dispositif de génération d'horloge et procédé de génération d'horloge - Google Patents

Dispositif de génération d'horloge et procédé de génération d'horloge Download PDF

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Publication number
WO2020075235A1
WO2020075235A1 PCT/JP2018/037703 JP2018037703W WO2020075235A1 WO 2020075235 A1 WO2020075235 A1 WO 2020075235A1 JP 2018037703 W JP2018037703 W JP 2018037703W WO 2020075235 A1 WO2020075235 A1 WO 2020075235A1
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clock
time
clock generation
media
synchronization signal
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PCT/JP2018/037703
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English (en)
Japanese (ja)
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兼司 福田
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株式会社メディアリンクス エルエスアイラボ
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Priority to PCT/JP2018/037703 priority Critical patent/WO2020075235A1/fr
Publication of WO2020075235A1 publication Critical patent/WO2020075235A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Definitions

  • the present invention relates to a clock generation device and a clock generation method, and more particularly to a clock generation device used in a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network. And a clock generation method.
  • PTP precision time protocol
  • IEEE1588 Precision time protocol
  • a master device and a slave device connected via a network transmit and receive a synchronization signal in which time information is superimposed, and calculate an error of an internal clock between the master device and the slave device. To enable. Then, by correcting the time in the slave device based on the calculated error, it is possible to accurately synchronize the time in the master device and the slave device (see Patent Document 1, for example).
  • SMPTE Socity of Motion Picture and Television Engineers 2059/2110 as a standard for transmitting media information such as broadcasting between devices connected via a network. According to these standards, it is possible to transmit media information such as broadcasting from a time-synchronized media transmission device to a media reception device via a network using PTP of IEEE1588 (for example, refer to Patent Document 2).
  • the present invention has been made in order to solve the above-described problems, and is intended for a device that performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network.
  • An object of the present invention is to perform clock generation with higher synchronization accuracy in a clock generation device used.
  • the clock generation device made to achieve the above object is a device that performs time synchronization by transmitting and receiving a synchronization signal on which time information is superimposed with a master device connected via a network.
  • the clock generator used is characterized by generating a media clock for superimposing media information using a phase-locked loop that is in phase with the phase of the synchronization signal.
  • a time clock generator that generates a time clock for reading time information from the synchronization signal by performing phase synchronization with the phase of the synchronization signal, and frequency conversion of the time clock generated by the time clock generation unit.
  • a media clock generation unit that generates a media clock for superimposing media information by phase-locking with the phase of the synchronization signal, and frequency conversion of the media clock generated by the media clock generation unit It is desirable to provide a time clock generation unit that generates a time clock for reading time information from the synchronization signal.
  • the phase lock loop includes a filter that excludes, from the synchronization signals transmitted and received to and from the master device, a synchronization signal that is delayed due to the condition of the transmission path in the network.
  • the filter performs statistical processing independently on the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device, thereby transmitting the transmission line in the network. It is desirable to judge whether or not the delay has occurred depending on the situation. Further, it is preferable that the statistical processing selects a minimum value among delay times in the synchronization signal transmitted and received a predetermined number of times.
  • the clock generation method according to the present invention made to achieve the above object performs time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network.
  • a clock generation method used in a device characterized by generating a media clock for superimposing media information using a phase-locked loop that is phase-locked with the phase of the synchronization signal.
  • a media clock generation step of generating a media clock for superimposing media information by performing phase synchronization with the phase of the frequency-converted signal is a media clock generation step of generating a media clock for superimposing media information by phase-locking with the phase of the synchronization signal, and a frequency of the media clock generated in the media clock generation step
  • the filtering step it is desirable to perform a filtering process in the phase-locked loop process, which excludes, from among the synchronization signals transmitted / received to / from the master device, a synchronization signal delayed due to the condition of the transmission path in the network. .
  • the delay time in the synchronization signal transmitted from the master device and the delay time in the synchronization signal transmitted to the master device are statistically processed independently of each other in the transmission path in the network. It is desirable to judge whether or not the delay has occurred depending on the situation. Further, it is preferable that the statistical processing selects a minimum value among delay times in the synchronization signal transmitted and received a predetermined number of times.
  • the synchronization accuracy is higher. Clock generation can be performed.
  • FIG. 1 is a diagram showing a schematic configuration of a media transmission system.
  • FIG. 2 is a diagram showing a state of a synchronization signal transmitted / received between the master node and the slave node.
  • FIG. 3 is a diagram showing a clock generation device according to the first embodiment.
  • FIG. 4 is a diagram illustrating a configuration example of the time clock generation unit.
  • FIG. 5 is a diagram illustrating a configuration example of the media clock generation unit.
  • FIG. 6 is a diagram showing a clock generation device according to the second embodiment.
  • FIG. 7 is a diagram illustrating a configuration example of the media clock generation unit.
  • FIG. 8 is a diagram showing a configuration example of the time clock generation unit.
  • FIG. 9 is a diagram showing a clock generation device according to the third embodiment.
  • FIG. 10 is a diagram showing a clock generation device according to the fourth embodiment.
  • FIG. 11 is a simplified flowchart for explaining the function of the filter.
  • FIG. 12 is a diagram
  • the media transmission system 100 includes a media transmission device 200, a media reception device 300, and a master clock device 400.
  • the media transmitting device 200, the media receiving device 300, and the master clock device 400 are connected to a so-called network called the Internet, and are configured to be capable of mutual communication according to the Internet protocol.
  • the media transmission device 200 inputs video data, audio data, auxiliary data, and the like, and performs data processing for transmitting the data to the media reception device 300 as data according to the Internet protocol.
  • the media receiving device 300 receives the data according to the Internet protocol transmitted from the media transmitting device 200, restores this to video data, audio data, auxiliary data, etc., and outputs it.
  • the media transmitting apparatus 200 receives video data, audio data, auxiliary data, etc. from the SDI cable, for example, by the serial receiving unit 201, and clock-receives the received video data, audio data, auxiliary data, etc. by the clock synchronizing unit 202.
  • the clock synchronization used here is synchronized with the clock in the media receiving device 300, as described later in detail.
  • the packetizing unit 203 encapsulates the received video data, audio data, auxiliary data, and the like, and the time stamp unit 204 stamps a time stamp on the encapsulated packet.
  • a packet containing video data, audio data, auxiliary data, etc. is transmitted to the network via the network transmission / reception unit 205.
  • the media receiving device 300 receives at the network transmission / reception unit 301 a packet containing video data, audio data, auxiliary data, etc. transmitted via the network. Then, the received packet is depacketized by the depacket unit 302 and buffered in the buffer 303. The packets that reach the media receiving device 300 do not always arrive in the correct order, and the intervals at which they arrive are not constant. Therefore, the buffer reading unit 304 reads the buffered data by matching the time synchronized with the clock in the media receiving device 300 and the time stamped in the packet, and further, the clock synchronized with the clock in the media receiving device 300. To synchronize the clock.
  • video data, audio data, auxiliary data, etc. are output from the serial transmission unit 305 via, for example, an SDI cable.
  • the media transmission device 200 and the media reception device 300 transmit and receive data via the network. Therefore, in order to properly process the transmitted / received data, the media transmitting device 200 and the media receiving device 300 need to share the highly synchronized time.
  • the media transmitting device 200 and the media receiving device 300 do not directly synchronize the time, but transmit a synchronization signal in which the time information is superimposed with the master clock device 400 connected via the network.
  • Time synchronization is indirectly performed by sending and receiving. That is, the media transmitting device 200 performs time synchronization by transmitting and receiving a synchronization signal in which time information is superposed to and from the master clock device 400 connected via the network, and the media receiving device 300 transmits via the network.
  • Time synchronization is performed by transmitting and receiving a synchronization signal on which time information is superposed to and from the master clock device 400 that is connected with the media clock device 400.
  • the media transmission device 200 and the media reception device 300 perform time synchronization by transmitting and receiving a synchronization signal in which time information is superimposed with a master device connected via a network
  • the clock generation device 10 is provided for generating a media clock for superimposing media information by using a phase lock loop that is phase-locked with the phase of the synchronization signal.
  • the clock generation device 10 included in the media transmission device 200 and the media reception device 300 can adopt a plurality of modified examples having different internal configurations as described later, but substantially the same can be used. Therefore, in the following, the clock generation device 10 included in the media transmission device 200 and the media reception device 300 will be described without distinction.
  • the clock generation device 10 calculates the error of the internal clock between the master clock device 400 and the clock generation device 10 by transmitting and receiving the synchronization signal in which the time information is superimposed with the master clock device 400. By correcting the time in the clock generation device 10 based on the error, the times in the master clock device 400 and the clock generation device 10 are synchronized with each other with high accuracy.
  • the clock generation device 10 also generates a media clock for superimposing media information by using a phase-locked loop that is phase-locked with the phase of this synchronization signal.
  • a phase-locked loop that is phase-locked with the synchronization signal transmitted from the master clock device 400 some variations can be adopted, but these examples will be described later.
  • FIG. 2 is a diagram showing a state of synchronization signals transmitted and received between the master node and the slave nodes.
  • PTP defined by IEEE 1588
  • the internal clock error between the master device and the slave device is increased.
  • the master clock device 400 and the clock generation device 10 shown in FIG. 1 correspond to the master node M and the slave node S, respectively.
  • synchronization messages The roles of the synchronization signals transmitted and received between the master node M and the slave nodes S are specified, and are also called synchronization messages (Sync messages).
  • the Sync message transmitted from the master node M to the slave node S includes the time (T1) at which the Sync message is transmitted from the master node M.
  • the FollowUp message sent from the master node M to the slave node S after the Sync message also includes the time (T1) at which the Sync message is sent from the master node M. This is to address the problem that the Sync message can include the measured value at time (T1) and is only a predicted value. Since the Follow Up message is sent after the Sync message, it is possible to include the measured value at time (T1), and the time (T1) included in the Follow Up message is more accurate.
  • the slave node S that receives the Sync message records the time (T2), and at the same time, predicts the time (T1) included in the Sync message or actually measures the time (T1) included in the Follow Up message. To record. This allows the slave node S to acquire the time (T1) and the time (T2) and calculate the time difference (T2-T1).
  • the slave node S receiving the Sync message sends the Delay Request message to the master node M and records the time (T3) of the sending.
  • the master node M that received the Delay Request message sends the received time (T4) to the slave node S by including it in the Delay Response message.
  • the slave node S that has received the Delay Response message records the time (T4) included in it. Thereby, the slave node S can acquire the time (T3) and the time (T4) and calculate the time difference (T4-T3).
  • the internal clock of the master node M is The internal clock difference (OFS: offset) of the slave node S can be calculated by the following formula.
  • OFS ⁇ (T2-T1)-(T4-T3) ⁇ / 2
  • Dely ⁇ (T2-T1) + (T4-T3) ⁇ / 2
  • Dely is a one-way portion of the delay time required for the synchronization signal to be transmitted between the master node M and the slave node S.
  • the internal clock error (OFS) between the master clock device 400 and the clock generation device 10 can be calculated, and the clock generation device is calculated based on the calculated error.
  • the clock generator 10 can also use the time synchronized with the internal clock of the master clock device 400.
  • the clock generation device 10 also generates a media clock for superimposing media information using a phase lock loop that is phase-locked with the phase of the synchronization signal described above.
  • a configuration example of the clock generation device for generating this media clock will be described.
  • FIG. 3 is a diagram showing a clock generation device according to the first embodiment.
  • the clock generation device 20 receives a synchronization signal (PTP) according to PTP defined by IEEE1588 and superimposes the synchronized media information on the master clock device 400.
  • the media clocks (Video-CLK, SDI-CLK) are generated.
  • the clock generation device 20 synchronizes with the phase of the synchronization signal (PTP) to obtain time information (Time) for reading time information from the synchronization signal (PTP).
  • -CLK time information
  • Time-CLK time clock
  • a media clock generation unit 22 for generating media clocks (Video-CLK, SDI-CLK) for superimposing information is provided.
  • the clock generation device 20 includes the data reproduction unit 23 that reads the data superimposed on the synchronization signal (PTP) using the time clock (Time-CLK) generated by the time clock generation unit 21. I have it.
  • the data reproducing unit 23 not only reads the times (T1, T2, T3, T4) as data superimposed on the synchronization signal (PTP), but also reads the master times from these times (T1, T2, T3, T4). It is configured to calculate and output the aforementioned offset (OFS) corresponding to the difference between the internal clock of the clock generation device 20 and the internal clock of the clock device 400.
  • OFFS aforementioned offset
  • the time clock generation unit 21 can generate the time clock (Time-CLK) from the offset (OFS) by adopting the configuration shown in FIG. 4, for example.
  • the offset (OFS) is an amount corresponding to the difference between the internal clock of the master clock device 400 and the internal clock of the clock generation device 20. Therefore, if the clock generation is controlled so that the offset (OFS) approaches 0, it becomes possible to use the clock that is highly accurately synchronized with the clock in the master clock device 400.
  • the time clock (Time-CLK) generated by the time clock generation unit 21 is returned to the data reproduction unit 23 and reflected in the calculation of the offset (OFS), so that the offset (OFS) approaches 0.
  • the time clock generation unit 21 and the data reproduction unit 23 function as a phase lock loop (phase synchronization circuit).
  • the time clock generation unit 21 includes a PID control unit (PID) and a fractional PLL (fPLL), and uses the offset (OFS) transmitted from the data reproduction unit 23 as an input signal. Then, the time clock (Time-CLK) synchronized with the master clock device 400 can be generated by correcting and outputting the reference clock (Ref-CLK) so that the offset (OFS) approaches zero. It is preferable that the offset (OFS) as an input signal is appropriately PID-controlled and then passed to the fractional PLL (fPLL).
  • a fractional PLL is a PLL that has a frequency division number (fractional number) that is not an integer using a method such as ⁇ modulation and that allows the oscillation frequency to be continuously changed.
  • the media clock generation unit 22 can generate media clocks (Video-CLK, SDI-CLK) from the time clock (Time-CLK) by adopting the configuration shown in FIG. 5, for example.
  • the media clock (Video-CLK) is a clock used when transmitting an image via the Internet, and is, for example, 148.5 MHz.
  • the media clock (SDI-CLK) is a clock used when transmitting an image by the serial digital interface standard represented by the SDI cable, and is 2.97 GHz, for example.
  • the media clock generation unit 22 includes a phase comparator (PFD), a low-pass filter (LPF), and a fractional PLL (fPLL), and a frequency divider (Div) is arranged at each position. There is. As a result, the media clock generation unit 22 can generate the media clocks (Video-CLK, SDI-CLK) using the time clock (Time-CLK) generated by the time clock generation unit 21 as an input signal.
  • PFD phase comparator
  • LPF low-pass filter
  • fPLL fractional PLL
  • Div frequency divider
  • the clock generation device 20 receives the synchronization signal (PTP), and thereby the media clock (Video-Video) for superimposing the synchronized media information on the master clock device 400.
  • CLK, SDI-CLK can be generated.
  • FIG. 6 is a diagram showing a clock generation device according to the second embodiment.
  • the clock generation device 30 according to the second embodiment receives the synchronization signal (PTP) according to the PTP defined by IEEE1588, and superimposes the synchronized media information on the master clock device 400.
  • the media clocks (Video-CLK, SDI-CLK) are generated.
  • the clock generation device 30 uses media clocks (Video-CLK, SDI) for superimposing media information by phase synchronization with the phase of the synchronization signal (PTP).
  • -CLK media clocks
  • a time for reading time information from the synchronization signal (PTP) by frequency-converting the media clock (Video-CLK) generated by the media clock generator 31 and the media clock generator 31.
  • a time clock generator 32 that generates a clock (Time-CLK) is provided.
  • the clock generation device 30 uses the time clock (Time-CLK) generated by the time clock generation unit 32 to read the data superimposed on the synchronization signal (PTP) and to perform the offset (
  • the data reproducing unit 33 that calculates and outputs the OFS) is provided.
  • the media clock (Video-CLK) generated by the media clock generation unit 31 is fed back to the data reproduction unit 33 as the time clock (Time-CLK) via the time clock generation unit 32 and offset (OFS).
  • the media clock generation unit 31 and the data reproduction unit 33 function as a phase lock loop (phase synchronization circuit) by controlling the offset (OFS) to approach 0.
  • the media clock generation unit 31 can generate the media clocks (Video-CLK, SDI-CLK) from the offset (OFS) by adopting the configuration shown in FIG. 7, for example.
  • the media clock generation unit 31 includes a PID control unit (PID) and a fractional PLL (fPLL), and uses an offset (OFS) transmitted from the data reproduction unit 33 as an input signal and an offset ( By correcting and outputting the reference clock (Ref-CLK) so that OFS) approaches zero, media clocks (Video-CLK, SDI-CLK) synchronized with the master clock device 400 can be generated. .
  • PID PID control unit
  • fPLL fractional PLL
  • the output from the fractional PLL (fPLL) is, for example, a 2.97 GHz media clock (SDI-CLK), and, for example, the 148.5 MHz media clock (Video-CLK) is transmitted via a frequency divider (Div) to the media.
  • SDI-CLK 2.97 GHz media clock
  • Video-CLK 148.5 MHz media clock
  • Div frequency divider
  • the clock (SDI-CLK) for use may be output.
  • the time clock generation unit 32 frequency-converts the media clock (Video-CLK) generated by the media clock generation unit 31 by adopting the configuration shown in FIG. 8, for example.
  • the time clock generation unit 32 combines a multiplier (Mul) and a frequency divider (Div) to generate a time clock (Time-CLK) of 125 MHz from a media clock (Video-CLK) of 148.5 MHz, for example. .
  • the clock generation device 30 receives the synchronization signal (PTP), and thereby the media clock (Video-Video) for superimposing the synchronized media information on the master clock device 400.
  • CLK, SDI-CLK can be generated.
  • FIG. 9 is a diagram showing a clock generation device according to the third embodiment
  • FIG. 10 is a diagram showing a clock generation device according to the fourth embodiment.
  • the clock generation device 40 according to the third embodiment like the clock generation device 20 according to the first embodiment, has a time clock generation unit 41, a media clock generation unit 42, and a data reproduction unit 43.
  • a filter 44 is provided inside the data reproducing unit 43.
  • the clock generation device 50 according to the fourth embodiment like the clock generation device 30 according to the second embodiment, has a media clock generation unit 51, a time clock generation unit 52, and data reproduction. And a filter 54 inside the data reproducing unit 53.
  • the clock generation device 40 according to the third embodiment and the clock generation device 50 according to the fourth embodiment are the clock generation device 20 according to the first embodiment and the clock generation device 30 according to the second embodiment, respectively.
  • This is the inside of the phase-locked loop in, specifically, the configuration in which the filters 44 and 54 are added inside the data reproducing units 43 and 53. Therefore, hereinafter, only matters related to the configurations of the filters 44 and 54 will be described.
  • the filters 44 and 54 are for removing, from the synchronization signals (PTP) transmitted / received to / from the master clock device 400, the synchronization signals delayed due to the condition of the transmission path in the network.
  • PTP synchronization signals
  • the method of calculating the error (offset) of the internal clock between the master clock device 400 and the clock generation device 10 according to PTP defined by IEEE1588 is such that the synchronization signal (PTP) is disturbed in the middle of the network. Instead, it is assumed that the data was transmitted in an ideal situation. Therefore, the filters 44 and 54 exclude the synchronization signal delayed due to the condition of the transmission path in the network in order to create the condition where this assumption is satisfied as much as possible.
  • the filters 44 and 54 independently perform statistical processing on the delay time of the synchronization signal (PTP) transmitted from the master clock device 400 and the delay time of the synchronization signal (PTP) transmitted to the master clock device 400. Therefore, it is preferable to judge whether or not the delay has occurred depending on the condition of the transmission path in the network. Since the synchronization signal (PTP) transmitted through the network does not always cause a delay due to the same factor in the forward path and the backward path, the delay time in the forward path and the backward path are statistically processed independently to make a more accurate determination. It can be performed.
  • a method such as a moving average can be adopted, but it is necessary to select the one having the minimum value among the delay times in the synchronization signal (PTP) transmitted and received a predetermined number of times. Is preferred. This is because when the delay time of the synchronization signal (PTP) has the minimum value, it is considered that the synchronization signal (PTP) was transmitted in an ideal state without being disturbed in the middle of the network.
  • the filters 44 and 54 select the filter 44 from the synchronization signals (PTP) received from the master clock device 400 based on the information of the times (T1, T2, T3, T4) acquired by the data reproducing units 43 and 44. , 54 are selected.
  • the filters 44 and 54 are provided with a register for temporarily storing the internally received synchronizing signal (PTP) and a selector for selecting the synchronizing signal (PTP) to pass through the filters 44 and 54.
  • FIG. 11 is a simplified flowchart for explaining the function of the filter.
  • the data reproducing units 43 and 44 acquire the time (T1) and the time (T2) (S1). . This makes it possible to calculate the time difference (T2-T1). Further, it becomes possible to acquire the time (T3) and the time (T4) (S2) and calculate the time difference (T4-T3).
  • At least a predetermined number of times (for example, three times) are temporarily stored, and after repeating the steps S1 and S2 by the predetermined number of times, the process proceeds to the next process (S3). .
  • the minimum value of the time difference (T2-T1) is selected from the times or time differences temporarily stored for a predetermined number of times. (S4). Furthermore, in the clock generation devices 40 and 50 according to the third and fourth embodiments, the minimum value of the time difference (T4 ⁇ T3) is selected from the times or time differences temporarily stored for the predetermined number of times ( S5).
  • the selection of the minimum value in step S4 and step S5 is performed independently. In other words, the acquisition times of the times selected as the minimum value are allowed to be different.
  • OFS ⁇ (T2-T1)-(T4-T3) ⁇ / 2
  • Dely ⁇ (T2-T1) + (T4-T3) ⁇ / 2
  • FIG. 12 is a diagram for explaining an example of the effect of the above minimum value calculation.
  • FIG. 12 illustrates the times (T1, T2, T3, T4) when the synchronization signal is transmitted / received between the master node and the slave node for 1 to 6 times.
  • the time (T1) at which the Sync message is transmitted from the master node is 1000, 2000, 3000, 4000, 5000, 6000, and the time at which the Sync message is transmitted by the slave node corresponding to this (T1) ( T2) is 1030, 2030, 3090, 4060, 5070, 6030.
  • the number of times 3, 4, and 5 causes an unexpected delay, and the time difference (T2-T1) becomes 90, 60, and 70, respectively.
  • the time difference (Filtered T2-T1) at the times 3, 4 and 5 of unexpected delays is applied.
  • the time difference (Filtered T2-T1) at the times 3, 4 and 5 of unexpected delays is applied.
  • the time (T3) is 1100, 2100, 3100, 4100, 5100, 6100
  • the corresponding time (T4) is 1130, 2130. , 3180, 4130, 5130, 6170.
  • an unexpected delay occurs in the numbers 3 and 6, and the time difference (T4 ⁇ T3) becomes 80 and 70, respectively.
  • the time difference (Filtered T4-T3) at the times 3 and 6 at which an unexpected delay occurs are 30 and 30, respectively, and it is possible to reduce the influence caused by the unexpected delay.
  • the clock generators 40 and 50 select the status of the transmission path in the network from among the synchronization signals (PTP) transmitted / received to / from the master clock device 400. Since the phase lock loop is provided with a filter that excludes the synchronization signal delayed by the above, even if an unexpected delay occurs due to congestion in the network, the effect can be suppressed to a small level.

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Abstract

L'invention concerne un dispositif de génération d'horloge, qui est utilisé pour un dispositif effectuant une synchronisation temporelle par émission et réception d'un signal de synchronisation sur lequel des informations de temps sont superposées à et à partir d'un dispositif maître connecté par l'intermédiaire d'un réseau, et qui effectue une génération d'horloge avec une précision de synchronisation plus élevée. Le dispositif de génération d'horloge est un dispositif de génération d'horloge utilisé pour un dispositif effectuant une synchronisation temporelle par émission et réception d'un signal de synchronisation sur lequel des informations temporelles sont superposées à et à partir d'un dispositif maître connecté par l'intermédiaire d'un réseau, et est caractérisé par la génération d'une horloge multimédia pour la superposition d'informations multimédias, à l'aide d'une boucle à verrouillage de phase qui est synchronisée en phase avec la phase du signal de synchronisation, réalisant ainsi une génération d'horloge avec une précision de synchronisation plus élevée.
PCT/JP2018/037703 2018-10-10 2018-10-10 Dispositif de génération d'horloge et procédé de génération d'horloge WO2020075235A1 (fr)

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