JP2014033413A - Semiconductor device and frequency error calculation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that it takes time to calculate deviation amount of a frequency of a clock signal in a conventional device.SOLUTION: In the semiconductor device, a theoretical value in a first period indicating the period in which a clock edge of an input signal SCL is input is calculated on the basis of the ratio of a theoretical value CLKA_f of the frequency of a first clock signal CLKA having low frequency accuracy and a theoretical value SCL of the frequency of an input signal having a high frequency accuracy. Moreover, the semiconductor device calculates the theoretical value in the first period whenever the clock edge of the first clock signal CLKA is input. And, the semiconductor device calculates the deviation amount from the theoretical value of the frequency of the first clock signal CLKA on the basis of whether or not the clock edge of the input signal SCL has been input in the first period.

Description

  The present invention relates to a semiconductor device and a frequency error calculation program, for example, a semiconductor device that operates using an externally applied clock signal as an operation lock, and a frequency error calculation program executed in the semiconductor device.

  In a digital broadcast receiving device, a receiving device may be constructed by combining a first semiconductor device that performs tuning processing and demodulation processing of a received signal and a second semiconductor device that performs decoding processing of a demodulated signal. At this time, each of the first semiconductor device and the second semiconductor device requires a reference clock signal serving as a reference for the operation clock signal. This reference clock signal is required to have a small absolute frequency error and a small jitter.

  For example, in the first semiconductor device, when the absolute value error of the frequency of the reference clock signal increases, the frequency shift of the local signal used for the tuning process increases and the carrier cannot be supplemented by the demodulation process. Further, in the first semiconductor device, when the absolute value error of the frequency of the reference clock signal becomes large, there occurs a problem that the PLL (Phase Locked Loop) of the clock recovery system cannot be locked to the demodulated signal. Further, even in the second semiconductor device, when the absolute value error of the frequency of the reference clock signal becomes large, there arises a problem that an appropriate decoding speed cannot be maintained. Further, when the jitter characteristic of the reference clock signal is deteriorated, there is a problem that the reception characteristic of the first semiconductor device is deteriorated.

  As described above, the frequency accuracy and jitter accuracy of the reference clock signal greatly affect the performance of the receiving apparatus. Therefore, a digital broadcast receiving apparatus often uses a crystal oscillator as a signal source of a reference clock signal. However, since the crystal oscillator is expensive, it is required to reduce the number of crystal oscillators in order to suppress the cost increase of the receiving device.

  One method of reducing the number of crystal oscillators is to supply a reference clock signal generated by one crystal oscillator to one semiconductor device and to the other semiconductor device a clock generated from the reference clock signal in one semiconductor device. It is conceivable to give a signal. However, in this case, problems such as an increase in signal lines between the two semiconductor devices and an increase in jitter due to the added signal lines occur. As another method for reducing the number of crystal oscillators, it is conceivable to use a ceramic oscillator having low jitter characteristics but inferior frequency accuracy instead of the crystal oscillator. When the ceramic oscillator is used in this way, it is necessary to detect the frequency error and correct the frequency error in order to ensure frequency accuracy. Therefore, Patent Document 1 discloses an example of a frequency error detection circuit.

  The frequency error detection circuit described in Patent Document 1 calculates and averages the number of DPLL controls in a plurality of burst periods in a time division direction control transmission type communication apparatus. As a result, the frequency error detection circuit described in Patent Document 1 increases or decreases the master clock count in the DPLL circuit by increasing or decreasing the pulses with respect to the master clock in accordance with the phase shift caused by the frequency error. The frequency error can be detected by matching the clock phases. The frequency error detection circuit described in Patent Document 1 can detect a frequency error with high accuracy without being affected by variations in each burst.

Japanese Examined Patent Publication No. 6-81042

  In the technique described in Patent Document 1, since a frequency error is calculated every time a burst signal is input, in order to converge the frequency error within a predetermined range, a large number of burst signals must be received. There is a problem that it takes a lot of time to obtain a high frequency error.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, in the semiconductor device, the logic level of the input signal is based on the ratio between the theoretical value of the frequency of the first clock signal with low frequency accuracy and the theoretical value of the frequency of the input signal with high frequency accuracy. The theoretical value of the first period indicating the period of transition of is calculated. In addition, the semiconductor device calculates the theoretical value of the first period every time the clock edge of the first clock signal is input. Then, the semiconductor device calculates an amount of deviation from the theoretical value of the frequency of the first clock signal based on whether or not the logic level of the input signal has changed during the first period.

  According to the embodiment, it is possible to calculate the deviation amount from the theoretical value of the frequency of the second clock signal with low frequency accuracy at high speed and with high accuracy.

1 is a block diagram of a receiving system including a semiconductor device according to a first embodiment; FIG. 3 is a diagram of a phase difference calculation unit according to the first embodiment. 4 is a timing chart for explaining the operation of the semiconductor device according to the first embodiment; It is a figure explaining the frequency error amount when the clock edge of an input signal is input during the carry generation period. It is a figure explaining the frequency error amount when the clock edge of an input signal is input during the carry non-occurrence period immediately before the carry generation period. It is a figure explaining the frequency error amount when the clock edge of an input signal is input during the carry generation period. It is a figure explaining the frequency error amount when the clock edge of an input signal is input during the carry non-occurrence period immediately after the carry generation period. FIG. 6 is a diagram for explaining a deviation amount calculated by the semiconductor device according to the first embodiment when the frequency of the first clock signal is an ideal value; FIG. 6 is a diagram for explaining a deviation amount calculated by the semiconductor device according to the first embodiment when the frequency of the first clock signal is higher than an ideal value. FIG. 6 is a diagram for explaining a deviation amount calculated by the semiconductor device according to the first embodiment when the frequency of the first clock signal is lower than an ideal value. FIG. 4 is a block diagram of a receiving system including a semiconductor device according to a second embodiment. FIG. 6 is a block diagram of a receiving system including a semiconductor device according to a third embodiment. FIG. 6 is a block diagram of a receiving system including a semiconductor device according to a fourth embodiment.

Embodiment 1
Hereinafter, embodiments will be described with reference to the drawings. In the first embodiment, a semiconductor device having a frequency error calculation unit that calculates a deviation amount from a theoretical value of the frequency of an externally generated reference clock signal will be described. This semiconductor device may have any function as long as it operates based on the reference clock signal. In the first embodiment, as an example of the semiconductor device, a down-conversion process is performed in a digital broadcast receiving system. A semiconductor device (for example, a receiving circuit) that performs demodulation processing will be described.

  FIG. 1 is a block diagram of a receiving system according to the first embodiment. As shown in FIG. 1, the reception system includes a reception circuit 1 and a host IC 2. The receiving circuit 1 is a semiconductor device in which a circuit is formed on one semiconductor chip. The host IC 2 is a semiconductor device in which a circuit is formed on a different semiconductor chip from the receiving circuit 1.

  The receiving circuit 1 operates based on the first clock signal CLKA generated by the low-accuracy clock signal generation unit 3. The receiving circuit 1 performs a down-conversion process and a demodulation process on the received signal received via the antenna ANT, and reproduces a data signal. The host IC 2 performs processing based on the data signal from the receiving circuit 1. In the first embodiment, the host IC 2 performs a decoding process on the data signal and controls the receiving circuit 1. The host IC 2 operates based on the reference clock signal CLKR generated by the high precision clock signal generation unit 4.

  Here, the clock signal generation unit will be described. In the receiving system according to the first embodiment, two clock signal generators with different accuracy are used. The accuracy of the clock signal includes accuracy with respect to jitter characteristics and accuracy with respect to an absolute value of frequency. The low-accuracy clock signal generation unit 3 generates the first clock signal CLKA that has low accuracy with respect to the absolute value of frequency and high accuracy with respect to jitter characteristics. In addition, the high-accuracy clock signal generation unit 4 has higher accuracy with respect to the absolute value of the frequency than the low-accuracy clock signal generation unit 3, and the accuracy with respect to jitter characteristics is as high as that of the first clock signal CLKA. That is, in the embodiment, when referring to the absolute value of the frequency, the expression that the accuracy of the clock signal generation unit and the clock signal is high or low is used. As the low-accuracy clock generation unit 3, a ceramic oscillator or the like can be used. As the high-accuracy clock generation unit 4, a crystal oscillator or the like can be used. The crystal oscillator is expensive and causes an increase in cost.

  Subsequently, the receiving system according to the first exemplary embodiment will be described in detail. As illustrated in FIG. 1, the reception circuit 1 includes a clock correction unit 10, an analog PLL circuit 11, a tuner unit 12, a digital PLL circuit 13, and a demodulation processing unit 14.

  The clock correction unit 10 operates based on the first clock signal CLKA. Then, the clock correction unit 10 calculates an error between the absolute value and the ideal value of the frequency of the first clock signal CLKA based on the first clock signal CLKA and the control signal (a signal including the serial data SDA and the serial clock SCL). A shift amount MOD to be corrected is calculated.

  The analog PLL circuit 11 generates an operation signal (for example, the local signal CLKA) based on the first clock signal CLKA. At this time, the analog PLL circuit 11 controls the frequency of the local signal CLKL based on the analog value. The analog PLL circuit 11 adjusts the frequency of the local signal CLKL with reference to the shift amount MOD generated by the clock correction unit 10.

  The tuner unit 12 performs a down-conversion process for generating a baseband signal or an intermediate frequency signal IF having a frequency lower than that of the received signal based on the received signal input from the antenna ANT based on the local signal and the local signal CLKL.

  The digital PLL circuit 13 generates an operation signal (for example, the operation clock signal CLKD) based on the first clock signal CLKA. At this time, the digital PLL circuit 13 controls the frequency of the operation clock signal CLKD based on the digital value. In addition, the digital PLL circuit 13 refers to the shift amount MOD generated by the clock correction unit 10 and adjusts the frequency of the operation clock signal CLKD.

  The demodulation processing unit 14 performs demodulation processing on the baseband signal based on the operation clock signal D. Then, the demodulated signal is output to the host IC 2 as a data signal.

  The host IC 2 includes a signal processing unit 31, a frequency dividing circuit 32, and a communication interface circuit 33. The signal processing unit 31 is a calculation unit such as a CPU, for example, and performs processing according to a program. In the first embodiment, the signal processing unit 31 performs a decoding process or the like on the data signal generated by the demodulation process of the demodulation processing unit 14. The signal processor 31 operates based on the reference clock signal CLKR generated by the high precision clock signal generator 4. In the example shown in FIG. 1, the signal processing unit 31 operates based on generating a clock signal obtained by multiplying the reference clock signal CLKR by a PLL circuit provided therein, and performing various processes based on the clock signal. Further, the signal processing unit 31 generates control data DA0 for the receiving circuit 1.

  The frequency dividing circuit 32 divides the reference clock signal CLKR generated by the high-precision clock signal generation unit 4 to generate the second clock signal CLKB. The communication interface circuit 33 generates a serial clock SCL based on the second clock signal CLKB, and generates serial data SDA based on the control data DA0. The communication interface circuit 33 is an interface circuit for performing communication according to the I2C standard, for example.

  Here, since the receiving system according to the first exemplary embodiment has one of the features of the clock correcting unit 10 of the receiving circuit 1, the clock correcting unit 10 will be described in more detail. As shown in FIG. 1, the clock correction unit 10 includes a communication interface circuit 21, a clock edge sampling circuit 22, a phase difference calculation unit 23, a counter 24, a transition determination unit 25, a frequency error calculation unit 26, and a frequency determination unit 27. .

  The communication interface circuit 21 is an interface circuit for communicating with the communication interface circuit 33 of the host IC 2, for example. That is, the communication interface circuit 21 performs communication according to the I2C standard. The communication interface circuit 21 receives the serial data SDA using the serial clock SCL, and supplies the control data DA1 to the circuit included in the clock correction unit 10 or the analog PLL circuit 11 and the digital PLL circuit 13.

  The clock edge sampling circuit 22 detects a clock edge of the serial clock SCL used as an input signal used for calculating the shift amount MOD, and outputs a clock detection signal CLKS indicating that the clock edge has been input. Here, the clock edge is caused by the transition of the logic level of the serial clock. Therefore, in the following, a state in which the clock edge sampling circuit 22 detects that the logic level of the serial clock SCL has transitioned is expressed as a clock edge being input.

  The phase difference calculator 23 operates in synchronization with the first clock signal CLKA, and the clock edge of the second clock signal (for example, the serial clock SCL) can be input in the period of the first clock signal CLKA. A first period (for example, a carry generation period) indicating a characteristic cycle is calculated from the ratio of the first frequency value CLKA_f and the second frequency value CLKB_f. Further, the phase difference calculation unit 23 sets the phase error value P indicating the theoretical value of the time difference between the clock edge of the first clock signal CLKA and the clock edge of the serial clock SCL in the carry generation period to the first frequency value CLKA_f and Calculated from the ratio of the second frequency value CLKB_f.

  In the receiving circuit 1 according to the first exemplary embodiment illustrated in FIG. 1, the phase difference calculation unit 23 includes a first register (for example, the register 231) and a second register (for example, the register 232). The register 231 stores a first frequency value CLKA_f indicating a theoretical value of the frequency of the first clock signal CLKA generated by the low-accuracy clock generation unit 3. The register 232 has a frequency of an input signal (for example, serial clock SCL) having a clock edge synchronized with the clock edge of the second clock signal CLKB generated from the reference clock signal CLKR generated by the high-accuracy clock generation unit 4. The second frequency value CLKB_f indicating the theoretical value is stored.

  Here, an input signal used in the clock correction unit 10 will be described. In the receiving system according to the first embodiment, a serial clock SCL is used as an input signal. The serial clock signal SCL has a frequency equal to or less than half that of the first clock signal CLKA to be corrected. By making such a relationship between the frequency of the first clock signal CLKA and the serial clock SCL, an erroneous determination in a phase difference calculation process described later can be prevented. The input signal may be a signal having a clock edge synchronized with the reference clock signal CLKR supplied to a different semiconductor device (in the receiving system according to the first embodiment, the host IC 2). Therefore, in the receiving system according to the first embodiment, in order to reduce the number of signal lines, a synchronous clock signal (for example, generated based on the second clock signal CLKB generated by dividing the reference clock signal CLKR) (for example, The serial clock signal SCL is used among the serial clock SCL) and a control signal (for example, serial data SDA) having a clock edge synchronized with the serial clock SCL. Note that serial data SDA can also be used as an input signal.

  An example of a specific circuit of the phase difference calculation unit 23 is shown in FIG. As shown in FIG. 2, the phase difference calculation unit 23 includes an adder 41 and a delay circuit 42. The adder 41 outputs an addition value between the previous addition result obtained through the delay circuit 42 and the frequency ratio T. The added value output from the adder 41 becomes the phase error value P. The added value output from the adder 41 has a maximum value of 1, and when the added value is 1 or more, a numerical value after the decimal point is output as the added value. Further, when the added value exceeds 1, the adder 41 sets the carry signal CA to the first logic level. The adder 41 performs an operation every time a clock edge of the first clock signal CLKA is input. The delay circuit 42 delays the addition value output from the adder 41 and outputs the delayed addition value to the adder 41. The phase difference calculation unit 23 has such a configuration, so that the phase error value P and the carry signal CA are updated each time the clock edge of the first clock signal CLKA is input. A period in which carry signal CA is at the first logic level (for example, high level) is a carry generation period.

  The counter 24 generates a transition count value by counting the number of occurrences of a first period (for example, a carry generation period). The counter 24 resets the transition count value by a power-on reset signal generated when the power is turned on.

  The transition determination unit 25 determines whether the clock edge of the input signal (for example, the serial clock SCL) is generated during the first period (for example, the carry generation period) or the second period (for example, the carry non-period) other than the carry generation period. The transition determination signal ST indicating whether it occurred during the occurrence period) is output. More specifically, the transition determination unit 25 sets the transition determination signal ST to the first state (for example, the normal state) when the clock edge of the serial clock SCL is input during the carry generation period. Further, the transition determination unit 25 sets the transition determination signal ST to the second state (for example, an abnormal state) when the clock edge of the serial clock SCL is input during the carry non-occurrence period. Furthermore, the transition determination unit 25 sets the transition determination signal to the third state (for example, the transition non-detection state) when the clock edge of the serial clock SCL is not input. These three states can be expressed by using, for example, a 2-bit signal as a transition determination signal.

  The frequency error calculator 26 calculates a frequency error amount from a theoretical value of the frequency of the first clock signal CLKA based on the transition determination signal ST and the phase error value P. The frequency determination unit 26 determines a direction of deviation from the theoretical value of the phase of the first clock signal CLKA based on the transition determination signal ST, and determines from the theoretical value of the frequency of the first clock signal CLKA based on the phase error value ST. The amount of deviation is calculated. More specifically, after the clock edge of the serial clock SCL is input during the carry generation period, the frequency error calculation unit 26 receives the clock edge of the serial clock SCL during the carry non-occurrence period immediately before the carry generation period. If it is, it is determined that the phase of the first clock signal CLKA is advanced with respect to the theoretical value. Further, the frequency error calculation unit 26 receives the first clock edge of the serial clock SCL after the clock edge of the serial clock SCL is input during the carry generation period and then when the clock edge of the serial clock SCL is input during the non-carry generation period immediately after the carry generation period. It is determined that the phase of the first clock signal CLKA is delayed from the theoretical value. Then, the frequency error calculation unit 26 divides the value calculated based on the phase error value P for each carry generation period by the transition count value to calculate an error amount from the theoretical value of the frequency of the first clock signal CLKA. . More specific operation of the frequency error calculator 26 will be described later.

  The frequency determination unit 27 calculates a deviation amount from the theoretical value of the frequency of the first clock signal based on the upper limit value and the lower limit value of the frequency error amount calculated by the frequency error calculation unit 26. More specifically, the frequency determination unit 27 determines the upper limit value and the lower limit value when the difference between the upper limit value and the lower limit value of the frequency error amount calculated by the frequency error calculation unit 26 is equal to or less than a predetermined value set in advance. (In Embodiment 1, the center value between the upper limit value and the lower limit value) is calculated as a deviation amount. The shift amount calculated by the frequency determination unit 27 is stored in the register 271. Here, the receiving circuit 1 according to the first embodiment includes an analog PLL circuit 11 and a digital PLL circuit 13 as an internal oscillation circuit that generates an operation signal based on the first clock signal, and has a predetermined function based on the operation signal. As a functional circuit for realizing the above, a tuner unit 12 and a demodulation processing unit 14 are provided. The frequency determination unit 27 corrects the frequency of the operation signal by applying the calculated deviation amount to the internal oscillation circuit.

  Next, a difference between the phase of the first clock signal CLKA and the phase of the serial clock SCL will be described. FIG. 3 shows a timing chart for explaining the operation of the receiving circuit 1 according to the first embodiment. FIG. 3 shows the first clock signal CLKA having three phases with respect to the serial clock SCL. First, the first clock signal CLKA indicated by [1] has the same phase as the ideal phase, and the first clock signal CLKA indicated by [2] The first clock signal CLKA indicated by [3] has a phase delayed from the ideal phase. That is, the first clock signal CLKA indicated by [1] has an ideal frequency, and the first clock signal CLKA indicated by [2] has a higher frequency than the ideal frequency. The first clock signal CLKA indicated by [3] has a frequency lower than the ideal frequency.

  In the example shown in FIG. 3, the ratio between the first frequency value CLKA_f indicating the theoretical value of the frequency of the first clock signal CLKA and the second frequency value CLKB_f indicating the theoretical value of the frequency of the serial clock SCL. This shows the case where is 0.11. Further, in the example shown in FIG. 3, the phase error value P calculated by the phase difference calculation unit 23, the carry generation period and the carry non-occurrence period are shown.

  As shown in FIG. 3, if the frequency of the first clock signal CLKA is the same as the theoretical value, the clock edge of the serial clock SCL is input during the carry generation period. On the other hand, when the frequency of the first clock signal CLKA is higher or lower than the theoretical value, there is a possibility that the clock edge of the serial clock SCL is input during the carry non-occurrence period.

  The probability that the clock edge of the serial clock SCL is input during the carry non-occurrence period differs depending on the magnitude of the frequency error amount from the theoretical value of the frequency of the first clock signal CLKA. The clock correction unit 10 calculates the frequency error amount of the first clock signal CLKA based on the relationship between the input timing of the clock edge of the serial clock SCL and the carry generation period and the magnitude of the phase error value P.

  Therefore, a method for calculating the frequency error amount in the frequency error calculator 26 will be described in detail. FIG. 4 illustrates a frequency error amount when the clock edge of the input signal is input during the carry generation period. As shown in FIG. 4, when there is a theoretical transition timing of the serial clock SCL in the first half of the carry generation period and the clock edge of the serial clock SCL is input during the carry generation period, the frequency error calculation unit 26 Calculates a value (Δt1 / n) obtained by dividing a value (Δt1 = 1−P) obtained by subtracting the phase error value P at the start of the carry generation period from 1 as a frequency error amount by the transition count value n. In this case, it can be determined that a frequency error of + Δt1 / n or less has occurred.

  Next, FIG. 5 is a diagram for explaining the frequency error amount when the clock edge of the input signal is input during the carry non-occurrence period immediately before the carry generation period. As shown in FIG. 5, when the clock edge of the serial clock SCL is input in the carry generation period immediately before the carry generation period, the frequency error calculator 26 uses the phase error value P at the start of the carry generation period. As a frequency error amount, a value (Δt2 / n) obtained by dividing a value obtained by subtracting the phase error value P from 1 (Δt2 = 1−P) by the transition count value n is calculated. In this case, it can be determined that a frequency error of + Δt2 / n or more has occurred.

  Next, FIG. 6 is a diagram for explaining the frequency error amount when the clock edge of the input signal is input during the carry generation period. As shown in FIG. 6, when there is a theoretical transition timing of the serial clock SCL in the second half of the carry generation period and the clock edge of the serial clock SCL is input during the carry generation period, the frequency error calculation unit 26 Calculates a value (Δt3 / n) obtained by dividing the phase error value P (Δt3 = P) at the end of the carry generation period by the transition count value n as the frequency error amount. In this case, it can be determined that a frequency error of −Δt3 / n or less has occurred.

  Next, FIG. 7 is a diagram for explaining the frequency error amount when the clock edge of the input signal is input during the carry non-occurrence period immediately after the carry generation period. As shown in FIG. 7, when the clock edge of the serial clock SCL is input in the carry generation period immediately after the carry generation period, the frequency error calculation unit 26 uses the phase error value at the end of the carry generation period as the frequency error amount. A value (Δt4 / n) obtained by dividing P (Δt4 = P) by the transition count value n is calculated. In this case, it can be determined that a frequency error of −Δt4 / n or more has occurred.

  Note that the frequency error calculation unit 26 does not calculate the frequency error value when the serial clock SCL is not input during the carry occurrence period and the carry non-occurrence periods before and after the carry occurrence period.

  Next, a calculation method of the shift amount MOD based on the frequency error value calculated by the above calculation method will be described. In the above calculation method, the value calculated by the phase error value P is divided by the transition count value n. That is, the frequency error amount calculated by the frequency error calculation unit 26 has a feature that it decreases as the transition count value n increases. As described with reference to FIGS. 4 to 7, the frequency error calculation unit 26 indicates whether the actual frequency error is greater than or less than the calculated frequency error value. For this reason, the frequency error value converges in a predetermined range by repeatedly calculating the frequency error value in the frequency error calculation unit 26. Therefore, the frequency determination unit 27 calculates the center value of the frequency error value range at the time when the upper limit value and the lower limit value of the frequency error value range converge to a predetermined range as a deviation amount. FIG. 8 to FIG. 10 are diagrams for explaining the deviation amounts calculated by the semiconductor device according to the first embodiment. 8 to 10, it is assumed that time elapses in the vertical direction.

  FIG. 8 is a diagram for explaining the amount of deviation calculated by the semiconductor device according to the first embodiment when the frequency of the serial clock SCL is an ideal value. As shown in FIG. 8, at the timing (a), the frequency determination unit 27 acquires the frequency error value X1 calculated at that time. In FIG. 8, the frequency error value X1 calculated at the timing (a) has a magnitude of Δt1 / na.

  Subsequently, at timing (b), the frequency determination unit 27 acquires the frequency error value X2 calculated at that time. In FIG. 8, the frequency error value X1 calculated at the timing (b) has a magnitude of Δt1 / nb. Thereby, the range of X2 to X1 is calculated as the range of the frequency error value. At this timing (b), since the size of the range of the frequency error value is larger than the predetermined range X set in advance, the clock correction unit 10 continues the shift amount calculation process.

  Subsequently, at timing (c), the frequency determination unit 27 acquires the frequency error value X3 calculated at that time. In FIG. 8, the frequency error value X3 calculated at the timing (c) has a magnitude of Δt1 / nc. Thereby, the range of X2 to X3 is calculated as the range of the frequency error value. The frequency error value X3 is smaller than the frequency error value X1 calculated at the timing (a) because the transition count value n is larger than the timing (a). At this timing (c), since the size of the range of the frequency error value is larger than the predetermined range X set in advance, the clock correction unit 10 continues the shift amount calculation process.

  Subsequently, at the timing (d), the frequency determination unit 27 acquires the frequency error value X4 calculated at that time. In FIG. 8, the frequency error value X4 calculated at the timing (d) has a magnitude of Δt3 / nd. The frequency error value X4 is smaller than the frequency error value X2 calculated at the timing (b) because the transition count value n is larger than the timing (b). At this timing (d), the frequency error value range is equal to or smaller than a predetermined range X set in advance, so that the clock correction unit 10 stops the deviation amount calculation process and sets the magnitude of the deviation amount MOD. Determine. In the example shown in FIG. 8, since the center value of the frequency error value range (X4 to X3) is 0 ppm, the amount of deviation from the theoretical value of the first clock signal CLKA is calculated as 0 ppm.

  Next, FIG. 9 is a diagram for explaining a deviation amount calculated by the semiconductor device according to the first embodiment when the frequency of the serial clock SCL is higher than an ideal value. As shown in FIG. 9, at the timing (a), the frequency determination unit 27 acquires the frequency error value X1 calculated at that time. In FIG. 9, the frequency error value X1 calculated at the timing (a) has a magnitude of Δt1 / na.

  Subsequently, at timing (b), the frequency determination unit 27 acquires the frequency error value X2 calculated at that time. In FIG. 9, the frequency error value X1 calculated at the timing (b) has a magnitude of Δt3 / nb. Thereby, the range of X2 to X1 is calculated as the range of the frequency error value. At this timing (b), since the size of the range of the frequency error value is larger than the predetermined range X set in advance, the clock correction unit 10 continues the shift amount calculation process.

  Subsequently, at timing (c), the frequency determination unit 27 acquires the frequency error value X3 calculated at that time. In FIG. 9, the frequency error value X3 calculated at the timing (c) has a magnitude of Δt2 / nc. At this timing (c), the clock edge of the serial clock SCL is input in the carry non-occurrence period immediately before the carry generation period. Therefore, it is recognized that the frequency of the first clock signal CLKA is highly shifted due to the frequency error value calculated at the timing (c). Thereby, the range of X3 to X1 is calculated as the range of the frequency error value. The frequency error value X3 is smaller than the frequency error value X1 calculated at the timing (a) because the transition count value n is larger than the timing (a). At this timing (c), since the size of the range of the frequency error value is larger than the predetermined range X set in advance, the clock correction unit 10 continues the shift amount calculation process. Further, since it is recognized that the frequency of the first clock signal CLKA is higher than the theoretical value at the timing (c), the frequency error calculation unit 26 and the frequency determination unit 27 thereafter have a high frequency of the clock signal CLKA. The calculation proceeds on the assumption that the direction is deviated.

  Subsequently, at the timing (d), the frequency determination unit 27 acquires the frequency error value X4 calculated at that time. In FIG. 9, the frequency error value X4 calculated at timing (d) has a magnitude of Δt1 / nd. The frequency error value X4 is smaller than the frequency error value X1 calculated at the timing (a) because the transition count value n is larger than the timing (a). At this timing (d), the frequency error value range is equal to or smaller than a predetermined range X set in advance, so that the clock correction unit 10 stops the deviation amount calculation process and sets the magnitude of the deviation amount MOD. Determine. In the example shown in FIG. 9, since the center value of the frequency error value range (X3 to X4) is + Yppm, the amount of deviation from the theoretical value of the first clock signal CLKA is calculated as + Yppm.

  Next, FIG. 10 is a diagram for explaining a deviation amount calculated by the semiconductor device according to the first embodiment when the frequency of the serial clock SCL is lower than the ideal value. As shown in FIG. 10, at the timing (a), the frequency determination unit 27 acquires the frequency error value X1 calculated at that time. In FIG. 10, the frequency error value X1 calculated at the timing (a) has a magnitude of Δt1 / na.

  Subsequently, at timing (b), the frequency determination unit 27 acquires the frequency error value X2 calculated at that time. In FIG. 10, the frequency error value X2 calculated at the timing (b) has a magnitude of Δt3 / nb. Thereby, the range of X2 to X1 is calculated as the range of the frequency error value. At this timing (b), since the size of the range of the frequency error value is larger than the predetermined range X set in advance, the clock correction unit 10 continues the shift amount calculation process.

  Subsequently, at timing (c), the frequency determination unit 27 acquires the frequency error value X3 calculated at that time. In FIG. 10, the frequency error value X3 calculated at the timing (c) has a magnitude of Δt4 / nc. At this timing (c), the clock edge of the serial clock SCL is input in the carry non-occurrence period immediately after the carry generation period. For this reason, it is recognized that the frequency of the first clock signal CLKA is shifted low due to the frequency error value calculated at the timing (c). Thereby, the range of X3 to X2 is calculated as the range of the frequency error value. The frequency error value X3 is smaller than the frequency error value X1 calculated at the timing (a) because the transition count value n is larger than the timing (a). At this timing (c), since the size of the range of the frequency error value is larger than the predetermined range X set in advance, the clock correction unit 10 continues the shift amount calculation process. Further, since it is recognized that the frequency of the first clock signal CLKA is lower than the theoretical value at the timing (c), the frequency error calculation unit 26 and the frequency determination unit 27 thereafter have a low frequency of the clock signal CLKA. The calculation proceeds on the assumption that the direction is deviated.

  Subsequently, at the timing (d), the frequency determination unit 27 acquires the frequency error value X4 calculated at that time. In FIG. 10, the frequency error value X4 calculated at timing (d) has a magnitude of Δt3 / nd. The frequency error value X4 is smaller than the frequency error value X2 calculated at the timing (b) because the transition count value n is larger than the timing (b). At this timing (d), the frequency error value range is equal to or smaller than a predetermined range X set in advance, so that the clock correction unit 10 stops the deviation amount calculation process and sets the magnitude of the deviation amount MOD. Determine. In the example shown in FIG. 10, since the center value of the frequency error value range (X3 to X4) is −Yppm, the amount of deviation from the theoretical value of the first clock signal CLKA is calculated as −Yppm.

  From the above description, in the receiving circuit 1 according to the first embodiment, the clock correction unit 10 generates the clock of the serial clock SCL based on the theoretical value of the frequency set in advance based on the first clock signal CLKA supplied to the semiconductor device. The carry generation period in which the edge is input is calculated. That is, the carry generation period calculated by the clock correction unit 10 varies in time according to the frequency of the first clock signal CLKA, and the length of the period changes. Further, the clock correction unit 10 determines whether the clock edge of the serial clock SCL generated based on the second clock signal CLKB, which is more accurate than the first clock signal CLKA, is input during the carry generation period or during the carry non-generation period. Recognize whether it was entered. The clock correction unit 10 calculates a frequency error range based on the input timing of the serial clock SCL, the phase error value P calculated during the carry generation period, and the transition count value n, and Based on the range, a deviation MOD from the theoretical value of the frequency of the first clock signal CLKA is calculated.

  As a result, the receiving circuit 1 according to the first embodiment calculates the shift amount MOD at an early stage based on the serial clock SCL generated inside the receiving system without waiting for a received signal input to the tuner unit or the like. Can do. In addition, the receiving circuit 1 can correct the frequency of the operation signal generated by the analog PLL circuit 11 and the digital PLL circuit 13 based on the deviation amount.

  On the other hand, the first clock signal is obtained by comparing the number of clocks of the reference signal generated in another semiconductor device such as the host IC 2 used together with the receiving circuit 1 and the first clock signal CLKA supplied to the receiving circuit 1. The error of CLKA can also be calculated. However, in this case, since the number of clocks is 100,000 in order to detect an error of 10 ppm, the frequency shift amount of the first clock signal CLKA is calculated as fast as the receiving circuit 1 according to the first embodiment. I can't.

  In addition, when a reference signal is separately received from another semiconductor device and the frequency shift amount of the first clock signal CLKA is calculated based on a difference in the number of clocks between the reference signal and the first clock signal CLKA, the receiving system There arises a problem that the number of terminals of the signal line and the receiving circuit 1 increases. However, the receiving circuit 1 according to the first embodiment uses the serial clock SCL used as one of the signals used for transmission of the control signal as a highly accurate input signal used for calculating the shift amount MOD. Thereby, since the receiving circuit 1 according to the first embodiment does not need to separately prepare a signal line for transmitting an input signal, it is possible to reduce the base area of the receiving system and the number of terminals of the semiconductor device.

  In addition, when calculating the frequency shift amount of the first clock signal CLKA by comparing the number of clocks, it is necessary to transmit a clock signal having the same frequency as the first clock signal CLKA as a reference signal. In this case, the frequency of the reference signal tends to increase, and there arises a problem that unnecessary radiation of the receiving system increases. However, in the receiving system according to the first embodiment, the serial clock SCL used for calculating the frequency shift amount in the receiving circuit 1 is a frequency that is half or less of the frequency of the first clock signal CLKA. More specifically, the frequency of the first clock signal CLKA is about 28 MHz, and the frequency of the serial clock SCL is about 400 Hz. For this reason, in the receiving system according to the first embodiment, it is possible to set the frequency of the input signal used for calculating the deviation amount to be low and suppress unnecessary radiation.

  In the receiving circuit 1 according to the first embodiment, the frequency of the serial clock SCL used for calculating the deviation amount is set to be equal to or less than half the frequency of the first clock signal CLKA, so that the serial clock SCL transitions. It is possible to prevent the theoretical value of the generated timing from randomly jumping from the first half to the second half of the carry generation period or from the second half to the first half. It is difficult to recognize whether the frequency of the first clock signal CLKA is high or low when the theoretical value of the timing at which the serial clock SCL transition occurs randomly jumps from the first half to the second half or from the second half to the first half. There is a problem to become.

  In addition, when a reference signal generated by another semiconductor device such as the host IC 2 is received and a clock signal or the like used in the receiving circuit 1 is generated based on the reference signal, the reference is generated due to the influence of power supply fluctuation in the host IC 2. In the signal generation process, the jitter characteristics of the reference signal may be deteriorated. However, the receiving circuit 1 according to the first embodiment calculates the shift amount MOD from the theoretical value of the frequency of the supplied first clock signal CLKA, and generates a clock signal or the like generated internally based on the shift amount MOD. Can be corrected. Thereby, in the receiving system according to the first embodiment, a low-accuracy clock generation element such as a ceramic oscillator can be used as a clock generation unit that generates the first clock signal CLKA. This ceramic oscillator can generate a clock signal having a good jitter characteristic although the accuracy with respect to the absolute value of the frequency is low. That is, in the receiving system according to the first embodiment, by using such a clock generation unit, it is possible to improve the jitter characteristics of the clock signal generated by the analog PLL circuit 11 and the digital PLL circuit 13. The reception characteristic can be improved by supplying a low jitter operation signal (for example, a local signal) to a tuner or the like of the reception system.

  When a reference signal generated by another semiconductor device such as the host IC 2 is received and a clock signal or the like used in the receiving circuit 1 is generated based on the reference signal, the reference signal is generated in the other semiconductor device. An oscillation circuit or the like is required. However, by using the receiving circuit 1 according to the first embodiment, it is not necessary to separately provide an oscillation circuit or the like for generating a reference signal in another semiconductor device. That is, by using the receiving circuit 1 according to the first embodiment, the circuit area of another semiconductor device can be reduced.

  In addition, if a clock signal used in the receiver circuit 1 is generated based on a reference signal supplied from another semiconductor device, etc., stopping either circuit will stop the entire receiver system. Therefore, power consumption cannot be reduced by stopping one of the circuits. However, in the receiving system according to the first embodiment, after calculating the shift amount MOD, the receiving circuit 1 and the host IC 2 operate based on the clock signals generated by the independent clock generating units. Therefore, in the receiving system according to the first embodiment, it is possible to stop one of the circuits and operate only the necessary circuit to reduce the power consumption of the receiving system.

Embodiment 2
In the second embodiment, a mode will be described in which serial data SDA is used as an input signal used by the clock correction unit to calculate the shift amount MOD. FIG. 11 is a block diagram of a receiving system including the receiving circuit 1a according to the second embodiment. In the description of the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the description thereof is omitted.

  As illustrated in FIG. 11, the reception circuit 1a includes a clock correction unit 10a instead of the clock correction unit 10 of the reception circuit 1 according to the first embodiment. The clock correction unit 10a includes a clock edge sampling circuit 22a instead of the clock edge sampling circuit 22 of the clock correction unit 10 according to the first embodiment. Then, the clock edge sampling circuit 22a detects a clock edge of the serial data SDA used as an input signal used for calculating the shift amount MOD, and outputs a clock detection signal CLKS indicating that the clock edge is input.

  That is, in the receiving circuit 1a according to the second embodiment, serial data SDA generated based on the second clock signal CLKB is used as an input signal in the same manner as the serial clock SCL. The shift amount MOD can be calculated by the same arithmetic processing as the circuit 1.

Embodiment 3
In the third embodiment, a mode will be described in which the clock correction unit uses the second clock signal CLKB as an input signal used to calculate the shift amount MOD. FIG. 12 is a block diagram of a receiving system including the receiving circuit 1b according to the third embodiment. In the description of the third embodiment, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the description thereof is omitted.

  As illustrated in FIG. 12, the reception circuit 1b includes a clock correction unit 10b instead of the clock correction unit 10 of the reception circuit 1 according to the first embodiment. The clock correction unit 10b includes a clock edge sampling circuit 22b instead of the clock edge sampling circuit 22 of the clock correction unit 10 according to the first embodiment. Then, the clock edge sampling circuit 22b detects a clock edge of the second clock signal CLKB used as an input signal used for calculating the shift amount MOD, and outputs a clock detection signal CLKS indicating that the clock edge has been input. .

  That is, in the receiving circuit 1b according to the third embodiment, the second clock signal CLKB used for generating the serial clock SCL is used as an input signal, and the same calculation as that performed by the receiving circuit 1 according to the first embodiment. The shift amount MOD can be calculated by the processing.

  In the receiving circuit 1b according to the third embodiment, it is necessary to newly add a signal line for transmitting the second clock signal CLKB. However, the second clock signal CLKB having a frequency higher than that of the serial clock SCL is used. By using it, the shift amount MOD can be calculated faster than the receiving circuit 1 according to the first embodiment. Note that the second clock signal CLKB has a frequency equal to or lower than one half of the frequency of the first clock signal CLKA, and therefore, unnecessary radiation can be reduced as in the first embodiment. .

Embodiment 4
In the fourth embodiment, a description will be given of a mode in which arithmetic processing in the clock correction unit 10 is performed by executing a frequency error calculation program in an arithmetic circuit. FIG. 13 is a block diagram of a receiving system including the receiving circuit 1c according to the fourth embodiment. In the description of the fourth embodiment, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the description thereof is omitted.

  As illustrated in FIG. 13, the reception circuit 1 c includes a clock correction unit 50 instead of the clock correction unit 10 according to the first embodiment. The clock correction unit 50 includes an arithmetic circuit 51 that implements a phase difference calculation unit 23, a counter 24, a transition determination unit 25, a frequency error calculation unit 26, and a frequency determination unit 27 by a frequency error calculation program. The clock correction unit 50 also includes a program storage unit 52 that stores a frequency error calculation program executed by the arithmetic circuit 51. The clock correction unit 50 also includes a communication interface circuit 21 and a clock edge sampling circuit 22.

  Note that the receiving circuit 1c according to the fourth embodiment includes the first register (for example, the register 231) and the second register (for example, the register 232) in the clock correction unit 50 as in the first embodiment. . The register 231 stores a first frequency value indicating a theoretical value of the first clock signal CLKA generated by the first clock generation unit (for example, the low-accuracy clock signal generation unit 3). In the register 232, the second clock signal generated by the second clock generation unit (for example, the high-accuracy clock signal generation unit 4) having higher frequency absolute value accuracy than the low-accuracy clock signal generation unit 3 is stored. A second frequency value indicating the theoretical value of the frequency of the input signal having a clock edge synchronized with the clock edge of the second clock signal CLKB is stored. The arithmetic circuit 51 performs arithmetic processing based on the first clock signal CLKA.

  The arithmetic circuit 51 calculates the amount of deviation from the theoretical value of the frequency of the first clock signal based on the frequency error calculation program. More specifically, the arithmetic circuit 51 synchronizes with the first clock signal CLKA, and indicates a cycle in which the clock edge of the serial clock SCL may be input in the cycle of the first clock signal CLKA. One period (for example, a carry generation period) is calculated from the ratio of the first frequency value and the second frequency value. This process is an arithmetic process equivalent to the process in the phase difference calculation unit 23 according to the first embodiment. The arithmetic circuit 51 uses the phase error value P indicating the theoretical value of the time difference between the clock edge of the first clock signal CLKA and the clock edge of the serial clock SCL in the carry generation period as the first frequency value CLKA_f and the second frequency value. Calculated from the ratio of CLKB_f. This process is an arithmetic process equivalent to the process in the phase difference calculation unit 23 according to the first embodiment. The arithmetic circuit 51 determines whether the clock edge of the serial clock SCL has occurred during the carry generation period or during the second period other than the carry generation period (for example, the carry non-occurrence period), and the transition determination value ST Is generated. This process is an arithmetic process equivalent to the process in the transition determination unit 25 according to the first embodiment. The arithmetic circuit 51 calculates a frequency error amount from a theoretical value of the frequency of the first clock signal CLKA based on the transition determination value ST and the phase error value P. This process is an arithmetic process equivalent to the process in the frequency error calculator 26 according to the first embodiment. The arithmetic circuit 51 calculates a deviation MOD from the theoretical value of the frequency of the first clock signal CLKA based on the upper limit value and the lower limit value of the frequency error amount. This process is equivalent to the frequency determination unit 27 according to the first embodiment. Also in the fourth embodiment, the shift amount MOD is stored in the register 271.

  The arithmetic circuit 51 that executes the frequency error calculation program determines the direction of deviation of the phase of the first clock signal CLKA from the theoretical value based on the transition determination signal ST, and determines the first clock signal based on the phase error value P. The frequency error amount from the theoretical value of the frequency of CLKA is calculated. This process is an arithmetic process equivalent to the process in the frequency error calculator 26 according to the first embodiment.

  In addition, the arithmetic circuit 51 that executes the frequency error calculation program counts the number of occurrences of the carry generation period to generate a transition count value. Then, the arithmetic circuit 51 divides the phase error value P by the transition count value n for each carry generation period to calculate a frequency error amount from the theoretical value of the frequency of the first clock signal. This processing is equivalent to the processing in the counter 24 and the frequency error calculation unit 26 according to the first embodiment.

  In addition, the arithmetic circuit 51 that executes the frequency error calculation program sets the clock edge of the serial clock SCL in the carry non-occurrence period immediately before the carry generation period after the clock edge of the serial clock SCL is input during the carry generation period. If it is input, it is determined that the phase of the first clock signal CLKA is advanced with respect to the theoretical value. The calculation group 51 determines that the phase of the first clock signal CLKA is delayed from the theoretical value when the clock edge of the serial clock SCL is input in the carry non-occurrence period immediately after the carry generation period. To do. This process is an arithmetic process equivalent to the process of the frequency error calculation unit 26 according to the first embodiment.

  The arithmetic circuit 51 that executes the frequency error calculation program has an upper limit value when the difference between the upper limit value and the lower limit value of the frequency error amount calculated by the frequency error calculation unit 26 is equal to or less than a predetermined value set in advance. A value between the lower limit value and the lower limit value is calculated as the deviation amount. This process is an arithmetic process equivalent to the process of the frequency determination unit 27 according to the first embodiment.

  The arithmetic circuit 51 that executes the frequency error calculation program sets the transition determination signal ST to the first state (for example, the normal state) when the clock edge of the serial clock SCL is input during the carry generation period. The arithmetic circuit 51 sets the transition determination signal ST to the second state (for example, an abnormal state) when the clock edge of the serial clock SCL is input during the carry non-occurrence period. Further, the arithmetic circuit 51 sets the transition determination signal to the third state (for example, the transition non-detection state) when the clock edge of the serial clock SCL is not input. This process is an arithmetic process equivalent to the process of the transition determination unit 25 according to the first embodiment.

  Then, the arithmetic circuit 51 that executes the frequency error calculation program corrects the frequency of the operation signal by giving the calculated shift amount MOD to the analog PLL circuit 11 and the digital PLL circuit 13. This process is an arithmetic process equivalent to the process of the frequency determination unit 27 according to the first embodiment.

  From the above description, the processing in the clock correction unit 10 according to the first embodiment can also be realized by arithmetic processing using software such as a frequency error calculation program. As described above, by performing the processing of the clock correction unit 10 by software, the receiving circuit 1 according to the first embodiment can be realized by a semiconductor device including a CPU core and the like.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible. For example, the clock correction unit 10 can be incorporated in the host IC 2. In this case, a high-accuracy clock signal generation unit 4 is provided on the receiving circuit 1 side, and a corrected clock signal generation unit 3 is provided on the host IC 2 side.

1, 1a, 1b, 1c Receiver circuit 2 Host IC
DESCRIPTION OF SYMBOLS 3 Low precision clock signal generation part 4 High precision clock signal generation part 10, 10a, 10b, 10c, 50 Clock correction part 11 Analog PLL circuit 12 Tuner part 13 Digital PLL circuit 14 Demodulation processing part 21 Communication interface circuit 22 Clock edge sampling circuit 23 phase difference calculation unit 231 register 232 register 24 counter 25 transition determination unit 26 frequency error calculation unit 27 frequency determination unit 271 register 31 signal processing unit 32 frequency divider circuit 33 communication interface circuit 41 adder 42 delay circuit 51 arithmetic circuit 52 program storage Part CA carry signal P phase error value n transition count value ST transition determination signal DA1 control data SCL serial clock SDA serial data CLKA first clock signal CLKB second clock Click signal CLKR the reference clock signal

Claims (20)

A first register that stores a first frequency value indicating a theoretical value of the first clock signal generated by the first clock generation unit;
The theoretical value of the frequency of the input signal having a clock edge synchronized with the clock edge of the second clock signal generated by the second clock generator having a higher absolute frequency accuracy than that of the first clock generator. A second register for storing a second frequency value;
A first period that operates in synchronization with the first clock signal and indicates a period in which a clock edge of the input signal may be input, among the periods of the first clock signal; A phase error value indicating a theoretical value of a time difference between the clock edge of the first clock signal and the clock edge of the input signal in a period is calculated from the ratio of the first frequency value and the second frequency value. A phase difference calculator to
A transition determination unit that outputs a transition determination signal indicating whether a clock edge of the input signal occurred during the first period or a second period other than the first period;
A frequency error calculation unit that calculates a frequency error amount from a theoretical value of the frequency of the first clock signal based on the transition determination signal and the phase error value;
A frequency determination unit that calculates a deviation amount from a theoretical value of the frequency of the first clock signal based on an upper limit value and a lower limit value of the frequency error amount;
A semiconductor device.   2. The semiconductor device according to claim 1, wherein the input signal has a frequency equal to or less than a half of a frequency of the first clock signal.   2. The input signal is any one of a synchronous clock signal generated based on the second clock signal in a different semiconductor device and a control signal having a clock edge synchronized with the synchronous clock signal. The semiconductor device described.   The frequency error calculation unit determines a deviation direction from the theoretical value of the phase of the first clock signal based on the transition determination signal, and based on the theoretical value of the frequency of the first clock signal based on the phase error value. The semiconductor device according to claim 1, wherein the shift amount is calculated. A counter that counts the number of occurrences of the first period and generates a transition count value;
The frequency error calculation unit divides a value calculated based on the phase error value for each first period by the transition count value and the frequency error amount with a theoretical value of the frequency of the first clock signal. The semiconductor device according to claim 1, wherein:   In the frequency error calculation unit, after the clock edge of the input signal is input during the first period, the clock edge of the input signal is input during the second period immediately before the first period. In the case, it is determined that the phase of the first clock signal is advanced with respect to the theoretical value, and the clock edge of the input signal is input in the second period immediately after the first period. The semiconductor device according to claim 1, wherein it is determined that the phase of the first clock signal is delayed with respect to a theoretical value.   The transition determination unit sets the transition determination signal to the first state when the clock edge of the input signal is input during the first period, and the clock edge of the input signal is input during the second period. 2. The semiconductor device according to claim 1, wherein the transition determination signal is set to a second state in a case, and the transition determination signal is set to a third state when a clock edge of the input signal is not input.   The frequency determination unit calculates a value between the upper limit value and the lower limit value when the difference between the upper limit value and the lower limit value of the frequency error amount is equal to or less than a predetermined value set in advance. The semiconductor device according to claim 1, calculated as: An internal oscillation circuit for generating an operation signal based on the first clock signal;
And a functional circuit that realizes a predetermined function based on the operation signal,
The semiconductor device according to claim 1, wherein the frequency determination unit corrects the frequency of the operation signal by giving the calculated shift amount to the internal oscillation circuit. The first clock generation unit generates a clock signal generated by a ceramic oscillator as the first clock signal,
The semiconductor device according to claim 1, wherein the second clock generation unit generates the second clock signal based on a clock signal generated by a crystal oscillator. A first register that stores a first frequency value indicating a theoretical value of the first clock signal generated by the first clock generation unit;
The theoretical value of the frequency of the input signal having a clock edge synchronized with the clock edge of the second clock signal generated by the second clock generator having a higher absolute frequency accuracy than that of the first clock generator. A second register for storing a second frequency value;
A frequency error calculation program that is executed by the arithmetic circuit in a semiconductor device having an arithmetic circuit that performs arithmetic processing based on the first clock signal, and calculates a deviation amount from a theoretical value of the frequency of the first clock signal Because
In synchronization with the first clock signal, a first period indicating a period in which a clock edge of the input signal may be input is included in the period of the first clock signal. Calculated from the ratio of the second frequency values;
A phase error value indicating a theoretical value of a time difference between the clock edge of the first clock signal and the clock edge of the input signal in the first period is calculated from the ratio of the first frequency value and the second frequency value. Calculate
Determining whether a clock edge of the input signal occurred during the first period or a second period other than the first period to generate a transition determination value;
Calculating a frequency error amount from a theoretical value of the frequency of the first clock signal based on the transition determination value and the phase error value;
A frequency error calculation program for calculating the deviation amount from a theoretical value of the frequency of the first clock signal based on an upper limit value and a lower limit value of the frequency error amount.   The frequency error calculation program according to claim 11, wherein the input signal has a frequency equal to or lower than a half of the frequency of the first clock signal.   12. The input signal is any one of a synchronous clock signal generated based on the second clock signal in a different semiconductor device and a control signal having a clock edge synchronized with the synchronous clock signal. The frequency error calculation program described.   The frequency error calculation program determines a deviation direction from the theoretical value of the phase of the first clock signal based on the transition determination signal, and based on the theoretical value of the frequency of the first clock signal based on the phase error value. The frequency error calculation program according to claim 11, wherein the frequency error amount is calculated. The frequency error calculation program is
Counting the number of occurrences of the first period to generate a transition count value,
The frequency error calculation program according to claim 11, wherein the frequency error amount is calculated by dividing the phase error value by the transition count value for each first period and the theoretical value of the frequency of the first clock signal. .   In the frequency error calculation program, after the clock edge of the input signal is input during the first period, the clock edge of the input signal is input during the second period immediately before the first period. In the case, it is determined that the phase of the first clock signal is advanced with respect to the theoretical value, and the clock edge of the input signal is input in the second period immediately after the first period. The frequency error calculation program according to claim 11, wherein the phase of the first clock signal is determined to be delayed from the theoretical value.   The frequency error calculation program calculates a deviation between a value between the upper limit value and the lower limit value when a difference between the upper limit value and the lower limit value of the frequency error amount is equal to or less than a predetermined value set in advance. The semiconductor device according to claim 11, wherein the semiconductor device is calculated as a quantity.   The frequency error calculation program sets the transition determination value to the first state when the clock edge of the input signal is input during the first period, and inputs the clock edge of the input signal during the second period. The frequency error calculation program according to claim 11, wherein the transition determination value is set to the second state in this case, and the transition determination value is set to the third state when the clock edge of the input signal is not input. The semiconductor device includes:
An internal oscillation circuit for generating an operation signal based on the first clock signal;
And a functional circuit that realizes a predetermined function based on the operation signal,
The frequency error calculation program according to claim 11, wherein the frequency error calculation program corrects the frequency of the operation signal by giving the calculated shift amount to the internal oscillation circuit. The first clock generation unit generates a clock signal generated by a ceramic oscillator as the first clock signal,
The frequency error calculation program according to claim 11, wherein the second clock generation unit generates the second clock signal based on a clock signal generated by a crystal oscillator.

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