JP2019121927A - Clock switching device - Google Patents

Abstract

To provide a clock switching device capable of suppressing variations of an output frequency of a PLL circuit when switching a clock into a second clock due to interruption of an input of a first clock.SOLUTION: A clock switching device provides first and second multiplication circuits 1 and 2 each of multiplying first and second clocks, and switches an output of the first multiplication circuit 1 in to the output of the second multiplication circuit 2 by a selection circuit 5 when detecting interruption of the first clock by a clock detection circuit 4. A divider circuit 6 dividing a clock output from the selection circuit 5 into 1/n, which includes a counter and is based on a counter value counted in a post step of the selection circuit 5.SELECTED DRAWING: Figure 1

Description

The present invention relates to an apparatus which switches to the other of one of a first clock and a second clock when the clock is cut off.

  For example, in a base station that emits a broadcast wave, a carrier wave is generated by a clock (clock signal) via, for example, DDS (Direct Digital Synthesizer), and modulation is performed by a baseband signal such as OFDM (Orthogonal Frequency Division Multiplexing), for example. It is sending. The clock used in this system is, for example, a PLL (Phase Locked Loop) circuit using a clock distributed from a VCXO (Voltage Controlled Crystal Oscillator) as a reference clock, which is provided in a host system in a base station. An output signal is used.

Also, if the output frequency of VCXO changes due to the environmental temperature, problems such as distortion of the video and audio to be transmitted will occur, so an extremely stable frequency clock distributed from outside the base station, for example, Rb (rubidium) oscillator The frequency of the output clock (high stability clock) is compared with the frequency of the clock output from the VCXO, and the frequency difference is transmitted to the baseband modulation unit. In the baseband modulation unit, the read clock of the DDS is corrected by the frequency difference to suppress the influence of the fluctuation of the output frequency of the VCXO.
Then, when the first clock distributed from the VCXO and the second clock which is the above-mentioned high stability clock are input to the selector (selection circuit) and the first clock is interrupted (when the circuit is turned off) ) Is switched to the second clock by the selector so that the operation is not stopped.

  The first clock and the second clock are supplied to the unit including the PLL circuit, the selector, and the like, respectively, through the signal cable for supplying the first clock and the signal cable for supplying the second clock. For this reason, when changing the installation location of the unit, for example, both cables may be disconnected. In that case, the control voltage of VCXO in the PLL circuit is fixed to a predetermined value so that the clock is not interrupted There is. Even if the position of the unit is not changed, if the operator erroneously unplugs the signal cable for supplying the first clock, for example, the first clock is interrupted.

The above-described system has the following problems.
The moment the first clock is interrupted and switched to the second clock, the supply of the reference clock to the PLL circuit is stopped, which causes a phase mismatch in the phase comparison circuit of the PLL circuit and supplies the VCXO. Frequency control signal greatly fluctuates. As a result, the frequency of the operation clock supplied to the baseband modulation unit, which is the output signal of the PLL circuit, also largely fluctuates, and the image signal and the audio signal are significantly degraded.
Also, when the PLL circuit is operated as fixed value control when both clocks are interrupted, the voltage which is fixed value when either clock recovers and the PLL circuit returns from the open loop to the closed loop Frequency pull-in starts again from the value. As a result, the output frequency of the PLL circuit temporarily fluctuates greatly, causing the same problem.

Patent Document 1 describes a technique for switching a clock signal BC from a spare oscillator to a clock signal MC divided by M when a reference clock which is a reference clock of a PLL circuit is cut off. In this technique, the clock signal MC is phase-controlled to the clock signal NC divided by N by the N divider circuit of the PLL circuit.
However, in the technique of Patent Document 1, since the input of the clock signal to the phase comparison circuit 15 is interrupted for a moment when the reference clock signal RC is cut off, the phase of the pulse signal divided by N is out of phase with the original phase. Eventually, the frequency of the output signal of the PLL circuit fluctuates greatly.

Japanese Patent Application Laid-Open No. 6-177754

  The present invention has been made based on such circumstances, and its object is to provide a technique capable of suppressing clock fluctuation when switching to a second clock due to the interruption of the input of the first clock. It is to provide.

A clock switching device according to the present invention comprises: a first multiplication circuit that multiplies a first clock by n (n is an even number);
A second multiplication circuit that multiplies by n the second clock that is switched and used when the first clock is interrupted;
A detection circuit that detects the presence / absence of the first clock, using as an operation clock a detection clock having a frequency twice or more that of the first clock before being multiplied by n;
A detection signal output when the detection circuit detects that the first clock is interrupted causes the output of the first multiplier circuit to run freely after the first clock is interrupted according to a detection signal output from the first multiplication circuit. Select circuit to switch to the output of
A divider which is disposed downstream of the selection circuit and includes a counter that counts pulses output from the selection circuit, and divides the clock output from the selection circuit into 1 / n based on the counted counter value. And a circuit.

  The present invention is provided with a first multiplication circuit and a second multiplication circuit that respectively multiply the first clock and the second clock by n, and the detection circuit detects the disconnection of the first clock by the selection circuit. The output of the multiplier circuit of 1 is switched to the output of the second multiplier circuit. Since the first multiplier circuit is free-running (the multiplied clock is output for a while) even after the first clock which is the input signal is interrupted, it is possible to use the second clock while being free-running. By switching, the clock does not disappear. Since a divider circuit is provided downstream of the selection circuit to divide the clock output from the selection circuit by 1 / n based on the counted value including the counter and the counter, the clock before and after the clock switching is selected. The phase difference is suppressed to be smaller than one cycle of the clock multiplied by n. Therefore, the fluctuation of the clock when the first clock is interrupted and the clock is switched can be suppressed.

FIG. 1 is a block diagram showing an entire configuration of an embodiment of a clock switching device according to the present invention. It is explanatory drawing which shows the relationship between the presence or absence of the clock input into a selector, and the clock selected by a selector. It is a time chart of each part of the clock switching device shown in FIG. It is a time chart which expands and shows a part of time chart shown in FIG.

FIG. 1 is a block diagram showing a broadcasting apparatus including a clock switching device according to an embodiment of the present invention, and the broadcasting apparatus is provided, for example, in a base station for broadcasting. The clock switching device comprises a first multiplication circuit 1 constituting a multiplier that multiplies the first clock by n (n is an even number), and a second clock that is switched and used when the first clock is interrupted. And a second multiplier circuit 2 that constitutes a multiplier that multiplies n by n. In this embodiment, each multiplier circuit 1, 2 is configured to multiply the clock by eight.
The first clock is a signal output from the VCXO provided in the host apparatus of the broadcast device, and is sent to the broadcast device via the signal cable. The second clock is a signal having a higher frequency stability than the first clock, for example, a signal distributed from an Rb oscillator provided outside the base station, and is sent to a broadcast device via a signal cable. In the following description, the first clock may be called a slave synchronous clock.

Reference numeral 31 in FIG. 1 denotes a TCXO, which detects that the first clock and the second clock are interrupted, that is, outputs a detection clock for detecting the interruption of the clock. In this example, since the clock of the TCXO 31 is used as a reference clock of the PLL circuit described later when both the first clock and the second clock are interrupted, the clock of the TCXO 31 has the same frequency as the second clock. It is set. Also, in this example, the frequency stability of the clock of the TCXO 31 to the ambient temperature is inferior to the frequency stability of the first clock.
A third multiplier circuit 3 constitutes a multiplier and is for setting the frequency of the detection clock to at least twice the frequency of the first clock. In this example, the third multiplication circuit 3 is configured to multiply the detection clock by eight. The clock output from the TCXO 31 is referred to as a detection clock before or after multiplication.

  Reference numeral 4 denotes a clock break detection circuit, which takes in a first clock input to the first multiplier circuit 1 and a second clock input to the second multiplier circuit 2 and detects a break in these clocks. It is provided to determine (whether or not the clock is interrupted). The clock disconnection detection circuit 4 uses the detection clock multiplied by 8 by the third multiplication circuit 3 as an operation clock, and determines whether or not the first clock and the second clock are disconnected. Specifically, when the "L" level of the first clock (second clock) continues for five or more clocks of the operation clock, or the first clock (second clock) is at "L" level When it is determined that the first clock (second clock) transitions from the “H” level to the “L” level within four clocks of the operation clock after the transition from “H” to “H” level, it is determined that the clock is disconnected.

  The clock break detection circuit 4 includes, for example, a first clock break detection unit and a second clock break detection unit, each of which comprises a logic circuit, and each clock break detection unit performs clock switching of “0” when there is a clock. The signal is output as a signal, and when there is no clock (when it is disconnected), “1” is output as a clock switching signal. Therefore, “0, 0” (when both the first clock and the second clock are input) from the clock break detection circuit 4 through two bit lines forming a 2-bit signal line, “ 1, 0 "(when the first clock is disconnected)," 0, 1 "(when the second clock is disconnected)," 1, 1 "(either the first clock or the second clock) Signal is output as a clock switching signal.

  Reference numeral 5 is a selection circuit (selector), and 6 is a frequency dividing circuit. The selection circuit 5 selects one of the output signal paths of the first multiplication circuit 1 to the third multiplication circuit 3 and connects it to the input terminal of the frequency division circuit 6, in other words, each multiplication circuit It is configured to select one of the multiplied clocks (first clock, second clock, clock from TCXO 31) sent from 1 to 3 and send the selected clock to the divider circuit 6. Selection of the output signal path in the selection circuit 5 is performed based on the above-described clock switching signal output from the clock disconnection detection circuit 4.

When the first clock is input to the first multiplier circuit 1, that is, when the clock switching signal is “0, 0” or “0, 1”, the selection circuit 5 selects the first clock of the first multiplier circuit 1. When the output end is selected and the first clock is disconnected and the second clock is input to the second multiplier circuit 2, that is, when the clock switching signal is "1, 0", the second multiplier circuit When 2 is selected and both clocks are disconnected, that is, when the clock switching signal is "1, 1", the third multiplying circuit 3 is selected.
FIG. 2 shows the relationship between the presence / absence of the first clock and the second clock and the clock selected by the selection circuit 5.

In this example, the divider circuit 6 includes a 3-bit counter that counts the clock selected by the selection circuit 5, and is configured to output the MSB (most significant bit) of the counter value of the counter. Since the counter outputs a value from 0 to 7 in decimal system, the MSB is “0” for count values 0 to 3 and “1” for count values 4 to 7, so MSB is a minute. The clock input to the peripheral circuit 6 is equivalent to a clock divided by 1/8. In the divider circuit 6, the MSB of the counter value may be output as it is, or may be inverted and output. The presence or absence of inversion does not affect the operation and effect of the present embodiment at all, but in the time chart of FIG. 3 described later, a signal obtained by inverting the MSB is used as a reference clock of the PLL circuit.
The divider circuit 6 is not limited to such a configuration, and divides the frequency of the clock output from the selection circuit 5 to the frequency before multiplication, that is, 1 / n (1/8 in this example). If it is a structure, it will not be restricted to the above-mentioned structure.

  A PLL circuit 7 is provided at the subsequent stage of the divider circuit 6. The PLL circuit 7 uses the clock output from the divider circuit 6 as a reference clock, and the phase of the signal obtained by dividing the frequency of the output signal of the VCXO 71 into 1 / N by the divider circuit 72 and the reference clock (reference signal) Are compared by the phase comparison unit 73, and the output frequency of the VCXO 71 is controlled by the control voltage corresponding to the comparison amount.

Reference numeral 81 denotes a baseband modulation unit, which uses the output signal output from the PLL circuit 7 as a clock, carries the baseband transmission signal on a carrier wave corresponding to this clock, and transmits the carrier via the high frequency modulation unit 82 It is. The baseband modulation unit 81 is provided with a DDS, for example, as described in the "Background Art" section, in order to output a clock as an analog wave.
Returning to the first clock, since the first clock is less stable in frequency than the second clock, for example, the frequency fluctuates due to the environmental temperature. The frequency difference between the first clock and the second clock is detected, and the detected frequency difference is used to correct the operation of the DDS. Specifically, the frequency of the clock output from the PLL circuit 7 is corrected by the correction value corresponding to the frequency difference, that is, when the frequency of the first clock is higher than the frequency of the second clock (lower case) In addition, only the correction value is subtracted (added) to stabilize the operation of the DDS and suppress the deterioration of the transmission signal.
Also, in this example, when the first clock and the second clock are cut off (when the clock is cut off), the output signal of the TCXO 31 is used as a clock, so the output signal of the TCXO 31 is used as the first clock. A frequency synchronization circuit 32 for synchronization is provided. The frequency synchronization circuit 32 divides a frequency of an output of the TCXO 31 so as to form a PLL circuit together with, for example, the TCXO 31, and a phase comparator which compares the phase of the frequency signal from the frequency divider with the first clock. And so on. The frequency synchronization circuit 32 may not be provided.

Next, the operation of the above-described embodiment will be described. Now, for example, it is installed near the first clock (dependent synchronous clock) sent from the VCXO provided in the upper apparatus in the base station, the second clock sent from the Rb oscillator, and the broadcast equipment shown in FIG. It is assumed that the third clocks sent from the TCXO 31 are input to the multiplying circuits 1 to 3, respectively. In this case, since the 2-bit clock switching signal of the clock disconnection detection circuit 4 is “0, 0”, the first clock multiplied by 8 in the first multiplication circuit 1 is selected in the selection circuit 5. Is selected. Then, the first clock is sent to the divider circuit 6, divided into eight to return to the original frequency before multiplication, and input to the phase comparator 73 of the PLL circuit 7 as a reference clock.
Then, the frequency signal output from the PLL circuit 7 is input as a clock to the baseband modulation unit 81, the frequency of this clock is corrected by the correction value obtained from the correction value calculation circuit 83, and is generated based on the corrected clock. The baseband transmission signal is placed on the carrier wave and transmitted.

Subsequently, how the clock is switched when the first clock is disconnected will be described with reference to FIGS. 3 and 4. In FIG. 3, symbols (a), (b), etc. attached to each time chart of each signal correspond to the symbols (a), (b), etc. shown in FIG. A description of the signal is given. FIG. 4 is a time chart showing the vicinity of the switching timing of the clock in an enlarged manner.
Assuming that the first clock is cut off at time t0, the clock cut detection circuit 4 has, for example, five detection clocks from the third multiplication circuit 3 corresponding to a frequency obtained by multiplying the first clock by 8. Since the level of the signal line of the first clock is at the “L” level for the time corresponding to or longer than the time t1, it is determined that the first clock has become disconnected. In the example of FIG. 3, a margin is taken for the detection of the clock disconnection, and the level of the signal line of the first clock is “L” while nine detection clocks are input. Thus, the clock switching signal is switched to “1, 0” at time t1. In FIG. 3E, for convenience, the state before switching is represented by the “L” level, and the state after switching is represented by the “H” level.
On the other hand, the first multiplier circuit 1 runs for a while after the input of the clock is interrupted (the clock of 8 multiplication is output), and therefore the timing when the clock switching signal switches to "1, 0" (time t1) The first clock multiplied by eight by the first frequency multiplier circuit 1 is input to the selection circuit 5 immediately before immediately before. As described above, the level of the output signal of divider circuit 6 changes from "L" level to "H" level when the counter value of the counter in divider circuit 6 becomes "0" or "7". In the example of FIG. 3, assuming that the clock switching signal is switched to "1, 0" when the counter value is "5", at this timing, the reference input to the PLL circuit 7 as shown in (i) The clock level is "L".
The clock selected by the selection circuit 5 at time t1 is switched from the first clock to the second clock, and the clock in the divider circuit 6 is selected by the clock input to the divider circuit 6 for the first time after time t1. The counter value of the counter is counted up from “5” to “6”, and the counter value becomes “7” by the subsequent second clock, and the level of the output signal of the divider circuit 6 is “L” level Change to the “H” level.

  Therefore, the time for which the count value is maintained at "5" is shortened in this example by the phase difference between the first clock and the second clock which are each multiplied by eight. Therefore, the original reference clock (the reference clock when the first clock is not interrupted) and the actual reference clock (the reference clock when the first clock is interrupted and switched to the second clock) There is a phase difference Δt between them. However, this phase difference Δt is suppressed within 1/8 of the phase difference of the second clock before multiplication, so that the fluctuation of the output frequency of the PLL circuit 7 is suppressed.

In addition, when the second clock is disconnected while the first clock is not yet recovered while the second clock is being switched and operated, the clock disconnection detection circuit 4 is output. Since the clock switching signal is “1, 1”, the selection circuit 5 is a detection clock output from the TCXO 31 and a clock multiplied by 8 by the third multiplication circuit 3 is selected. Also in this case, since the second multiplication circuit 2 is free running even after the second clock is cut, the clock to be counted by the distribution circuit 6 is similarly detected from the second clock for detection. The clock is switched to the clock, and the output level of the divider circuit 6 becomes “H” level or “L” according to the counter value. Accordingly, the fluctuation of the output frequency of PLL circuit 7 is suppressed similarly, and when both the first clock and the second clock are cut off, the fixed voltage described in the item of "Background Art" This is much more advantageous than the control mode.
The multiplication number of the third multiplication circuit 3 is not limited to "8", and any multiplication number may be used as long as it doubles or more.

  As described above, according to the above-described embodiment, the first clock and the second clock are each multiplied by n, and using self-running even after the input of the multiplying circuit 1 (2) is interrupted, Since the clock output from the selection circuit 5 is divided into 1 / n based on the counter value of the divider circuit 6, the phase difference between the clocks before and after the clock switching can be reduced. It is required to minimize the fluctuation of the clock when the clock is switched. For example, it is extremely useful to apply the present invention to the switching of the clock used when performing baseband modulation in a base station that emits broadcast radio waves. .

1 to 3 multiplication circuit 31 TCXO
4 Clock break detection circuit 5 Selection circuit 6 Divider circuit 7 PLL circuit 71 VCXO
73 Phase Comparator 81 Baseband Modulator

Claims (6)

A first multiplication circuit that multiplies the first clock by n (n is an even number);
A second multiplication circuit that multiplies by n the second clock that is switched and used when the first clock is interrupted;
A detection circuit that detects the presence or absence of the first clock using, as an operation clock, a detection clock that has a frequency twice or more the frequency of the first clock before being multiplied by n;
A detection signal output when the detection circuit detects that the first clock is interrupted causes the output of the first multiplier circuit to run freely after the first clock is interrupted according to a detection signal output from the first multiplication circuit. Select circuit to switch to the output of
A divider which is disposed downstream of the selection circuit and includes a counter that counts pulses output from the selection circuit, and divides the clock output from the selection circuit into 1 / n based on the counted counter value. A clock switching device comprising: a circuit.   The clock switching device according to claim 1, wherein the second clock has higher frequency stability than the first clock.   3. The clock switching device according to claim 1, wherein the clock for detection has lower frequency stability than the first clock.   The clock switching device according to any one of claims 1 to 3, further comprising an oscillator that outputs the clock for detection. The detection circuit is configured to detect the presence or absence of the second clock in addition to detecting the presence or absence of the first clock;
The clock for detection is input to the selection circuit.
The selection circuit selects the clock for detection according to a detection signal output when the detection circuit detects that the first clock and the second clock are interrupted, and selects the clock for the division. The clock switching device according to any one of claims 1 to 4, wherein the clock switching device outputs the clock. An oscillator for outputting the clock for detection;
6. The clock switching device according to claim 5, further comprising a circuit for synchronizing the detection clock with the first clock.

Images