JPS63287206A - Clock signal hit preventive circuit - Google Patents

Abstract

PURPOSE:To generate a consecutive output clock signal without missing of pulse at all times even with an optional phase difference of the active system and the standby system by providing a frequency multiplier circuit and a frequency division circuit. CONSTITUTION:After clock signals A, B of the active and standby systems are converted into clock signals having a frequency of a multiple of N by frequency multiplier circuits 5, 6, one of them is selected by a changeover circuit 7 and a 1st LC resonance circuit 11 is excited by the clock signal, and after the excited sinusoidal wave signal is converted into a clock pulse of the set level by the 1st clock signal recovery circuit 12, the signal is formed into a clock signal of 1/N frequency by a frequency division circuit 13. The sinusoidal wave signal outputted by a 2nd LC resonance circuit 14 tuned to the clock signal is converted into the clock pulse of the set level by the 2nd clock signal recovery circuit 15. Thus, the phase change quantity after and before the system changeover is decreased sufficiently and the clock signal obtained is a consecutive clock pulse without missing of pulse.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a clock signal generating section of a synchronous terminal device, etc., when the output of a clock signal is switched from a working system to a protection system. The present invention relates to a clock signal interruption prevention circuit that prevents instantaneous interruptions in clock signals.

[Conventional technology]

FIG. 8 is a circuit diagram showing a conventional clock signal interruption prevention circuit. In the figure, 1 is an input terminal for the active system clock signal, 2 is an input terminal for the backup system clock signal, and 3 is an input terminal for the active system clock signal. 4 is a disconnection detection circuit that detects an input disconnection of the protection system clock signal; 7 is a switching circuit that selects one of the clock signals of the active system and the protection system; 8 is a switching circuit T; A switching signal generation circuit that generates a switching signal to be controlled; 9 an inverter that is a component of the switching signal generation circuit 8; 10 a NAND gate that is a component of the switching signal generation circuit 8; 14 a working system and a backup system; LC resonance circuit tuned to the frequency fO of the clock signal of the system; 15 is a SIN/T as a clock signal regeneration circuit;
In the TL conversion circuit, 16 is an output terminal for an output clock signal.

Next, the operation will be explained.

The active system and protection system clock signals A and B are respectively inputted from input terminals 1.2, and the disconnection detection circuit 3.4 monitors whether or not there is an interruption in the active system and protection system clock signals A and B, respectively. The disconnection detection circuit 3.4 is composed of, for example, an RC monostable multivibrator, and when it detects a disconnection with a time width corresponding to a time constant set by a resistor and a capacitor,
It sends disconnection detection signals C and D, respectively. In FIG. 8, disconnection detection signals C and D are signals that become low level when disconnection is detected. The disconnection detection signals C and D are input to the switching signal generation circuit 8, and the switching signal E is generated according to a certain algorithm.
is generated. In FIG. 8, by using the inverter 9 and the Nant gate 10, the switching signal E becomes low level only when a disconnection is detected in the active system clock signal A and no disconnection is detected in the protection system clock signal B. I have to. On the other hand, the active system clock signal A and the protection system clock signal B are inputted to the switching circuit 7, and when the switching signal E is high level, the active system is selected, and when the switching signal E is low level, the protection system is selected, and the selected clock signal F is selected. is sent to the LC sympathy circuit 14. The LC resonant circuit 14 receives the clock signal F.
The frequency f. Since it is tuned to the frequency f, it is excited by the clock signal F. outputs a sine wave signal G.

The sine wave signal G is sent to the SIN/TTL conversion circuit 15,
It is regenerated and converted into a TTL level clock signal H, and sent out from the output terminal 16.

Next, the operation when the active system clock signal A is disconnected and the system switches to the standby system will be described. However, here, it is assumed that the active system clock signal A and the standby system clock signal B have the same phase so as to avoid problems described later. 9th
The figure shows a waveform diagram of signals A to H of each part of the circuit when system switching occurs. Assuming that the interruption detection circuit 3 detects an interruption of the input clock signal when the input is interrupted for five time slots, the output E of the switching signal generation circuit 8 is also set to the level at the end of the time slot, as shown in FIG. Five time slots after the active system clock signal A is interrupted, it is switched to the protection system clock signal B, and the switching circuit 5 outputs a clock signal F that is interrupted for five time slots. In order to compensate for this instantaneous interruption for 5 time slots, the clock signal F
is input to the LC resonance circuit 14. The LC resonant circuit 14 uses the frequency f of the clock signal F. Therefore, even if clock signal F is interrupted by 5 time slots, the 9th
As shown in the figure, the amplitude gradually attenuates, but the frequency f.

When the clock signal F is inputted again after five time slots, the amplitude of the sine wave signal G is restored to its original magnitude. Therefore, unless the sine wave signal G disappears due to attenuation during the specified period of the clock signal F, the level conversion by the sine wave signal GVC8IN/TTL conversion circuit 15 allows the continuous output clock signal H
can be played.

The above is an explanation of the operation when the phases of the active system clock signal A and the protection system clock signal B match, but when there is a phase difference of π between the active system and protection system clock signals A and B, The operation is as follows.

FIG. 10 shows clock signals A for the active system and the standby system.

FIG. 7 is a waveform diagram of each part of the circuit when there is a phase difference of π in B. FIG.

In this case, as shown in the clock signal F and the sine wave signal G as shown in FIG. Since the phase is inverted with respect to the clock signal A, it acts to attenuate the sine wave signal G before switching and generate a sine wave signal G whose phase is inverted with respect to the sine wave signal G before switching. do. Therefore, after the amplitude of the sine wave signal G is attenuated to a zero level after switching, a new sine wave signal with an inverted phase is excited by the clock signal after switching.

[Problem that the invention seeks to solve]

Since the conventional clock signal instantaneous interruption prevention circuit is configured as described above, when a phase difference occurs between the working system clock signal A and the protection system clock signal B, the sine wave signal G is There were problems such as the clock signal being attenuated by the clock signal, resulting in a clock signal with missing pulses before and after the switching. In particular, the further the phase difference is away from π, the smaller the amount of attenuation of the sine wave signal G becomes. However, when the phase difference becomes π, the amplitude of the sine wave signal G attenuates to zero, and the SI
Regardless of the sensitivity of the N/TLL circuit 15, there was a hot spot in which the output clock signal H suffered from pulse dropouts.

This invention was made to solve the above-mentioned problems, and no matter how large the phase difference between the working clock signal and the protection clock signal is, the clock signal switching of each unit can be easily performed. It is an object of the present invention to provide a clock signal instantaneous interruption prevention circuit that reproduces continuous output clock signals without causing instantaneous interruptions before and after.

[Means for solving problems]

The clock signal instantaneous interruption prevention circuit according to the present invention uses a frequency multiplier to convert the clock signals of the working system and the preliminary system 1 into N
After converting it into a clock signal with double the frequency, one is selected by the switching circuit, the first LC resonant circuit is excited by the selected clock signal, and the excited sine wave signal is
After converting it into a clock pulse of a set level with a clock signal regeneration circuit of $1, it is made into a clock signal of 1/N frequency by a frequency dividing circuit, inputted to a second LC resonant circuit tuned to this clock signal, and this second LC resonant circuit is tuned. The second LC resonant circuit converts the sine wave signal outputted by the second LC resonant circuit into clock pulses at a set level in the second clock signal regeneration circuit, thereby obtaining a continuous output clock signal without missing pulses. .

[Effect]

In the frequency dividing circuit according to the present invention, the phase difference between the clock pulses of the working system and the standby system obtained by frequency multiplication is in the vicinity of π, and the first clock signal regeneration circuit receives several clock pulses before and after system switching. Where a clock signal containing interruptions across time slots is output, this clock signal is
Since the frequency is divided, the amount of phase change before and after system switching is made sufficiently smaller than π, regardless of whether the clock interruption width is an odd number or an even number. Therefore, after inputting this /N-divided clock pulse to the second LC resonant circuit, the clock signal obtained by converting the level in the second clock signal regeneration circuit is as follows.
Continuous clock pulses with no pulse dropout.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is an input terminal for the active system clock signal, 2 is an input terminal for the protection system clock signal, 3 is an interruption detection circuit that detects an input interruption of the active system clock signal, and 4 is a detection circuit for detecting an input interruption of the protection system clock signal. 5 is a frequency multiplier circuit that doubles the frequency of the active system clock signal, 6 is a frequency multiplier circuit that doubles the frequency of the protection system clock signal, and T is the active system or protection system. 8 is a switching signal generation circuit that generates a switching signal to control the switching circuit 7 , 9 is an inverter that is a component of the switching signal generation circuit 8 , and 10 is a switching signal generation circuit 8 NAND gate, which is a component of
1 is the frequency f of the clock signal of the active system and the protection system. a first LC resonant circuit tuned to a frequency 2fo twice that of 1;
2 is SIN/2 as the first clock signal regeneration circuit.
A TTL conversion circuit, 13 a frequency dividing circuit that converts the frequency to /2, and 14 a frequency f. The second LCC common circuit 15 tuned to the SIN/T as a second clock signal regeneration circuit
In the TL conversion circuit, 16 is an output terminal for an output clock signal.

Next, the operation will be explained with reference to the signal waveform diagrams of each part of the circuit shown in FIGS. 2 to 6. First, input terminals 1 and 2
The clock signals A and B of the working system and the standby system with a phase difference φ input to the frequency multipliers 5 and 6 are converted to a
It is converted into clock signals C and D of fo, and the phase difference becomes 2φ. Therefore, if 0≦φ≦π, the phase difference between the clock signals C and D of the working system and the protection system after frequency multiplication becomes as shown in FIG. In the switching circuit T, the frequency 2f
One of the two-system clock signals C and D converted to o is selected and input to the first LC resonant circuit 11 tuned to the frequency 2fo. A sine wave signal G is excited from the first LC resonant circuit 11, but if the phase difference between the clock signals C and D of the working system and the protection system after frequency multiplication is in the vicinity of π, several time slots are generated. This results in a sine wave signal G including a break across the area. This sine wave signal G is converted to a TTL level in a SIN/TTL conversion circuit 12, and then converted to a frequency f in a frequency dividing circuit 13. The frequency is divided by the clock signal generator. Here, the clock signal H having a frequency of 2fo input to the frequency dividing circuit 13 has a phase difference between O and π before and after system switching, but the frequency f is the frequency divided by the frequency dividing circuit 13. As shown in FIG. 7, the phase difference of the clock signal (2) before and after the system switching is reduced compared to the case of the clock signals C and D having a frequency of 2fo. This is because the frequency dividing circuit 13 has the effect of reducing the amount of phase change before and after system switching to -. The reason why the sine wave signal G which is the output of the first LC resonant circuit 11 is interrupted is due to the input clock signals C and D.
This is because the phase difference before and after the system switching is in the vicinity of π, so the frequency f from the frequency dividing circuit 13. The clock signal generator has a frequency f. a second LC resonant circuit 1 tuned to
4, a continuous sine wave signal G that does not include interruptions even when the system is switched is excited. This sine wave signal G is SI
By converting the level in the N/TTL conversion circuit 15,
Even by system switching, a continuous output clock signal K without any interruption can be obtained.

The above operation? To explain in more detail, the phase difference φ between the working system and protection system clock signals A and B will be explained separately for each case below. In addition, corresponding to each case of the magnitude of the phase difference φ, the waveform diagram of the signals A-H of each part of the circuit in FIG.
As shown in FIGS.

FIG. 2 shows waveforms A-H of each part of the circuit before and after system switching. In this case, since φ is not in the vicinity of -, the first LC
The amount of phase change of the clock signal F to the resonant circuit 11 due to the system switching is not in the vicinity of π. Therefore, the sinusoidal signal G
becomes a continuous signal without any breaks, and this sine wave signal G
As described above, the level is converted by the SIN/TTL conversion circuit 12, and the frequency is further divided by the frequency dividing circuit 13.
The output clock signal that is input to the LC resonance circuit 14 and then level-converted by the SIN/TTL conversion circuit 15 has a phase change amount φ' before and after switching that is equal to φ, as shown in FIG. Become. In this case, the amount of phase change due to switching is not alleviated. However, there will be no interruption in K.

FIG. 3 shows waveforms A-H of each part of the circuit before and after system switching. In this case, the amount of phase change due to system switching of the clock signal F to the first LC resonant circuit 11 is π, so a break occurs in the sine wave signal G, which is transferred to the SIN/TTL conversion circuit 1.
In the clock signal obtained by level conversion according to No. 5, a disconnection of several time slots occurs. However, since the amount of phase change of this clock signal before and after switching is -, a continuous sine wave signal J is excited from the second LC resonant circuit 14, and whenever a break occurs in the output clock signal K, do not have.

Waveforms A-Ht of various parts of the circuit at the time are shown in FIG. In this case, since the amount of phase change before and after switching the clock signals C and D to the first LC resonant circuit 11 is in the vicinity of π, a break occurs in the sine wave signal G, and this is converted to a level. A disconnection of several time slots occurs in the level conversion signal H/J lock signal.

At this time, as shown in FIG. 4, depending on the timing at which the clock signal is disconnected and the number of pulses at which the clock signal is disconnected, the amount of phase change before and after the switching of the clock signal may become -+. Therefore, as shown within the circle broken line in FIG. 7, the clock signal ■ to the second LC resonant circuit 14 is
Before and after switching, the phase changes by -+Δ. However, since the thickness of Δ is minute, the second LC resonant circuit 1
There is no interruption in the sine wave signal J excited at 4, and there is no interruption in the output clock signal K. 0IV) When −<φ<π, the waveforms of each part of the circuit before and after system switching. A-H is shown in FIG. In this case, since the phase difference before and after the switching of the clock signal F to the first LC resonant circuit 11 is π, the phase change amount range is O<ζ × π. Therefore, the first L
A continuous sine wave signal G without interruption is excited from the C resonance circuit 11. This sine wave signal G is level-converted in the same way as above, and then frequency-divided by 1, the second LCC
The amount of phase change of the clock signal ■ to the resonant circuit 14 before and after switching is reduced to -, and a continuous sine wave signal J without any interruption is excited from the second LCC resonant circuit 14, and this sine wave signal By converting the level of G, a continuous output clock signal K without interruptions can be obtained.

(2) When φ=π Waveforms A to H of each part of the circuit before and after system switching are shown in FIG. In this case, the amount of phase change before and after switching the clock signal F to the first LC resonant circuit 11 is zero. Therefore, since no phase change occurs before and after switching, the output clock signal becomes a continuous clock signal without any phase change.

From the above 1) to ■), as shown in Figure 7, the second LC
The amount of phase change due to system switching of the input clock signal ■ to the LC resonance circuit 14 from the system of the input clock signal ■ to the resonant circuit 14 does not exceed -10Δ. Therefore, 0≦φ≦π
For any phase difference, the output clock signal will always be a continuous clock signal without any interruptions.

In the above embodiment, the frequency f of the clock signals A and B in the frequency multiplier circuits 5 and 6. is multiplied by 2fo, and in the frequency dividing circuit 13, φ' is also -+Δ will not be exceeded.

Therefore, by increasing the value of N, the amount of phase change ζ due to system switching can be further reduced, and the effect of preventing instantaneous power outages can be enhanced. Further, in the embodiment shown in FIG. 1, the frequency multiplier circuits 5 and 6 are arranged before the switching circuit 7, but the switching circuit T receives the manual clock signal A for the active system and the standby system.

B is input directly to the frequency divider circuit 13 and the first LC resonant circuit 1.
Even if the frequency multiplier circuits 5 and 6 are placed between the two, the same instantaneous interruption prevention effect as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, after the input clock signals of the working system and the protection system are converted to N times the frequency by the frequency multiplier circuit, the switching circuit excites the sine wave signal of N times the frequency, and this is used to reproduce the clock signal. Since the circuit is structured differently, the second LC
The resonant circuit and the second clock signal regeneration circuit have the effect of being able to always generate a continuous output clock signal without missing pulses, even for any phase difference between the working system and the backup system. .

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a clock signal instantaneous interruption prevention circuit according to an embodiment of the present invention, FIGS. 2 and 3. 4, 5, and 6 are waveform diagrams of signals in each part of the circuit to explain the operation of the circuit shown in FIG. 1, and FIG. 7 shows the effect of reducing the amount of phase change before and after system switching according to the present invention. FIG. 8 is a circuit diagram showing a conventional clock signal interruption prevention circuit, and FIGS. 9 and 10 are signal waveform diagrams of various parts of the circuit to explain the operation of the circuit shown in FIG. 8. . 3.4 is an input disconnection detection circuit, 5 and 6 are frequency multiplier circuits, and 7
11 is a switching circuit; 11 is a first LCC common circuit; 12 is a first clock signal regeneration circuit; 13 is a frequency dividing circuit; 14 is a second LC resonant circuit; and 15 is a second clock signal regeneration circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation
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Claims (1)

[Claims] a disconnection detection circuit that detects an input disconnection of the active system clock signal and the backup system clock signal; a frequency multiplier circuit that converts each of the active system and backup system clock signals into a clock signal whose frequency is N times higher; a switching circuit that selects one of the working system clock signal and the standby system clock signal multiplied by N times; a first LC resonant circuit that outputs a sine wave signal tuned to the clock signal outputted by the switching circuit; a first clock signal regeneration circuit that regenerates and converts the sine wave signal output from the first LC resonant circuit into a clock signal of a set level; and a clock signal from the first clock signal regeneration circuit that converts the clock signal to 1/N. A frequency dividing circuit that divides the frequency,
a second LC resonant circuit that outputs a sine wave signal tuned to the clock signal from the frequency dividing circuit; and a second LC resonant circuit that regenerates and converts the sine wave signal output from the second LC resonant circuit into a clock signal at a set level. 2. A clock signal instantaneous interruption prevention circuit comprising a second clock signal regeneration circuit.