KR100323223B1 - Phase lock device of time frequency supply apparatus - Google Patents

Abstract

PURPOSE: A phase lock device of a time frequency supply apparatus is provided, which is capable of locking a phase by phase preceding and retarding operations by comparing/estimating 1PPS used as a reference clock to use a delay cell and a multiplexor. CONSTITUTION: A comparison part(31) receives two 1PPS signals, generates a counter value corresponding to a phase error of input signals(1PPS1,1PPS2) by a clock(CLOCK), and calculates a control value. The first and second delay parts(32,33) accomplish synchronization by making two 1PPS signals precede or retard by a resolution of one step according to a control value of the comparison part(31). An OR gate(34) receives output signals of the first and second delay parts(32,33) to output a 1PPS signal.

Description

Phase synchronizer of time frequency supply

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase synchronization device of a time frequency supply device, and in particular, compares / evaluates 1PPS (pulse per second, pulse per second) used as a reference clock of a code division multiple access (CDMA) system. The present invention relates to a device for synchronizing phases by using phase retardation and retardation using delay and multiplexers.

In general, a CDMA system is a system in which multiple users share the same frequency band and communicate with each other, such as a PCS (Personal Communication System), a DCS (Digital Cellular Switch), a WLL (Wireless Local Loop), etc. Used in

1 is a block diagram of a general time frequency supply device.

As shown therein, phase synchronization unit 1 for synchronizing the phase by receiving the time information and position information of the time frequency supply device; A GPS receiver (2) for receiving a GPS satellite signal from a GPS (Global Positioning System) satellite and providing GPS 1PPS (pulse per second) to the phase synchronizer 1; It consists of a reception control and a TOD generator (3) for exchanging information with the phase synchronization unit (1), receiving information from the GPS receiver (3), and transmitting commands to generate reception control and time of day (TOD). It became.

The general time frequency supply device configured as described above receives time information and satellite information from the GPS satellites, and compares and analyzes the signal generated by the rubidium oscillator and the 1PPS signal generated by the GPS receiver 2 once per second. In other words, it performs a kind of phase locked loop (PLL) to generate a very precise 10 MHz signal, a 1 PPS signal, and a TOD to supply a reference clock to the CDMA system. An LCD (Liquid Crystal Display) is used to view the current state of the CDMA time-frequency supply. The LCD displays the current time and time mode (UTC / GPS), the current position, and the relative frequency error of 10 MHz.

In particular, the time information is obtained from the GPS receiver 2 once every two seconds, and the time information for the remaining one second is used to convert time information about UTC / GPS mode. Thus, the time frequency supply device provides time and location information using information received from GPS satellites.

2 is a block diagram of a phase synchronization device of a conventional time frequency supply device.

As shown in the figure, the variable circuit unit 11 for leading or behind the input 1PPS with a resolution of one step; The variable circuit unit 11 includes a multiplexer 12 that multiplexes the variable 1PPS signal by a desired clock number according to a control signal of the central processing unit and outputs a variable signal.

The conventional phase synchronizing device configured as described above uses a 10 MHz rubidium oscillator as a frequency source of the redundant system. An oscillator with a 10 MHz accuracy of ± 2 × 10 ^-11 is divided into 10 million to generate 1 PPS. The 1PPS inputted with the crystal frequency of 100 MHz, which is a control frequency, as the frequency source in the variable circuit section 11 Advanced or backward in resolution. Then, the central processing unit operates the multiplexer 12 to output 1 PPS of the desired clock number to supply the reference clock to the CDMA system.

In this case, jitter refers to how much each bit is shifted forward or backward in the time position in which the digital transmission is supposed to be performed. In the digital transmission, jitter is a multiplexer jitter and a player that occurs during the multiplexing-demultiplexing process. There is regenerator jitter that occurs during transmission across these fields.

However, the conventional device has a problem that the accuracy of the accuracy is lowered and jitter is generated by implementing a synchronization circuit using a 100MHz crystal as a frequency source in the variable circuit unit.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to compare / evaluate 1PPS used as a reference clock of a CDMA system, and to use a phase delay and a multiplexer to delay and reverse a phase. The present invention provides a phase synchronization device of a time frequency supply device for synchronizing phases.

Phase synchronization device of the time frequency supply device according to the present invention to achieve the above object,

A comparator for receiving two 1PPS signals and generating a counter value corresponding to a phase difference between the two signals inputted by using a clock and calculating a control value; First and second delay units for synchronizing the two 1PPS input according to the control value of the comparator with one step resolution or one second; The technical configuration is characterized by consisting of a logic operation unit for outputting the 1PPS signal by performing a logical operation of the output of the first and second delay unit.

1 is a block diagram of a general time frequency supply device,

2 is a block diagram of a phase synchronization device of a conventional time frequency supply device;

3 is a block diagram of a redundant time frequency supply system for CDMA to which the present invention is applied;

4 is a block diagram of a phase synchronization device of a time frequency supply device according to the present invention;

5 is a detailed block diagram of a comparison unit in FIG. 4;

6 is a detailed circuit diagram of the counter unit in FIG. 5;

7 is a detailed block diagram of a first delay unit and a second delay unit in FIG. 4;

FIG. 8 is a detailed circuit diagram of a first delay unit and a second delay unit in FIG. 7;

9 is a circuit diagram showing a delay step in FIG. 8;

FIG. 10 is a waveform diagram illustrating an output of a comparison unit in FIG. 4;

FIG. 11 is a waveform diagram illustrating outputs of the first and second delay units in FIG. 4; FIG.

Figure 12 is a comparison waveform diagram with cesium 1PPS when using the cell delay.

<Explanation of symbols for the main parts of the drawings>

31: comparison unit

32, 33: first and second delay unit

34: logical sum operation unit

Hereinafter, an embodiment according to the technical idea of the phase synchronization device of the present invention time frequency supply device configured as described above is as follows.

3 is a block diagram of a redundant time frequency supply system for CDMA to which the present invention is applied.

As shown in FIG. 1, a clock having a built-in rubidium oscillator used as a clock source of the equipment and measuring the time offset of 1PPS in which the oscillator clock is divided by 10 million and the 1PPS generated by the GPS receiver 2, and phase-synchronized to the GPS 1PPS GTFU 21 and 22 for outputting time information and other status information; GSDA (23) (24) for comparing and evaluating the clocks generated by the two GTFUs (21) (22) and the output of the status information to phase-synchronize the clock and 1PPS, respectively, and for self-diagnosing the system. Wow; It is composed of GTPA (25) (26) for supplying a stable power required for the redundant equipment of the GTFU (21) 22 and GSDA (23) (24).

4 is a block diagram of a phase synchronization device of a time frequency supply device according to the present invention.

As shown therein, a comparator 31 which receives two 1PPS signals, generates a counter value corresponding to the phase difference between the two signals inputted by the clock, and calculates a control value; First and second delay units (32) (33) for synchronizing the two 1PPS inputs according to the control value of the comparison unit (31) to advance or lag with one step resolution; And a logic operation unit 34 for performing logic operation on the outputs of the first and second delay units 32 and 33 to output the 1PPS signal.

As shown in FIG. 5, the comparator 31 includes: first and second deflip-flops 41 and 42 for receiving and delaying two 1PPS signals; An exclusive negative logic operation unit 43 for receiving the signals of the first and second flip-flops 41 and 42 and performing exclusive negative logical operation; A logical product operator (44) for receiving the signals of the first and second deflip-flops (41) (42) and performing an AND operation; The exclusive negative logic operation part 43 and the counter product 45 are counted according to the input clock.

The counter unit 45 includes an up / down counter 46 for up / down counting the signals of the exclusive negative logic operation unit 43 and the logical product operation unit 44, as shown in FIG. It consists of an octal buffer 47 that temporarily stores the output of the up / down counter 46.

As shown in FIG. 7, the first and second delay units 32 and 33 receive a control signal from the comparator 31 and output a 1PPS delay control signal to a plurality of bit select lines. A control unit 51; A delay unit 52 for delaying an input signal of 1PPS; The multiplexer 53 is configured to multiplex and output the 1PPS signal delayed by the delay unit 52 according to the control signal of the controller 51.

The operation of the phase synchronization device of the time frequency supply device according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, a redundant time frequency supply system for CDMA provides a reference clock to a CDMA system, which can be used as a source of synchronization of the system. The system consists of six modules, two GTFU (21) (22), GSDA (23) (24), and two GTPA (25) (26) modules, each of which is not the same module. In the event of this failure or malfunction, the CDMA system can always provide a high accuracy clock even if the module is removed.

Thus, the GTFU (21) (22) module has a built-in 10MHz rubidium oscillator that is used as the clock source of the equipment, and 20ns (nano second, nanosecond) of 1PPS generated by the 10MHz clock of the oscillator and 1PPS generated by the GPS receiver 2 Time offset is measured and the processor evaluates / controls this value by the least-squares method, and outputs the phase synchronized to GPS 1PPS (10MHz, 1PPS), time information and other status information (TOD, Time Of Day). Output GSDA (23) (24) module compares / evaluates 10MHz, 1PPS and TOD outputs generated by two GTFU (21) (22) to phase synchronize 10MHz clock and 1PPS, and diagnoses the system itself. Will print. In addition, the GTPA 25, 26 provides stable power required for the duplication equipment of the GTFU 21, 22 and GSDA 23, 24 at + 24V, ± 12V, and + 5V.

Therefore, 1PPS in the GTFU (21) (22) module is always kept within ± 150ns to GPS1PPS, which is the stabilization condition of the system itself, and the cell delay is compared and evaluated by comparing and evaluating each 1PPS generated in the two redundancy modules. It is necessary to match the phases and ensure accurate accuracy.

Accordingly, in the present invention, when two inputs 1PPS are applied to the comparator 31, a counter value corresponding to the phase difference between the two signals is generated by the 50 MHz clock, and the processor evaluates the control value by the least-square method for 100 seconds to obtain an accurate control value. Will yield

10 is a waveform diagram showing the output of the comparator 31, and FIG. 11 is a waveform diagram showing the output of the first and second delay units 32 and 33. FIG.

Thus, when one of the two 1PPS inputs becomes "high", the outputs of the deflip-flops 41 and 42 become "high" and the output of the exclusive negative logic operation section 43 becomes "low". Then, the counter unit 45 operating with a clock of 50 MHz starts operation with a resolution of 20 ns. When the remaining input becomes "high", the output of the exclusive negative logic operation unit 43 becomes "high", and the counter of the counter unit 45 is completed, and the counter unit 45 transmits the counter completion signal to the central processing unit. Done.

The control values calculated in this way are controlled by only one step (about 12 ns) each time the first and second delay units 32 and 33 of 300 ns are evaluated once. That is, the control unit 51 receives the control signal from the comparator 31 and outputs a delay control signal of 1PPS to the 5-bit select line, and the delay unit 52 delays the input 1PPS signal. In step 53, the 1PPS signal delayed by the delay unit 52 is output by multiplexing by one step.

Thus, the 1PPS input to the first and second delay units 32 and 33 is synchronized 150ns behind the GPS 1PPS. This is because the first and second delay units 32 and 33 control 150 ns, which is the center of the total delay value of 300 ns, as a default to control the signal forward or backward, so that 150 ns is advanced in the GTFU 21 and 22 modules. . Then, the data read from the comparator 31 is processed by the least square method for 100 times of data, and then only one step is controlled in the direction of correcting the phase error. This is to prevent malfunction of the system due to time jump.

And it has a control range of 300ns for control of leading and backward phases of ± 150ns of the system, and the controllable value in the central processing unit is 23 stems, and it is controlled from 0 to 22 (00000 ~ 10110) by 5 bit selection line. Is possible and the initial value is 11 (01011).

12 is a comparison waveform diagram of cesium 1PPS when cell delay is used. In other words, since it is not synchronized with cesium 1PPS, there is an offset (294821.8 microseconds), but it can be seen that the output of 1PPS is stable.

As described above, the present invention compares / evaluates 1PPS used as a reference clock of a CDMA system, and synchronizes phases by using phase delay and backward operation using a cell delay and a multiplexer.

As described above, the phase synchronization device of the time-frequency supply device according to the present invention has an effect of removing jitter of 1PPS output by synchronizing phases with phase leading and falling operations using a cell delay and a multiplexer.

In addition, since the present invention does not use an oscillator as compared to the conventional apparatus, the cost can be reduced, and the same chip can be used to reduce the error caused by the operating environment.

Claims (2)

A comparator for receiving a 1PPS signal received from GPS and a 1PPS signal generated using an internal oscillator and a clock and outputting a phase difference control value for correcting a phase difference between two 1PPS signals inputted by the clock; 1PPS signal whose phase is corrected by performing a logical OR operation on the phase control value and the output of the first and second delay units to advance or lag the two 1PPS signals with a resolution of one step. In the phase synchronization device of the time frequency supply device consisting of a logical sum operation unit for outputting The comparison unit, First and second flip-flops for receiving and delaying the two 1PPS signals; An exclusive negation operation unit configured to receive the signals of the first and second flip-flops and perform an exclusive negation operation; An AND operation unit for performing an AND operation on the signals of the first and second deflip-flops; A counter unit for counting signals of the exclusive negated logic operator and the logical product operator according to the input clock and outputting the count value as a phase difference control value, The first and second delay units, A control unit which receives the control signal from the comparator and outputs a delay control signal of a 1PPS signal to a selection line of a plurality of bits; A delay unit for delaying the 1PPS signal; And a multiplexing unit configured to multiplex and output the 1PPS signal delayed by the delay unit by one step according to the control signal output from the control unit. The method of claim 1, wherein the counter unit, An up / down counter for up / down counting the signals of the exclusive negated logical operator and the logical operator; And an octal buffer for temporarily storing the output of the up / down counter.

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