KR20010027386A - Apparatus for synchronizing output of time and frequency card assembly duplicated - Google Patents

Abstract

PURPOSE: A device for equalizing output phase of a duplexing TFCA-A1(Time & Frequency Card Assembly), is provided to use an identical 1-PPS(Pulse Per Second) inputted to the duplexing TFCA-A1 for equalizing output phase, so that duplexing functions can be stably performed in duplexing switching. CONSTITUTION: A D-flip flop(10) latches a time clock(1-PPS(Pulse Per Second)) from a GPS(Global Positioning System) receiver according to a reference frequency(10MHz) from the GPS receiver, to generate a predetermined pulse. A counter(20) is cleared every second by receiving an output of the D-flip flop(10), and counts a reference frequency(10MHz) to generate a reference frequency of a PLL(Phase Locked Loop,30). The PLL(30) receives an inner division register value from a CPU(80), for synchronizing the phase of the reference frequency outputted from the counter(20) with the phase of a comparison frequency. A voltage control oscillator(40) controlled by an output signal of the PLL(30) outputs 39.3216MHz to maintain phase synchronization of the reference frequency and a comparison frequency. A system clock generator(50) performs frequency demultiply by two for na output of the voltage control oscillator(40), and generate a system clock(19.6608MHz) for supply to a channel card. A reference time generating counter(60) counts an output signal of the system clock generator(50), and generates a reference time(PP2S) for supply to the channel card. An N-frequency demultiplier(70) performs frequency de-multiplying for the system clock outputted in the system clock generator(50), to generate a comparison frequency for inputted the PLL(30). A CPU(80) controls an overall operation of the TFCA-A1(Time & Frequency Card Assembly).

Description

Apparatus for synchronizing output of time and frequency card assembly duplicated}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a base station system of Personal Communications Service (PCS), and in particular, the same pulse per input (PPS) input to a Time & Frequency Card Assembly (TFCA-A1) that is redundantly operated in a base station system. By matching the output phases of both TFCA-A1 using the second), the present invention relates to an output phase matching device of a redundant time frequency card that performs a redundancy function stably during a redundancy changeover.

In general, TFCA-A1 (Time Frequency Card) operates in redundancy, and 1PPS (Pulse Per Second (Time Clock), 10MHz (Reference Frequency), TOD (Time of Day) input from Global Positioning System (GPS) receiver in base station system Time information), and 19.6608 MHz (system clock) synchronized to 10 MHz, and divide it to generate information obtained by processing PP2S (Pulse Per 2 Seconds) and input TOD information.

Fig. 1 shows such a general TFCA-A1 and channel card block configuration.

As shown, the GPS receiver 1 receives data from a satellite and outputs 10 MHz (reference frequency), 1 PPS (time clock), and TOD (Time Of Day) for synchronization of the PCS system. The TFCA-A1 (2) receives 10 MHz (reference frequency), 1 PPS (time clock), and TOD (Time Of Day) time from the GPS receiver 1, and 19.6608 MHz (system clock) synchronized with the 10 MHz. And information processed by the PP2S (reference time) divided by the 19.6608 MHz (system clock) and the TOD. The channel card 3 receives a signal output from the TFCA-A1 2 to perform modulation and demodulation.

Although not shown in Figure 1, the TFCA-A1 (2) is implemented by operating in redundancy.

The TFCA-A1 2 divides 10 MHz (reference frequency) output from the GPS receiver 1 to generate 2 MHz, and then inputs the 2 MHz as a reference frequency of a phase locked loop (PLL). do. The phase locked loop circuit then generates a frequency synchronized with this 2 MHz, generates a clock for generating a system clock (19.6608 MHz), and generates a reference time PP2S using this.

However, the PLL device adjusts the voltage input to a voltage controlled oscillator (VCXO) having a frequency of 39.3216 MHz by using 2 MHz input as a reference frequency, since the reference frequency is high (2 MHz). The number of dispensing registers inside the PLL device becomes large, which makes it difficult to match the dispensing time points between the two TFCA-A1s. As a result, the phases of the reference frequencies used in the two TFCA-A1 internal PLL devices are out of sync. The larger the setting value of the dispensing register, the greater the error reflected in the phase difference. For this reason, the phases of the reference frequencies between the two boards are different and the output phase of each TFCA-A1 matches the phase of the reference frequency input to the PLL device, resulting in different output phases of the two TFCA-A1s. When the output phases of the two TFCA-A1 are different from each other, an abnormality occurs in the output of the TFCA-A1 during the redundant switching, and a problem in the service of the base station occurs due to a malfunction of the channel card.

Accordingly, the present invention is proposed to solve the conventional problem caused by the phase mismatch of the output between the two cards at the time of duplication of time frequency card implemented in redundancy for the stability and reliability of system operation as described above. The object of the present invention is to

By using the same 1PPS (Pulse Per Second) input to the Time & Frequency Card Assembly (TFCA-A1), which is operated by redundancy in the base station system, the output phases of both TFCA-A1 are matched, thereby stably during redundancy switching. An object of the present invention is to provide an output phase matching device of a redundant time frequency card that performs a redundancy function.

In order to achieve the above object, the present invention provides a time clock (1PPS) for inputting a time clock (1PPS), each of which is input in the same phase to the redundant time frequency card (TFCA-A1), from a GPS receiver of a personal mobile communication base station system. A flip-flop (D Flip Flop) is latched according to 10MHz to generate a corresponding pulse, and the counter is cleared every second by receiving this pulse with a clear pin, and counts the 10MHz to generate a reference frequency of 3.2KHz of a phase-locked loop circuit. . This generates 3.2KHz synchronized to the time clock (1PPS), and the phase locked loop circuit adjusts the input voltage of the voltage controlled oscillator to synchronize the phase of the comparison frequency to the phase of this 3.2KHz reference frequency. The voltage controlled oscillator thus generates 39.3216 MHz while maintaining the phase synchronization of the reference frequency and the comparison frequency of the phase locked loop circuit. Thus, the outputs of both time frequency cards are phase-locked with each other, so that a stable redundancy transition is achieved.

1 is a block diagram of a general time frequency card block of a personal mobile communication system (PCS);

2 is a block diagram of an output phase matching device of a redundant time frequency card according to the present invention;

<Description of the code | symbol about the principal part of drawing>

10: flip-flop 20: counter

30: phase locked loop circuit 40: voltage controlled oscillator

50: system clock generator 60: counter for reference time generation

70: N frequency divider 80: CPU

Hereinafter, the output phase matching device of the present invention redundant time frequency card as described above in detail with reference to the accompanying drawings as follows.

2 is a block diagram of a redundant time frequency card block including a redundant time frequency card output phase matching device according to the present invention.

As shown, the one-side time frequency card is a flip-flop that latches the time clock 1PPS from the GPS receiver 1 and generates a predetermined pulse according to a reference frequency (10 MHz) output from the GPS receiver 1. (D Flip Flop) 10; A counter 20 which is cleared every second by receiving the output of the flip-flop 10 with a clear pin, and counts the reference frequency (10 MHz) to generate a reference frequency of the phase locked loop circuit 30; ; A phase locked loop (PLL) 30 for receiving an internal frequency division register value from the CPU 80 and synchronizing the phase of the comparison frequency with the phase of the reference frequency output from the counter 20; A voltage controlled oscillator 40 controlled by an output signal of the phase locked loop circuit 30 and outputting 39.3216 MHz so that phase synchronization of the reference frequency and a comparison frequency is maintained; A system clock generator (50) which divides the output of the voltage controlled oscillator (40) into two to generate a system clock (19.6608 MHz) and provides it to the channel card (3); A reference time generation counter (60) for counting the output signal of the system clock generator (50) to generate a reference time (PP2S) and provide it to the channel card (3); An N divider (70) for dividing a system clock output from the system clock generator (50) to generate a comparison frequency and input the same to the phase locked loop circuit (30); An N divider (70) for generating the comparison frequency and inputting it to the phase locked loop circuit (30); It is composed of a CPU 80 that controls the overall operation of the TFCA-A1. The other side time frequency card has the same configuration, and the active state and the standby state are set when mounted and operated in the base station system.

The operation of the redundant time frequency card will now be described based on the operation of the output phase matching device of the redundant time frequency card according to the present invention.

First, the reference frequency (10 MHz), time clock (1 PPS), and time information (TOD) input from the GPS receiver 1 to the two time frequency cards TFCA-A1 are in phase with each other. In the present invention, the phase of the PLL device reference frequency inside each TFCA-A1 is synchronized to the time clock (1 PPS).

That is, since the phases of 1PPS input from the GPS receiver 1 to both TFCA-A1 cards are the same, this characteristic is used to match the phase of 3.2KHz used as the reference frequency for the PLL device of each TFCA-A1 to 1PPS. .

In other words, in the flip-flop 10, the 10MHz output from the GPS receiver 1 is input to the clock pin and 1PPS from the GPS receiver 1 is input to the input pin, which has a high state for a duty of 100 ns. Generate a pulse. The counter 20 receives the pulse as a clear pin and clears it every second. The counter 20 counts the 10 MHz to generate a 3.2 KHz reference frequency for the synchronization reference. Thus, this reference frequency (3.2 KHz) is output in a state synchronized every second to the phase of 1PPS input from the GPS receiver 1, thereby minimizing the number of frequency division registers in the phase-locked loop circuit 30. As a result, an error generated between both TFCA-A1 can be reduced.

The phase locked loop circuit (PLL device) 30 then receives an internal frequency divider register value from the CPU 80 and synchronizes the phase of the comparison frequency with the phase of the reference frequency output from the counter 20. The output of this phase locked loop circuit 30 is passed through a Low Pass Filter (not shown in Figure 2) to adjust the voltage input to the voltage controlled oscillator (VCXO) 40 having a frequency of 39.3216 MHz, Maintain phase synchronization of the comparison frequency. The system clock generator 50 divides the output of the voltage controlled oscillator 40 into two to generate 19.6608 MHz, which is the system clock of the channel card. The N divider 70 divides (previously divides) 19.6608 MHz, which is the output of the system clock generator 50, and generates a comparison frequency to easily compare the phase with a reference frequency of 3.2 KHz. To provide. The reference time generation counter 60 counts this 19.6608 MHz to generate a reference time PP2S. Thus, the system clock generated 19.6608 MHz and the reference time PP2S are provided to the channel card.

In this way, the output of the voltage controlled oscillator 40 is matched to the phase of the reference frequency of 3.2KHz by the phase-locked loop circuit 30, and 3.2KHz is synchronized to the phase of 1PPS input from the GPS receiver 1, and both TFCA- Since the phase of 1PPS input to A1 is the same, the output phases of both cards are exactly the same.

The output phases of the redundant TFCA-A1 are exactly matched to allow the two TFCA-A1 to simultaneously output for about 20 ns during redundancy switching, thereby performing the redundancy function without any abnormality in the output.

As described above, the output phase matching device of the redundant time frequency card according to the present invention is the same 1PPS (Pulse Per) input to a time & frequency card assembly (TFCA-A1) operated by redundancy in a base station system. By synchronizing the reference frequency phase of the phase-locked loop circuit with the phase of Second) and matching the output phase of the voltage controlled oscillator with the phase of this reference frequency, the outputs of both time frequency cards are exactly matched to achieve stable redundancy switching. . Therefore, it is possible to prevent an abnormal occurrence of a channel card caused by a mismatch in the output phases of the frequency cards between the time cards in the conventional redundant switching, and thus, the service of the corresponding station can be stably performed even during the redundant switching. have.

Claims (2)

In the redundant time frequency card (TFCA-A1) of the personal mobile communication base station system, Each time frequency card, According to a reference frequency (10 MHz) output from a GPS (Global Positioning System) receiver in the base station system, a de-flop (Latch) to latch a time clock (1PPS) from the GPS receiver to generate a predetermined pulse ( D Flip Flop); A counter that receives the output of the flip-flop through a clear pin and is cleared every second, and counts the reference frequency (10 MHz) to generate a reference frequency serving as a synchronization reference of a phase-locked loop circuit; A redundancy time comprising a phase locked loop (PLL) for receiving an internal division register value from a CPU of a time frequency card and synchronizing a phase of a comparison frequency with a reference frequency phase from the counter; Output phase matching device of the frequency card. 2. The apparatus of claim 1, wherein the reference frequency output from the counter is 3.2KHz, minimizing the number of internal frequency divider registers of the phase locked loop circuit.