CN116961647A - Multi-chip system with synchronous module and phase-locked loop circuit applicable to same - Google Patents
Multi-chip system with synchronous module and phase-locked loop circuit applicable to same Download PDFInfo
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- CN116961647A CN116961647A CN202210637178.1A CN202210637178A CN116961647A CN 116961647 A CN116961647 A CN 116961647A CN 202210637178 A CN202210637178 A CN 202210637178A CN 116961647 A CN116961647 A CN 116961647A
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- 230000001360 synchronised effect Effects 0.000 title description 17
- 230000001934 delay Effects 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 230000003111 delayed effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
A synchronization module includes a first digital circuit, a second digital circuit, and a phase-locked loop circuit. The first digital circuit is configured to receive an input clock signal. The second digital circuit is configured to output an output clock signal. The phase-locked loop circuit is coupled between the first digital circuit and the second digital circuit. The phase-locked loop circuit includes a delay coupled between the phase frequency detector and the frequency divider. The delayer carries out delay compensation on an output signal of the frequency divider and outputs the output signal to the phase frequency detector. The delay compensation is at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.
Description
Technical Field
The invention relates to a synchronous module, a multi-chip system and a phase-locked loop circuit applicable to the same; and more particularly to a synchronization module with retarder compensation, a multi-chip system and a suitable pll circuit.
Background
As products develop, the complexity and scale of the internal systems of the products also increase. In order to reduce errors between systems, the efficiency of synchronization of clocks between systems is important. Especially in multichip systems, there may still be clock non-synchronization problems due to process or line variations from chip to chip even with the same set of reference clocks. Limitations are also imposed on the expansion or integration of the system.
In view of this, it would be a major key in the product development in the art to overcome the lack of clock synchronization in multi-chip systems due to process or other design differences (e.g., temperature or wiring, etc.) between chips/subsystems.
Disclosure of Invention
The invention provides a synchronous module which comprises a first digital circuit, a second digital circuit and a phase-locked loop circuit. The first digital circuit is configured to receive an input clock signal. The second digital circuit is configured to output an output clock signal. The phase-locked loop circuit is coupled between the first digital circuit and the second digital circuit. The phase-locked loop circuit includes a delay coupled between the phase frequency detector and the frequency divider. The delayer carries out delay compensation on an output signal of the frequency divider and outputs the output signal to the phase frequency detector. The delay compensation is at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.
In one embodiment, the delay is a Digitally Controlled Delay (DCDL).
In one embodiment, the delay device receives a control signal to adjust the delay compensation.
In one embodiment, the delay detector is coupled between the first digital circuit and the second digital circuit, and provides the control signal to the delay according to the input clock signal and the output clock signal.
In one embodiment, the second digital circuit further includes a clock gating switch configured to receive a synchronous gating signal.
The invention provides a multi-chip system comprising a reference clock module and a plurality of chip modules. Each chip module comprises a first digital circuit, a second digital circuit and a phase-locked loop circuit. The first digital circuit is configured to receive an input clock signal. The second digital circuit is configured to output an output clock signal. The phase-locked loop circuit is coupled between the first digital circuit and the second digital circuit. The phase-locked loop circuit includes a delay coupled between the phase frequency detector and the frequency divider. The delayer carries out delay compensation on an output signal of the frequency divider and outputs the output signal to the phase frequency detector. The delay compensation is based on at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.
In one embodiment, the delays are digitally controlled delays.
In one embodiment, the delays respectively receive a control signal to adjust the corresponding delay compensation.
In an embodiment, the multi-chip system further includes an inter-chip delay detector coupled to the chip modules, the inter-chip delay detector respectively providing the control signals to the delays according to the output clock signals of the chip modules.
In one embodiment, the chip modules each include a clock gating switch configured to receive a synchronization gating signal.
The invention provides a phase-locked loop circuit which comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider and a delay. The phase frequency detector is configured to receive an input signal. The charge pump is coupled to the phase frequency detector. The loop filter is coupled to the charge pump. The voltage-controlled oscillator is coupled to the loop filter and configured to output an output signal. The frequency divider is coupled to the voltage-controlled oscillator and configured to divide the output signal by frequency to output a divided signal. The delay device is coupled to the frequency divider and the phase frequency detector and is configured to perform delay compensation on the frequency-divided signal of the frequency divider and output the frequency-divided signal to the phase frequency detector.
As described above, the delay compensation is provided by the delay device coupled between the phase frequency detector and the frequency divider in the pll circuit, so as to eliminate the problem of asynchronous clock due to the hardware difference between the clock input and output.
Drawings
FIG. 1 is a block diagram illustrating an exemplary synchronization module according to an embodiment of the invention.
Fig. 2A is an exemplary block diagram of a pll circuit according to an embodiment of the invention.
FIG. 2B is an example clock signal for each node in FIG. 2A.
FIG. 3 is a block diagram illustrating an exemplary synchronization module with a delay detector according to an embodiment of the present invention.
FIG. 4 is a block diagram illustrating an exemplary synchronization module with a clock gating switch according to an embodiment of the present invention.
FIG. 5 is an exemplary block diagram of a multi-chip system in accordance with one embodiment of the present invention.
FIG. 6 is a block diagram illustrating an inter-chip delay detector according to an embodiment of the present invention.
FIG. 7 is a block diagram of an exemplary multi-chip system with clock gating switches according to one embodiment of the present invention.
Description of main reference numerals:
100. synchronization module
110. First digital circuit
120. Second digital circuit
121. Clock gating switch
130. Phase-locked loop circuit
131. Phase frequency detector
132. Frequency divider
133. Delay device
134. Charge pump
135. Loop filter
136. Voltage controlled oscillator
140. Delay detector
200. Multi-chip system
210. Reference clock module
221,222,223,224 chip module
230. Inter-chip delay detector
2211,2221,2231,2241 clock gating switch
A, B, C, D nodes
cki input clock signal
cko output clock signal
Cn control signal
Sys synchronous gating signal
Detailed Description
The spirit of the present disclosure will be clearly illustrated by the accompanying drawings and detailed description, and any person skilled in the art, after having the knowledge of the embodiments of the present disclosure, can make changes and modifications by the techniques taught by the present disclosure, without departing from the spirit and scope of the present disclosure.
The terms "first," "second," …, and the like, as used herein, do not denote a particular order or sequence, nor are they intended to be limiting of the invention, but rather are merely used to distinguish one element or operation from another in the same technical terms. As used herein, the terms "comprising," "including," "having," "containing," and the like are intended to be inclusive and mean an inclusion, but not limited to.
The term (terms) as used herein generally has the ordinary meaning of each term as used in this field, in the disclosure herein, and in the special context, unless otherwise indicated. Certain words used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the invention.
In the drawings, the thickness of layers, plates, regions or spaces, etc. are exaggerated for clarity. Like numbers refer to like elements throughout. It will be understood that when an element such as a layer, plate, region or space is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or be with or without intervening elements present between the elements. As used herein, "connected" or "coupled" may refer to a physical and/or electrical connection. Furthermore, to simplify the drawings and emphasize what is presented in the drawings, existing structures or elements in the drawings may be depicted in a simple schematic manner or presented in an omitted manner.
In the drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished by following the reference label by a dash and a second label that is used to distinguish between similar components. If only a first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, irrespective of second or other subsequent reference labels.
As shown in fig. 1, a synchronization module 100 includes a first digital circuit 110, a second digital circuit 120, and a phase-locked loop circuit 130. The first digital circuit 110 is configured to receive an input clock signal cki. The second digital circuit 120 is configured to output an output clock signal cko. The phase-locked loop circuit 130 is coupled between the first digital circuit 110 and the second digital circuit 120. The pll circuit 130 includes a delay 133 coupled between the phase frequency detector 131 and the frequency divider 132. The delay device 133 outputs the output signal Do of the frequency divider 132 after delay compensation (i.e., the delayed signal Do') to the phase frequency detector 131. The delay compensation is at least one of a first delay time of the first digital circuit 110 and a second delay time of the second digital circuit 120.
Specifically, the first digital circuit 110 is coupled to an input side (e.g., an input terminal of the phase frequency detector 131) of the phase-locked loop circuit 130. The first digital circuit 110 receives the input clock signal cki and outputs the received clock signal cki to the input terminal of the phase frequency detector 131 of the phase-locked loop circuit 130. The input clock signal cki will cause a slight delay (i.e., a first delay time) through the first digital circuit 110. On the other hand, the second digital circuit 120 is coupled to an output side (e.g., an output terminal of the voltage-controlled oscillator 136) of the phase-locked loop circuit 130. The second digital circuit 120 receives the output of the pll circuit 130 and outputs the output clock signal cko after a slight delay (i.e., a second delay time). It should be noted that the values and/or lengths of the first delay time of the first digital circuit 110 and the second delay time of the second digital circuit 120 may be different due to differences in process, temperature and/or path.
As shown in fig. 2A, the pll circuit 130 may include, for example, a phase frequency detector 131, a charge pump 134, a loop filter 135, a voltage controlled oscillator 136, a frequency divider 132, and a delay 133. The charge pump 134 is coupled to the phase frequency detector 131 (in the embodiment of fig. 2A, the charge pump 134 may be integrated with the phase frequency detector 131). The loop filter 135 is coupled to the charge pump 134. The voltage-controlled oscillator 136 is coupled to the loop filter 135. The frequency divider 132 is coupled to the voltage-controlled oscillator 136 and configured to divide the output signal of the voltage-controlled oscillator 136 to output a divided signal (i.e., the output signal Do). The delay device 133 is coupled to the frequency divider 132 and the phase frequency detector 131, and is configured to delay-compensate the output signal Do of the frequency divider 132 and output the delay-compensated output signal to the phase frequency detector 131. In one embodiment, the delay 133 is preferably a Digital Control Delay (DCDL). It should be noted that the components and/or configurations of the pll circuit 130 are merely examples, and are not intended to limit the present invention, and any conventional circuit modifications made by those skilled in the art are within the scope of the present invention.
As shown in fig. 2B, fig. 2B is an exemplary clock signal diagram of each node of the phase-locked loop circuit 130 shown in fig. 2A. The node a is a signal of the input clock signal cki delayed by the first delay time td1 after passing through the first digital circuit 110. Node B compensates the post-CMP signal for the delay of node C via delay 133. Node C is the signal from node D after passing through the frequency divider 132. It should be noted that the frequency removal values shown in fig. 2B are only examples, and are not meant to limit the present invention. Node D is the signal output by vco 136. The output clock signal cko is a signal of the node D delayed by the second delay time td2 by the second digital circuit 120. It should be noted that the value of the delay compensation CMP shown in fig. 2B is merely an example, and the value of the delay compensation CMP may be at least one of the first delay time td1 and the second delay time td2. For example, the first delay time td1 or the second delay time td2 is compensated separately. Or selecting a proper compensation value after simulation according to the first delay time td1 and the second delay time td2.
In one embodiment, the delay 133 may receive the control signal Cn to adjust the value of the delay compensation. In this embodiment, the control signal Cn may be a digital signal. For example, after the digital control signal Cn is stored in the register (which may be written in advance of the register or adjusted according to the actual situation), the delay 133 reads the control signal Cn from the register. In one embodiment, the control signal Cn may be provided by any controller (e.g., microprocessor, FPGA, etc.). As shown in fig. 3, the synchronization module 100 further includes a delay detector 140 coupled between the first digital circuit 110 and the second digital circuit 120, and provides a control signal Cn to the delay device 133 according to the input clock signal cki and the output clock signal cko. Specifically, the delay detector 140 may determine a value of the required delay compensation CMP according to the asynchronization and/or delay between the input clock signal cki and the output clock signal cko, and generate the control signal Cn and output the delay 133 according to the value of the delay compensation CMP. The delay 133 can change its own delay parameter according to the control signal Cn to achieve the desired delay compensation CMP. The value of the delay compensation CMP can be dynamically adjusted according to the line condition or the element condition.
In one embodiment, as shown in fig. 4, the second digital circuit 120 of the synchronization module 100 further includes a clock gating switch 121 configured to receive the synchronization gating signal sys. In particular, the synchronous gating signal sys may be a clock signal (e.g., an external clock) that is different from the input clock signal cki. The clock gating switch 121 may control the second digital circuit 120 to output the output clock signal cko according to the synchronous gating signal sys. For example, when the synchronous gating signal sys is high (digital 1), the second digital circuit 120 can output the output clock signal cko. Conversely, when the synchronous gating signal sys is low (digital 0), the second digital circuit 120 cannot output the output clock signal cko. The synchronization of the synchronization module 100 can be more accurate by synchronizing the gating signal sys with the clock gating switch 121. Specifically, when there are more systems (e.g., multi-chip systems) that need to be synchronized, each chip in the multi-chip system can be operated at substantially the same clock interval by synchronizing the gating signal sys with the clock gating switch 121 as a coarse adjustment. At this time, the phase-locked loop circuit 130 with the delay 133 can be used for fine tuning, so that the synchronization of the synchronization module 100 is more accurate. It should be noted that the configuration of the clock gating switch 121 is only an example and is not a limitation of the present invention. The clock gating switch 121 may also be located at any suitable node in the synchronization module 100.
In one embodiment, as shown in FIG. 5, FIG. 5 illustrates a multi-chip system 200 including a reference clock module 210 and a plurality of chip modules 221-224. Each of the chip modules 221-224 includes a first digital circuit 110, a second digital circuit 120, and a phase locked loop circuit 130, respectively, of the synchronization module 100. The first digital circuit 110 is configured to receive an input clock signal cki generated by the reference clock module 210. The second digital circuit 120 is configured to output clock signals cko1-cko4. Synchronization between the output clock signals cko1-cko4 is thereby achieved by the respective phase-locked loop circuits 130 of the chip modules 221-224.
Specifically, the clock inputs of the chip modules 221-224 are all the input clock signal cki generated by the reference clock module 210. However, because of hardware differences in processes or lines (e.g., delays generated by the respective first and/or second digital circuits of the chip modules 221-224 are not the same), differences (i.e., dyssynchrony) are generated between the output clock signals cko1-cko4 of the chip modules 221-224. The respective phase-locked loop circuits of the chip modules 221-224 may perform delay compensation by their delays according to the delays of the respective first digital circuits and/or second digital circuits, thereby achieving clock synchronization between the chip modules 221-224. For example, the pll circuit of the chip module 221 may have a first delay compensation, and the value of the first delay compensation is determined according to the delay of the first digital circuit and/or the second digital circuit of the chip module 221. On the other hand, the pll circuit of the chip module 222 may have a second delay compensation, and the value of the second delay compensation is determined according to the delay of the first digital circuit and/or the second digital circuit of the chip module 222. The value of the first delay compensation may be the same as or different from the value of the second delay compensation, and may be adjusted depending on the actual situation. In one embodiment, the delays of the chip modules 221-224 may also receive different control signals to adjust the corresponding delay compensation values. For example, a delay in the chip module 221 that generates a first delay compensation may receive the first control signal; the second control signal may be received by a delay in the chip module 222 that generates a second delay compensation. It should be noted that the present invention is not limited to the number of the chip modules in fig. 5, and those skilled in the art can adjust the chip modules according to actual needs.
Alternatively, as shown in FIG. 6, multi-chip system 200 may include an inter-chip delay detector 230 coupled between chip modules 221-224. The inter-chip delay detector 230 provides control signals Cn1-Cn4 to corresponding delays according to the output clock signals cko1-cko4 of the chip modules 221-224, respectively. Specifically, the output clock signals cko1-cko4 may correspond to the input clock signal cki generated by the reference clock module 210, and the inter-chip delay detector 230 may determine a ratio of a difference or an out-of-sync between the output clock signals cko1-cko4 and the input clock signal cki. Thereby providing control signals Cn1-Cn4 to the corresponding delays to adjust the value of the delay compensation of the delays. For example, the control signal Cn1 is provided to the delay of the chip module 221 to adjust the value of the first delay compensation; the control signal Cn2 is provided to the delay of the chip module 221 to adjust the value of the second delay compensation. Thereby achieving clock synchronization between the chip modules 221-224. It should be noted that the control signals Cn1-Cn4 can also be determined by simulation or by a related process parameter.
In one embodiment, as shown in FIG. 7, the chip modules 221-224 may each include a clock gating switch 2211-2241 configured to receive a synchronous gating signal sys. Specifically, the clock gating switches 2211-2241 can control the input or output of the clock signals of the chip modules 221-224 according to the synchronous gating signal sys. For example, when the clock gating switches 2211-2241 are disposed in the respective second digital circuits of the chip modules 221-224, the second digital circuits can output the output clock signals cko1-cko4 when the synchronous gating signal sys is in a high state (digital 1). Conversely, when the synchronous gating signal sys is low (digital 0), the second digital circuit cannot output the output clock signals cko1-cko4. On the other hand, when the clock gating switches 2211-2241 are disposed in the first digital circuits of the chip modules 221-224, the chip modules 221-224 can receive the input clock signal cki when the synchronous gating signal sys is in a high state (digital 1); when the synchronous gating signal sys is low (digital 0), the chip module 221-224 cannot receive the input clock signal cki. Clock synchronization between the chip modules 221-224 of the multi-chip system 200 may be more accurate by synchronizing the gating signal sys with the clock gating switches 2211-2241.
The invention has been described with respect to the above-described embodiments, however, the above-described embodiments are merely examples of practicing the invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. On the contrary, it is intended to cover modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (11)
1. A synchronization module, comprising:
a first digital circuit configured to receive an input clock signal;
a second digital circuit configured to output an output clock signal; and
a phase-locked loop circuit coupled between the first digital circuit and the second digital circuit, comprising:
the delay device is coupled between a phase frequency detector and a frequency divider, and outputs an output signal of the frequency divider to the phase frequency detector after performing delay compensation;
the delay compensation is based on at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.
2. The synchronization module of claim 1 wherein the delay is a digitally controlled delay.
3. The synchronization module of claim 1 wherein the delay device receives a control signal to adjust the delay compensation.
4. The synchronization module of claim 3, further comprising:
and a delay detector coupled between the first digital circuit and the second digital circuit and providing the control signal to the delay according to the input clock signal and the output clock signal.
5. The synchronization module of claim 1, wherein the second digital circuit further comprises a clock gating switch configured to receive a synchronization gating signal.
6. A multi-chip system, comprising:
a reference clock module configured to generate an input clock signal; and
a plurality of chip modules;
wherein each of the plurality of chip modules comprises:
a first digital circuit configured to receive the input clock signal;
a second digital circuit configured to output an output clock signal; and
a phase-locked loop circuit coupled between the first digital circuit and the second digital circuit, comprising:
the delay device is coupled between a phase frequency detector and a frequency divider, and outputs an output signal of the frequency divider to the phase frequency detector after performing delay compensation;
the delay compensation is at least one of a first delay time of the first digital circuit and a second delay time of the second digital circuit.
7. The multi-chip system of claim 6, wherein the delays are a digitally controlled delay.
8. The multi-chip system of claim 6, wherein the delays each receive a control signal to adjust the corresponding delay compensation.
9. The multi-chip system of claim 8, further comprising:
the inter-chip delay detector is coupled to the chip modules and respectively provides the control signals to the delays according to the output clock signals of the chip modules.
10. The multi-chip system of claim 6, wherein the chip modules each comprise a clock gating switch configured to receive a synchronization gating signal.
11. A phase locked loop circuit comprising:
a phase frequency detector configured to receive an input signal;
a charge pump coupled to the phase frequency detector;
a loop filter coupled to the charge pump;
a voltage-controlled oscillator coupled to the loop filter and configured to output an output signal;
a frequency divider coupled to the voltage-controlled oscillator and configured to divide the output signal by frequency to output a divided signal; and
and the delayer is coupled with the frequency divider and the phase frequency detector, and is configured to perform delay compensation on the frequency-divided signal of the frequency divider and output the frequency-divided signal to the phase frequency detector.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111114716A TWI815402B (en) | 2022-04-18 | 2022-04-18 | Multichip system with synchronization module and phase locked loop circuit thereof |
| TW111114716 | 2022-04-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116961647A true CN116961647A (en) | 2023-10-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210637178.1A Pending CN116961647A (en) | 2022-04-18 | 2022-06-07 | Multi-chip system with synchronous module and phase-locked loop circuit applicable to same |
Country Status (2)
| Country | Link |
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| CN (1) | CN116961647A (en) |
| TW (1) | TWI815402B (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005060472B3 (en) * | 2005-12-17 | 2007-04-26 | Atmel Germany Gmbh | Phase-locked loop-frequency generator for transmitting-/receiving device, has control unit including sigma-delta-modulator and designed to determine control words depending on signal that is provided by sigma-delta-modulator |
| US7579886B2 (en) * | 2006-12-07 | 2009-08-25 | Cadence Design Systems, Inc. | Phase locked loop with adaptive phase error compensation |
| US8373462B2 (en) * | 2011-05-19 | 2013-02-12 | Nanya Technology Corp. | Delay lock loop and delay lock method |
| US9413364B2 (en) * | 2014-07-09 | 2016-08-09 | Intel Corporation | Apparatus and method for clock synchronization for inter-die synchronized data transfer |
| US10090845B1 (en) * | 2017-03-28 | 2018-10-02 | Stmicroelectronics International N.V. | Fraction-N digital PLL capable of canceling quantization noise from sigma-delta modulator |
| US10496127B1 (en) * | 2018-06-04 | 2019-12-03 | Linear Technology Holding Llc | Multi-chip timing alignment to a common reference signal |
| US10727838B2 (en) * | 2018-07-13 | 2020-07-28 | Qualcomm Incorporated | Systems and methods for power conservation in a phase locked loop (PLL) |
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- 2022-04-18 TW TW111114716A patent/TWI815402B/en active
- 2022-06-07 CN CN202210637178.1A patent/CN116961647A/en active Pending
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| Publication number | Publication date |
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| TW202343978A (en) | 2023-11-01 |
| TWI815402B (en) | 2023-09-11 |
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