JPH06141027A - Synchronizing signal supply device - Google Patents

Abstract

PURPOSE:To prevent an error from occurring in communication data passing a device by blocking a second clock by outputting a phase control signal to an AND circuit when an unmatched clock between a system in current use and a spare system and spare information are inputted. CONSTITUTION:When the spare information is inputted due to the unmatch of the phases of distribution clocks D1 and D2, a phase comparator 7 outputs the phase control signal P2. The AND circuit 5b stops the output of the second clock C2, from a PLL 4b at every input of the phase control signal P2. The phase comparator 7 inputs the clocks D1, D2 to an EXOR, and the OR output of the EXOR is inputted to an OR circuit via a delay circuit, and the output of the OR circuit to which the spare information is directly inputted and the clock C2 from the PLL are inputted to an FF. Thereby, when the system 1 of the clock D2 is set as the spare system, the systems 0 and 1 of the clock D1 are inputted to the comparator 7, and furthermore, the phase control signal P2 which makes the clock D track an operation side by the input of the spare information is generated. The error can be prevented from occurring in signal data in the device by blocking the clock when the signal P2 is inputted to a frequency divider 6b by the circuit 5b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal supplying device, and more particularly to a synchronizing signal supplying device for supplying a synchronizing clock to a communication device in a redundant configuration of an active system and a standby system.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of an example of a conventional synchronizing signal supply device. The first and second synchronization signals A and B of the working (0) system and the standby (1) system of the redundant configuration are respectively set to N.
(N is a positive integer) Frequency-divided first and second branch signals A1, B
The receiving units 11a and 11b and the frequency doubling unit 12 that output 1
a, 12b, selectors 13a, 13b for selectively outputting the first or second branch signal A1 or B1, and first and second clocks C1, C2 synchronized with the branch signal A1 or B1, respectively. PLLs 14a and 14b that oscillate and output, and a frequency divider 1 that divides the first and second clocks C1 and C2 by 1/4 and outputs as divided clocks D1 and D2 for the active system and the standby system.
6a and 16b.

As described above, each system has a redundant system so that the operation of the system is guaranteed even if one system fails.

[0004]

In this conventional synchronizing signal supply device, in the redundant system, the clock distribution PLL and the frequency dividing circuit operate independently in the 0-system and the 1-system, respectively. In the redundant switching, there is a drawback that the clock supplied to the device is erroneous due to the phase mismatch of the distributed clocks and the error in the duty is correct and an error occurs in the signal data passing through the device.

[0005]

In the synchronizing signal supply circuit of the present invention, the first and second synchronizing signals of the active system and the standby system are respectively frequency-divided by N (N = a positive integer). Output means as a branch signal, means for selectively outputting the first or second branch signal, means for oscillating and outputting first and second clocks synchronized with the selected output, and the first and second Means for dividing the output of the AND circuit for inputting the second clock and the phase control signal by 1 / N and outputting it as a distribution clock for the active system and the standby system; and for the standby system when the information from the standby side is input. Means for stopping the phase control signal input to the AND circuit.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

In the present embodiment, the first and second synchronizing signals A and B of the working (0) system and the standby (1) system are respectively multiplied by N to obtain the first synchronization signal.
And the receiving unit 1 that outputs the second branch signals A1 and B1.
a, 1b and frequency doublers 2a, 2b, and selectors 3a, 3b for selectively outputting the first or second branch signal A1 or B1,
PLLs 4a and 4b for oscillating and outputting first and second clocks C1 and C2 respectively synchronized with the branch signal A1 or B1
And the outputs of the AND circuits 5a and 5b for inputting the first and second clocks C1 and C2 and the phase control signals P1 and P2 to 1
/ N and frequency dividers 6a and 6b for outputting as distributed clocks D1 and D2 of the active system and the standby system, and a phase control signal P2 input to the AND circuit 5b of the standby system when information from the standby side is input. And a phase comparator 7 for stopping the operation.

FIG. 3 is a timing chart for explaining the operation of this embodiment. When the phases of the distributed clocks D1 and D2 do not match and the spare side information is input, the phase comparator 7 outputs the phase control signal P2. The AND circuit 5b stops the output of the second clock C2 from the PLL 4b every time the phase control signal P2 is input. FIG. 4 is a detailed block diagram of the phase comparator of this embodiment. The distributed clocks D1 and D2 are input to the exclusive OR circuit EXOR, and the OR outputs thereof are input to the OR circuits ORa and b via the delay circuit, respectively, and the OR circuit ORb to which the spare side information is directly input is input.
And the clock C2 from the PLL 4b are input to the flip-flop FF.

In this way, when one sequence in the distribution clock D2 is the backup system, the distribution clock D
The 0-system and 1-system of 1 are input to the phase comparator 7, and the phase control signal P2 that causes the distributed clock D2 on the spare side to follow the operating side is generated by the input of the spare-side information. By shutting off the clock that the phase control signal P2 inputs from the PLL 4b to the frequency divider 6b by the AND circuit 5b, the phase of the distribution clock D2 on the protection side always follows the operation side, so that the distribution clocks that have been switched are almost missed. Does not occur and the signal data passing through the device is error free.

[0010]

As described above, according to the present invention, the first and second synchronizing signals of the active system and the standby system are respectively multiplied by N (N = a positive integer) to generate the first and second branch signals. Means for outputting, means for selectively outputting the first or second branch signal, means for oscillating and outputting first and second clocks synchronized with the selected output, and first and second clocks And means for dividing the output of the AND circuit for inputting the transfer control signal by 1 / N and outputting it as a distribution clock for the active system and the standby system,
When the information from the spare side is input, the AND of the spare system
By providing the circuit with the means for stopping the input phase control signal, the switched distribution clock is not missed, and the signal data passing through the device has no effect.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a conventional synchronization signal supply device.

FIG. 3 is a timing chart for explaining the operation of the present embodiment.

FIG. 4 is a detailed block diagram of a phase comparator of the present embodiment.

[Explanation of symbols]

 1a, 1b Receiver 2a, 2b Frequency Division 3a, 3b Selector 4a, 4b Pull-In Oscillator (PLL) 5a, 5b AND Circuit 6a, 6b Frequency Divider 7 Phase Comparator

Claims (1)

[Claims] 1. Means for multiplying each of the first and second synchronization signals of the active system and the standby system by N (N = a positive integer) and outputting them as first and second branch signals, and the first or second branch signal. Means for selectively outputting the second branch signal, and first means for synchronizing with the selected output
And a means for oscillating and outputting the second clock, and the output of the AND circuit for inputting the first and second clocks and the phase control signal is divided by 1 / N and output as a distribution clock for the active system and the standby system. And a means for stopping the phase control signal input to the AND circuit of the spare system when information from the spare side is input.