JP2011114668A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can verify cross-talk resistance under various conditions in the earlier stage of development. <P>SOLUTION: The semiconductor device includes a signal generating circuit 3, delay circuits 40, 41, 42, 43, ..., and 4m, delay circuits 50, 51, 52, 53, ..., and 5m, and selecting circuits 60, 61, 62, 63, ..., and 6m respectively provided corresponding to output buffers 70, 71, 72, 73, ..., and 7m to select any one of the signals outputted from the delay circuits 40, 41, 42, 43, ..., and 4m or the delay circuits 50, 51, 52, 53, ..., and 5m and output the signal selected to the corresponding output buffers 70, 71, 72, 73, ..., and 7m. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device capable of evaluating noise resistance such as crosstalk.

  In systems equipped with semiconductors in recent years, wiring crosstalk has become a problem due to higher communication speed and higher pattern density on a PCB (Printed Circuit Board). For example, wiring to a DDR (Double Data Rate) memory is a multi-bit parallel wiring, high-speed transfer, low voltage, and it is difficult to maintain signal quality. In particular, when they are adjacent to each other with long wiring, they are affected by crosstalk, and the waveform of the data to be transferred may be disturbed, resulting in the worst value.

  Wiring crosstalk will be described with reference to FIGS. Wiring crosstalk occurs when the adjacent sections are long, such as the signal lines A and B in FIG. 10, and the adjacent signals rise and fall when the distance between the adjacent wirings is short. Affected by. Since the signal line A and the signal line B are adjacent to each other, the rise of the signal line A appears in the signal of the signal line B, for example, as shown in the waveform of FIG. Appears on line A signal. Such an influence disappears as shown in FIG. 11 if a certain distance is separated like the signal line B and the signal line C in FIG. In addition, as shown in FIG. 12, even if the signal lines A and C are fixed at the low level, when the signal on the signal line B rises, the signal line A may be ringed.

  Also, the higher the signal, the shorter the slew rate time, thereby increasing the crosstalk. In some cases, when a signal such as a clock that alternately alternates between a low level and a high level is adjacent to a signal having a fixed low level, the signal may be seen as a pulse signal even though the signal has a fixed low level.

  Conventionally, the effects of crosstalk were virtually tested by chip simulation and board simulation, and measures were taken against the wiring of the semiconductor device and the wiring of the board to be mounted, but when installed in the actual system, There has been a problem that there are many subsequent detections such as a problem of crosstalk that has been hidden due to power supply noise, EMI (Electro magnetic interference), and the like.

  As a noise test of an output signal of a semiconductor device, for example, a semiconductor integrated device described in Patent Document 1 has been proposed. The semiconductor integrated device described in Patent Document 1 is provided with a test circuit for testing simultaneous switching noise.

  The semiconductor integrated device described in Patent Document 1 has a built-in test circuit that can test simultaneous switching noise, and does not consider crosstalk noise of wiring other than simultaneous switching noise. For this reason, it was impossible to set conditions for generating the maximum crosstalk noise or to observe the effects of asynchronous pulses.

  The present invention aims to solve such problems.

  That is, an object of the present invention is to provide a semiconductor device capable of confirming crosstalk resistance by changing conditions at an early stage of development.

  According to a first aspect of the present invention, there is provided a semiconductor device comprising: a logic circuit that performs a predetermined logic operation; and a plurality of output buffers that respectively output a plurality of signals output from the logic circuit to the outside. A signal generation circuit for generating a noise tolerance test signal having a predetermined frequency; a first delay circuit for adjusting a delay time for each signal output from the logic circuit; and a signal output from the signal generation circuit And a second delay circuit that adjusts the delay time of each of the plurality of output buffers, and a signal output from the first delay circuit or a signal output from the second delay circuit. And a selection circuit that selects one of them and outputs it to the corresponding output buffer.

  The invention described in claim 2 is characterized in that, in the invention described in claim 1, the signal generation circuit can output a signal having a frequency different from the frequency of the signal output from the logic circuit. To do.

  According to the invention described in claim 1, a signal generation circuit that generates a noise tolerance test signal having a predetermined frequency, a first delay circuit that adjusts the delay time for each signal output from the logic circuit, A second delay circuit for adjusting a delay time of the signal output from the signal generation circuit, and a signal output from the first delay circuit or a second delay circuit provided corresponding to each of the plurality of output buffers. And a selection circuit that selects one of the output signals and outputs the selected signal to the corresponding output buffer, so that a signal for noise tolerance test is output by the signal generation circuit to be a signal to be tested for crosstalk. On the other hand, it is possible to generate crosstalk noise. The target signal can be set in any combination by the selection circuit, so that it is possible to determine which signal on the bus is the most dangerous and to understand which problem has occurred. By setting the delay circuit, it is possible to test by creating various states.

  According to the second aspect of the present invention, since the signal generation circuit can output a signal having a frequency different from the frequency of the signal output from the logic circuit, various states can be automatically created by delay setting. It becomes possible to produce.

1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the delay circuit shown in FIG. 1. FIG. 2 is a waveform diagram showing a signal output from the signal generation circuit shown in FIG. 1 and a delay by a delay circuit. FIG. 2 is a waveform diagram showing a state of crosstalk of the semiconductor device shown in FIG. 1. FIG. 2 is a waveform diagram showing a state of crosstalk of the semiconductor device shown in FIG. 1. FIG. 2 is a waveform diagram showing a state of crosstalk of the semiconductor device shown in FIG. 1. It is a wave form diagram which shows the state of the crosstalk in the case of the asynchronous pulse of the semiconductor device shown by FIG. 2 is a flowchart of a crosstalk confirmation test of the semiconductor device shown in FIG. 2 is a flowchart of a crosstalk confirmation test in a case where there is a mechanism capable of performing the structuring process of the semiconductor device shown in FIG. It is explanatory drawing of the wiring state in which crosstalk occurs. It is a wave form diagram of a crosstalk waveform. It is a wave form diagram of a crosstalk waveform.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the delay circuit shown in FIG. FIG. 3 is a waveform diagram showing a signal output from the signal generation circuit shown in FIG. 1 and a delay by the delay circuit. FIG. 4 is a waveform diagram showing a state of crosstalk of the semiconductor device shown in FIG. FIG. 5 is a waveform diagram showing a state of crosstalk of the semiconductor device shown in FIG. FIG. 6 is a waveform diagram showing a state of crosstalk of the semiconductor device shown in FIG. FIG. 7 is a waveform diagram showing the state of crosstalk in the case of the asynchronous pulse of the semiconductor device shown in FIG. FIG. 8 is a flowchart of a crosstalk confirmation test of the semiconductor device shown in FIG. FIG. 9 is a flowchart of a crosstalk confirmation test in the case where there is a mechanism capable of performing the structuring process of the semiconductor device shown in FIG.

  FIG. 1 shows a semiconductor device 1 according to an embodiment of the present invention. 1 includes a logic circuit 20, 21, 22, 23,..., 2m, a signal generation circuit 3, and delay circuits 40, 41, 42, 43,. 4m, delay circuits 50, 51, 52, 53,..., 5m as second delay circuits, multiplexers 60, 61, 62, 63,..., 6m as selection circuits, and output buffers 70, 71, 72 , 73,..., 7m.

  The logic circuits 20, 21, 22, 23,..., 2 m are circuits that perform various logical operation processes in the semiconductor device 1. Note that the logic circuits 20, 21, 22, 23,..., 2m are not independent circuit blocks, but are one or a combination of several circuit blocks, and m + 1 signals may be output therefrom. Good.

  The signal generation circuit 3 is a circuit that outputs a pulse signal having a predetermined frequency (for example, the same frequency as the logic circuits 20, 21, 22, 23,..., 2m).

  The delay circuit 40 delays the signal output from the logic circuit 20 by a predetermined delay time. The delay circuit 41 delays the signal output from the logic circuit 21 by a predetermined delay time. The delay circuit 42 delays the signal output from the logic circuit 22 by a predetermined delay time. The delay circuit 43 delays the signal output from the logic circuit 23 by a predetermined delay time. The delay circuit 4m delays the signal output from the logic circuit 2m by a predetermined delay time. Of course, the delay circuits 40, 41, 42, 43,..., 4m can independently set the delay time.

  The delay circuits 50, 51, 52, 53,..., 5m delay the signal output from the signal generation circuit 3 by a predetermined delay time. Of course, each of the delay circuits 50, 51, 52, 53,..., 5m can set the delay time independently.

  The delay circuits 40, 41, 42, 43, ..., 4m and the delay circuits 50, 51, 52, 53, ..., 5m are configured as shown in FIG. FIG. 2 representatively illustrates a delay circuit 50. As shown in FIG. 2, the delay circuit 50 includes delay cells 501, 502, 503,..., 50 (N−1), 50 (N−2), 50N, and a multiplexer 50a.

  Delay cells 501, 502, 503,..., 50 (N−1), 50 (N−2), and 50 N are delay cells having the same delay value, and each of the delay cells 501, 502, and 503 is a delay cell. ..., the delay cell 50 (N-1), the delay cell 50 (N-2), and the delay cell 50N are connected in series in this order. The delay cell 501, the delay cell 502, the delay cell 503,..., The delay cell 50 (N-1), the delay cell 50 (N-2), and the delay cell 50N have their outputs connected to the multiplexer 50a. . Then, by selecting with the selection signal SEL, a signal to which a target delay is added can be selected.

  For example, if the number of delay stages is 0, the input terminal 0 is selected by the multiplexer 50a, and if the number of delay stages is 7, the input terminal 7 is selected by the multiplexer 50a. The number of bits of the selection signal SEL of the multiplexer 50a is 1 bit if there are two types of delay signals, 2 bits if there are 3 to 4 types of delay signals, and 3 bits if there are 5 or 8 types of delay signals. The selection signal SEL may be set by a user in a storage circuit such as a register, or may be set by automatic adjustment by calibration, such as a delay adjustment circuit of a DDR memory. It is assumed that the delay adjustment can be reset by user setting.

  Further, for example, when the reference delay stage number setting is 4, the delay stage number 0 is a propagation delay value of 1 cell × 4 in the minus direction from the reference, and the delay stage number 7 is 1 cell propagation in the plus direction from the reference. A delay value × 3 delay values can be set. Generally, a delay value of several tens of picoseconds per stage is set, and a fine setting is made with the width to adjust the skew. Although not particularly used in this embodiment, automatic setting by calibration is also performed.

  The multiplexer 60 selects the output signal of the delay circuit 40 and the output signal of the delay circuit 50. When the selection terminal SEL0 is 0, the output signal of the delay circuit 40 is selected, and when the selection terminal SEL0 is 1, the output signal of the delay circuit 50 is selected. The multiplexer 61 selects the output signal of the delay circuit 41 and the output signal of the delay circuit 51. When the selection terminal SEL1 is 0, the output signal of the delay circuit 41 is selected, and when the selection terminal SEL1 is 1, the output signal of the delay circuit 51 is selected. The multiplexer 62 selects the output signal of the delay circuit 42 and the output signal of the delay circuit 52. When the selection terminal SEL2 is 0, the output signal of the delay circuit 42 is selected, and when the selection terminal SEL2 is 1, the output signal of the delay circuit 52 is selected. The multiplexer 63 selects the output signal of the delay circuit 43 and the output signal of the delay circuit 53. When the selection terminal SEL3 is 0, the output signal of the delay circuit 43 is selected. When the selection terminal SEL3 is 1, the output signal of the delay circuit 53 is selected. The multiplexer 6m selects the output signal of the delay circuit 4m and the output signal of the delay circuit 5m. When the selection terminal SELm is 0, the output signal of the delay circuit 4m is selected, and when the selection terminal SELm is 1, the output signal of the delay circuit 5m is selected.

  The output buffer 70 is an output buffer for outputting the signal output from the multiplexer 60 to the outside of the semiconductor device 1, and the output signal of the output buffer 70 is the DATA0 output. The output buffer 71 is an output buffer for outputting the signal output from the multiplexer 61 to the outside of the semiconductor device 1, and the output signal of the output buffer 71 becomes the DATA1 output. The output buffer 72 is an output buffer for outputting the signal output from the multiplexer 62 to the outside of the semiconductor device 1, and the output signal of the output buffer 72 becomes the DATA2 output. The output buffer 73 is an output buffer for outputting the signal output from the multiplexer 63 to the outside of the semiconductor device 1, and the output signal of the output buffer 73 becomes the DATA3 output. The output buffer 7m is an output buffer for outputting the signal output from the multiplexer 6m to the outside of the semiconductor device 1, and the output signal of the output buffer 7m is the DATAm output.

  That is, the output signals from the logic circuits 20, 21, 22, 23,..., 2m to the delay circuits 40, 41, 42, 43,..., 4m, and the signal generation circuit 3 to the delay circuits 50, 51, 52, 53 ,..., 5m selects the output signal via multiplexers 60, 61, 62, 63,..., 6m by select signal SELi (i = 0, 1, 2,..., M; m is the DATA bus width) When the select signal SELi is “0”, a signal from a normal logic circuit is output, and when the select signal SELi is “1”, a signal from the signal generation circuit 3 is output.

  In the present embodiment, for example, the signal generation circuit 3 outputs a pulse signal having the same frequency as the DATA output signal. This pulse signal is treated as an aggressor (a side that affects crosstalk). Then, in the DATA output, the victim (victim; the side affected by the crosstalk) is set, the delay setting is changed little by little to create the worst condition, and the value of the operation result is verified.

  Next, the state of signal waveforms during operation of the semiconductor device 1 having the above-described configuration will be described.

  First, the output signal to the DATA0 output, the output signal to the DATA1 output, and the output signal to the DATA3 output in FIG. 1 are set as an aggressor. That is, the select signals SEL0, SEL1, and SEL3 of the multiplexers 60, 61, and 63 for the DATA0 output, the DATA1 output, and the DATA3 output are set to “1”. The DATA2 output is a victim, that is, the select signal SEL2 of the DATA2 output multiplexer 62 is set to "0". A normal signal (output signal of the logic circuit 22) is output as the DATA2 output.

  The waveform in FIG. 3 is a waveform when the signal generating circuit 3 is used as an oscillator, and the upper waveform is obtained when the delay setting is set as a reference point, and the middle waveform is a negative delay with respect to the upper waveform. The lower waveform is obtained by setting the delay to the plus side with respect to the upper waveform.

  The signal from the signal generation circuit 3 generates a pulse signal having the same frequency as the signal output from the DATA output. The signal from the signal generator 3 is transmitted to the DATA0 output, the DATA1 output, and the DATA3 output, and the output signal of the logic circuit 22 is output as the DATA2 output. The ideal signal of the DATA2 output at this time is a signal that is not affected by the DATA0 output, the DATA1 output, and the DATA3 output, and can maintain the signal quality of the output signal of the logic circuit 22 as it is, but it is actually affected by the crosstalk. For this reason, the waveform becomes distorted, and the distorted waveform is output. When such a waveform is obtained, for example, when data is written as a data signal in a memory or the like, the logic may change depending on the signal in the memory on the receiving side, and the data may fail.

  Examples of the influence of crosstalk on the DATA2 output when the signal shown in FIG. 3 is output to the DATA0 output, the DATA1 output, and the DATA3 output are shown in FIGS.

  In FIG. 4, a pulse signal with a reference delay is output as an aggressor, and ringing occurs in the output signal due to the rise and fall of the aggressor.

  FIG. 5 shows a case where the signal delay of the signal generation circuit 3 is set to the minus side, and ringing is also generated by the aggressor.

  FIG. 6 shows a case where the signal delay of the signal generating circuit 3 is set to the plus side, and the rise and fall times of the aggressor and the victim are the same. Overshoot is happening when both stand up at the same time.

  In the configuration described above, since the signal of the signal generation circuit 3 and the frequency of the DATA output are synchronized, the skew adjustment is performed by the user on the setting side. The user can create the worst crosstalk state by gradually changing the delay setting value by software or hardware.

  Next, the waveform when the frequency of the pulse signal of the signal generation circuit 3 of the present invention is set to a frequency different from the frequency of the signal output from the DATA output is shown.

  FIG. 7 shows the case of an asynchronous pulse signal. In FIG. 7, the frequency of the pulse signal of the signal generator 3 is 210 MHz and is output to the DATA0 output and the DATA2 output, and the normal signal output from the logic circuit 21 is output to the DATA1 output at a cycle of 200 MHz. That is, the DATA0 output and the DATA2 output are aggressors, and the DATA1 output is a victim. Since the operating frequencies are different, it is possible to see the effects of various crosstalks, such as switching with the same logic at the same time, switching with different logics.

  The waveform portion of FIG. 7A is a pattern in which noise appears due to the DATA1 output due to the rise of the adjacent DATA0 output and DATA2 output, but the waveform collapses due to the rise of the DATA1 output. The waveform portion B is a pattern in which the waveform collapses when the rising of the DATA0 output and the DATA2 output crosses the falling of the DATA1 output. In the portion C, the rise of the DATA0 output and the DATA2 output appears immediately before the rise of the DATA1 output, and the waveform is broken. The portion D is a pattern in which the rise of the DATA0 output and the DATA2 output coincides with the rise of the DATA1 output, and an overshoot occurs.

  Next, the crosstalk confirmation test flow in this embodiment will be described with reference to FIG.

  First, in step S101, control is performed so that the corresponding selection signal SELi is “0” with the signal to be inspected as a victim, and the process proceeds to step S102. Control uses register settings and external terminal settings. The aggressor controls the corresponding selection signal SELi to be “1”. The control also uses register settings and external terminal settings.

  Next, in step S102, the delay value of each signal is set, and the process proceeds to step S103. The delay value needs to be adjusted so that the phases match if simultaneous switching is used. The case where crosstalk is a problem is when the victim signal to be inspected rises or rises and all other aggressors rise or start to rise at the same time. Perform delay adjustment. That is, the signal generation circuit 3 is operated in this step.

  Next, in step S103, data is transferred from the circuit corresponding to the output terminal set to the victim among the logic circuits 20, 21, 22, 23,..., 2m, and the process proceeds to step S104.

  Next, in step S104, it is confirmed whether the data signal transferred in step S103 is recognized as correct logic by checking the waveform at an observation point, for example, an oscilloscope, or by writing data if it is a memory. If it is a memory, write the data and then read it to check the correctness of the value. Since the aggressor signal is a signal from the signal generation circuit 3, it is necessary to mask the value when confirming the value, that is, to prevent the determination.

  In addition, there is no problem with the combination of Aggressa and Victim. For example, when there are 16 data buses, one may be a victim, the other 15 may be an aggressor, an odd-numbered data signal may be an aggressor, and an even-numbered data signal may be a victim.

  Further, when there is a mechanism capable of performing structured processing, such as a processor, on the controller side that adjusts each delay circuit or switches multiplexers, the flow shown in FIG. 9 can be taken. The flow of FIG. 9 will be described.

  First, in step S201, the values of variables i, j, and k are reset (set to “0”), and the process proceeds to step S202.

  Next, in step S202, the aggressor target is set to DATAi output, the victim is set to other DATA output, and the process proceeds to step S203. For example, when the process proceeds from step S201, the DATA0 output is an aggressor, and the data after the DATA1 output is a victim.

  Next, in step S203, the victim delay is set to the value of the variable j, and the process proceeds to step S204. That is, since the variable j = 0 at the beginning, the input 0 that does not pass through the delay cell is selected from the inputs of the multiplexer 50a in the circuit of FIG.

  Next, in step S204, the delay of the aggressor is set to the value of the variable k, and the process proceeds to step S205. That is, since the variable k = 0 at first, the input 0 that does not pass through the delay cell is selected from the inputs of the multiplexer 50a in the circuit of FIG.

  Next, in step S205, data is transferred from the circuit set as victim among the logic circuits 20, 21, 22, 23,..., 2m, and the process proceeds to step S206. Of course, the signal generating circuit 3 starts its operation before this step.

  Next, in step S206, the result is confirmed in the same manner as the flow of FIG. 8, and the process proceeds to step S207.

  Next, in step S207, it is determined whether or not the variable k is the maximum value. If the variable k is the maximum value (Y), the process proceeds to step S208. If not (N), the process proceeds to step S210.

  Next, in step S208, it is determined whether or not the variable j is the maximum value. If the variable j is the maximum value (Y), the process proceeds to step S209. If not (N), the process proceeds to step S211.

  Next, in step S209, it is determined whether or not the variable i is the maximum value. If the variable i is the maximum value (Y), the process ends. If not (N), the process proceeds to step S212.

  On the other hand, in step S210, the value of variable k is incremented (+1), and the process returns to step S204.

  In step S211, the value of variable j is incremented (+1) and the value of variable k is reset (set to “0”), and the process returns to step S203.

  In step S212, the value of variable i is incremented (+1), and the process returns to step S202.

  That is, according to the flow shown in FIG. 9, a combination of delay setting, aggressor, and victim can be implemented for various patterns by a loop in the program. For this reason, the influence of various crosstalks can be seen without confirming the delay setting.

  According to this embodiment, the signal generation circuit 3, the delay circuits 40, 41, 42, 43,..., 4m, the delay circuits 50, 51, 52, 53,. , 73,..., 7m, respectively. The signals output from the delay circuits 40, 41, 42, 43,..., 4m or the delay circuits 50, 51, 52, 53,. .., 6m for selecting one of the signals and outputting it to the corresponding output buffers 70, 71, 72, 73,..., 7m. For example, the signal generation circuit can output the signal for the crosstalk to influence the signal to be tested for crosstalk, thereby generating crosstalk noise. In addition, the target signals can be set in any combination by the selection circuits 60, 61, 62, 63,..., 6m, so that it is possible to determine which signal on the bus is the most dangerous and to grasp the problem. Can be inspected by creating various states by setting the delay circuits 40, 41, 42, 43,..., 4m and the delay circuits 50, 51, 52, 53,. .

  Since the signal generation circuit 3 outputs a signal having a frequency different from the frequency of the signal output from the logic circuits 20, 21, 22, 23,..., 2m, various states can be created by setting the delay. It becomes possible to produce automatically. In other words, the difference in frequency creates the worst state as the probability of the greatest common divisor.

  Further, the signal generating circuit 3 outputs a signal having a frequency different from the frequency of the signal output from the logic circuits 20, 21, 22, 23,. It is also effective for wiring signals. By setting aggressor and victim for a part of the wiring, supplying a pulse to the aggressor, and judging the result by the receiving circuit, the cross between signals of adjacent long wirings in the semiconductor device 1 Talk can be confirmed.

  Further, a plurality of signal generation circuits 3 may be provided, and an aggressor may be set for an output signal from each signal generation circuit 3. Moreover, it is good also as one kind etc. in some groups. For example, if there are 16 buses, if 4 buses are connected to one signal generation circuit 3, then there will be 4 buses in total. The frequency of each signal generating circuit 3 may be set to a different frequency. For example, if there is a signal from the DATA0 output to the DATA2 output, and the DATA1 output is the victim and a 100 MHz data signal is output, for the DATA0 output and DATA2 output as an aggressor, set the DATA0 output to 110 MHz and the DATA2 output to 120 MHz. Makes it possible to create even worse conditions.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 3 Signal generation circuit 20, 21, 22, 23, 2m Logic circuit 40, 41, 42, 43, 4m Delay circuit (1st delay circuit)
50, 51, 52, 53, 5m delay circuit (second delay circuit)
60, 61, 62, 63, 6m Multiplexer (selection circuit)
70, 71, 72, 73, 7m Output buffer

JP 2007-27328 A

Claims (2)

In a semiconductor device comprising: a logic circuit that performs a predetermined logic operation; and a plurality of output buffers for outputting a plurality of signals output from the logic circuit to the outside, respectively.
A signal generation circuit for generating a noise immunity test signal of a predetermined frequency;
A first delay circuit for adjusting a delay time for each signal output from the logic circuit;
A second delay circuit for adjusting a delay time of the signal output from the signal generation circuit;
Provided corresponding to each of the plurality of output buffers, and select either the signal output from the first delay circuit or the signal output from the second delay circuit and output to the corresponding output buffer A selection circuit to
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the signal generation circuit can output a signal having a frequency different from a frequency of a signal output from the logic circuit.

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