JP2007027328A - Semiconductor integrated device and noise testing method using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated device having a built-in testing circuit, capable of simultaneous switching noise testing, and to provide a noise testing method that uses it. <P>SOLUTION: The semiconductor integrated device comprises a system circuit 11 for performing a predetermined logical operation processing; a test circuit 12 having two or more signal generation circuits 14 which generate either one signal of a low level continuous wave (a), a high level continuous wave (b), a normal operation pulse wave (c), and an inverting operation pulse wave (d) according to a waveform control signal WAV; and a switching means 13 for switching normal mode where the output signal of the system circuit 11 is supplied to external circuits, according to a mode control signal MOD, with a test mode in which the output signal of the test circuit 12 is supplied to external circuits. The signal of a pulse wave is supplied to the output terminal for simultaneous switching, while continuous waves or a pulse wave is supplied to the output terminal for observing simultaneous switching noise. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated device and a noise test method using the same, and more particularly to a semiconductor integrated device optimal for evaluating simultaneous switching noise and a noise test method using the same.

  In recent years, semiconductor integrated devices have become larger in scale due to miniaturization of semiconductor processes, the number of input / output pins has increased, and the power supply voltage has also decreased.

  For this reason, when a plurality of outputs of the semiconductor integrated device are changed at the same time, inductive noise, that is, so-called simultaneous switching noise, that cannot be ignored in other non-operational outputs may occur.

  Power fluctuation due to simultaneous switching noise is caused by a large transient current flowing instantaneously to the power / ground wiring due to switching of the input / output buffer.

For example, in a CMOS circuit, a large transient current flows through a power supply / ground wiring mainly when a plurality of output buffers are simultaneously switched. Therefore, a logic malfunction and instability of operation are caused by fluctuations in the power supply voltage.
Potential fluctuations due to simultaneous switching cause timing shifts and malfunctions in inter-chip signal transmission.

  Therefore, when simultaneous switching noise cannot be ignored when connecting a semiconductor integrated device to a substrate on which a wiring pattern is formed and connecting it to an external circuit, countermeasure parts such as a damping resistor must be retrofitted or the substrate prototype must be repeated. There is a problem of not becoming.

  A method of analyzing this simultaneous switching noise by simulation and taking noise countermeasures from the initial design stage is known (for example, see Patent Document 1).

  The simulation method disclosed in Patent Document 1 is based on a simple model that expresses a large number of elements such as resistance, capacitance, inductance, and internal and external load capacitances of a package and LSI in a lumped constant. A model that takes layout information into account is generated and simulated.

  However, there is a problem that it is difficult to predict simultaneous switching noise with sufficient accuracy because the accuracy of the model is limited in analysis by simulation.

  There is also known a semiconductor device in which a test chip on which a test circuit for generating a simultaneous output switching event is formed is mounted on a substrate by a ball grid array (BGA) (see, for example, Patent Document 2).

  The test circuit disclosed in Patent Document 2 includes four registers that realize a test function. These registers generate toggle signals and output the signals to the logic circuit via the I / O pins.

However, the semiconductor device disclosed in Patent Document 2 does not disclose any simultaneous switching noise when the semiconductor device is mounted on a circuit board and connected to an external circuit.
JP 2004-54522 A (page 5, FIG. 1) Japanese Patent Laid-Open No. 11-6867 (5 pages, FIG. 2)

  An object of the present invention is to provide a semiconductor integrated device having a built-in test circuit capable of simultaneous switching noise test and a noise test method using the same.

  In order to achieve the above object, in a semiconductor integrated device of one embodiment of the present invention, a system circuit that performs predetermined logical operation processing and a plurality of signal generation circuits that generate a continuous wave or pulse wave signal according to a waveform control signal A switching circuit for switching between a normal mode for supplying an output signal of the system circuit to an external circuit and a test mode for supplying the output signal of the test circuit to the external circuit in accordance with a mode control signal. It is characterized by comprising.

  In a noise test method of one embodiment of the present invention, a system circuit that performs predetermined logic operation processing, a test circuit that has a plurality of signal generation circuits that generate a continuous wave or pulse wave signal according to a waveform control signal, and mode control A semiconductor integrated device comprising switching means for switching between a normal mode for supplying an output signal of the system circuit to an external circuit and a test mode for supplying an output signal of the test circuit to the external circuit according to a signal A first step of connecting to an external circuit via a wiring; a second step of switching to the test mode in accordance with the mode control signal; and the test to a wiring arbitrarily selected from the wiring in accordance with the waveform control signal A first output signal of the circuit is supplied, and a second output different from the first output signal is supplied to other wirings except the selected wiring. It is characterized with the third step of supplying a fourth step of determining the induced noise to the selected wiring, to be provided with a an issue.

  According to the present invention, a semiconductor integrated device having an embedded test circuit capable of simultaneous switching noise test and a noise test method using the same are obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated device according to Embodiment 1 of the present invention.
As shown in FIG. 1, a semiconductor integrated device 10 includes a system circuit 11 that performs a predetermined logical operation, a test circuit 12 that generates a continuous wave or pulse wave signal according to a waveform control signal WAV supplied from the outside, Switching between a normal mode in which the output signal of the system circuit 11 is supplied to an external circuit (not shown) and a test mode in which the output signal of the test circuit 12 is supplied to the external circuit in accordance with a mode control signal MOD supplied from the outside. And switching means 13 for performing.

  The system circuit 11 includes, for example, a memory cell (not shown) and a signal generation unit (not shown) that generates an address signal, a data write signal, a control signal, a clock signal, and the like necessary for writing or reading data in the memory cell. And a logical operation unit (not shown) for performing predetermined logical operation processing.

  In the normal mode, the system circuit 11 performs predetermined logical operation processing while writing write data to a designated address of a memory cell or reading read data from a designated address in accordance with a control signal.

  The test circuit 12 has the same number of signal generation circuits 14 as the signal output terminals of the system circuit 11 and a first register 15 that stores data indicating that the signal generated by the signal generation circuit 14 is a continuous wave or a pulse wave. And a second register 16 for storing data indicating low level or high level when the signal is a continuous wave and indicating normal rotation pulse or inversion pulse when the signal is a pulse wave. .

  The first and second registers 15 and 16 are, for example, 7-bit shift registers, and are connected in series and operate as 14-bit shift registers.

  The waveform control signal WAV indicates that the first clock signal CLK1 serving as a carrier, data 1a to 7a indicating that the signal is a continuous wave or a pulse wave, and a low level or a high level when the signal is a continuous wave. And an enable signal for permitting writing of the data signal DATA to the first and second registers 15 and 16 and indicating the data signal DATA having data 1b to 7b indicating that it is a normal pulse or an inverted pulse in the case of a pulse wave ENA and a second clock signal CLK2 for transferring the data signal DATA are included.

  When the enable signal ENA is “H”, the data 1a to 7a are stored in the first register 15 and the data 1b to 7b are stored in the second register 16 in synchronization with the second clock signal CLK2.

  The first clock signal CLK1 of the waveform control signal WAV is supplied to the test circuit 12 via the input terminal 22, the data signal DATA is supplied to the input terminal 23, the enable signal ENA is supplied to the input terminal 24, and the second clock signal CLK2 is supplied to the test circuit 12 via the input terminal 25. ing.

  The signal generation circuit 14 includes an AND circuit 17 that calculates a logical product of the first clock signal CLK1 and data stored in the first register 15, an inverter 18 that inverts the output of the AND circuit 17, and an output of the AND circuit 17. Alternatively, a selector 19 that selects a signal output from the inverter 18 is provided.

  The selector 19 is a multiplexer composed of, for example, CMOS transistors, and is switched at the same time according to the data 1b to 7b stored in the second register 16.

  Further, the test circuit 12 includes a buffer 20 for supplying the first clock signal CLK1 to the plurality of AND circuits 17.

  The switching means 13 has the same number of selectors 21 as the signal generation circuit 14, and the selector 21 is a multiplexer composed of, for example, CMOS transistors.

  The mode control signal MOD indicates, for example, a normal mode when “L” and a test mode when “H”, and the selectors 21 of the switching means 13 are simultaneously switched according to the mode control signal MOD.

  The mode control signal MOD is supplied to the switching means 13 via the input terminal 26, and the output signal selected by the selector 21 is output to an external circuit (not shown) via the output terminal 27.

  FIG. 2 is a timing chart showing the relationship between the data stored in the first and second registers 15 and 16 and the waveform of the output signal of the signal generation circuit 14.

As shown in FIG. 2, when the data 1a and 1b of the first and second registers 15 and 16 are (0, 0), the output of the logic circuit 17 becomes “L”, and the selector 19 outputs the output of the logic circuit 17. Since “L” is selected, the output signal becomes a low level continuous wave a.
When the data 1a and 1b are (0, 1), the output of the inverter 18 is selected, so that the waveform of the output signal becomes a high level continuous wave b.

When the data 1a and 1b of the first and second registers 15 and 16 are (1, 0), the output of the logic circuit 17 becomes the first clock signal CLK1, and the selector 19 selects the output of the logic circuit 17; The output signal is a forward pulse wave c.
When the data 1a and 1b of the first and second registers 15 and 16 are (1, 1), the output of the inverter 18 is selected, so that the output signal is an inverted pulse wave d.

  That is, the data stored in the first register 15 determines whether the output signal is a continuous wave or a pulse wave. When the output signal is a continuous wave according to the data stored in the second register 16, the low level or the high level is determined. In the case of a pulse wave, it is determined whether it is a normal rotation pulse or a reverse rotation pulse.

  Thereby, the output signal of the test circuit 12 is selected according to the mode control signal MOD, and one of the low level continuous wave a, the high level continuous wave b, the normal pulse wave c, and the inverted pulse wave d is selected according to the waveform control signal WAV. The signal can be output to an external circuit.

  Next, the noise test method will be described with reference to FIGS. FIG. 3 is a flowchart showing the noise test method, and FIG. 4 is a diagram showing the configuration of the noise test system.

  As shown in FIG. 3, first, the semiconductor integrated device 10 is connected to an external circuit via wiring (step S01).

  That is, as shown in FIG. 4, the integrated circuit 10 and the semiconductor integrated device 49 to which the output of the integrated circuit 10 is input are arranged on the substrate 48 on which the wirings 41 to 47 are formed, and are connected via the wirings 41 to 47. To do.

Next, the test mode is selected by the mode control signal MOD (step S02).
That is, as shown in FIG. 4, the control signal generator 50 is connected to the input terminal 26 of the semiconductor integrated circuit 10 via the wiring 51, and the selector 21 of the switching means 13 is driven.

  Next, an output terminal for simultaneous switching and a terminal for observing simultaneous switching noise are set (step S03).

  Here, as shown in FIG. 4, the output terminal 27 of the semiconductor integrated device 10 connected to the wiring 45 is used as an observation terminal, and the output terminal 27 of the semiconductor integrated device 10 connected to the other wirings 41 to 44, 46, 47 is used. Are output terminals for simultaneous switching.

  Next, the waveform of the signal output to the output terminal that performs simultaneous switching and the terminal that observes simultaneous switching noise is set (step S04).

  Here, a signal of a forward rotation pulse wave is output to the output terminal 27 that performs simultaneous switching connected to the wirings 41 to 44, 46, and 47, and Low to the terminal 27 that observes simultaneous switching noise connected to the wiring 45. A level continuous wave signal is output.

  That is, as shown in FIG. 4, a 14-bit data signal “11110110000000” and an enable signal ENA are sent from the control signal generator 50 to the input terminals 23, 24, and 25 of the semiconductor integrated device 10 through the wiring 52. The second clock CLK2 is output.

  As a result, “1111011” is stored in the first register 15 as data 1a to 7a, and “0000000” is stored in the second register 16 as data 1b to 7b.

  Next, the first clock signal CLK1 is input and the output signal of the test circuit 12 is output to the output terminal 27 (step S05).

  That is, as shown in FIG. 4, when a first clock signal CLK1, for example, a clock signal equal to the clock signal of the system circuit 11, is input to the buffer 20 of the test circuit 12 via the input terminal 22, it is stored in the first register 15. In accordance with the data 1 a to 7 a and the data 1 b to 7 b stored in the second register 16, a low level continuous wave a signal is output to the output terminal 27 connected to the wiring 45, and the wirings 41 to 44, 46, 47 are output. A signal of the forward rotation pulse wave c is output to the connected output terminal 27.

  Next, the noise induced in the terminal for observing the simultaneous switching noise is observed (step S06).

  That is, as shown in FIG. 4, the probe 53 is brought into contact with the wiring 45 connected to the terminal for observing simultaneous switching noise, and the noise is observed with a waveform observer 54, for example, an oscilloscope.

  The contact position of the probe 53 can be freely set between the output terminal 27 of the semiconductor integrated device connected to the wiring 45 and the input terminal of the semiconductor integrated device 49.

FIG. 5 is a timing chart showing simultaneous switching noise according to this embodiment.
As shown in FIG. 5, a low level continuous wave a is propagated to the wiring 45 and a forward pulse wave c signal propagates to the wirings 41 to 44, 46, and 47, but a forward pulse wave c signal propagates to the wiring 45. It is possible to observe a simultaneous switching noise e called ground bounce in which the Low level induced in response to the rise and fall of.

  When the simultaneous switching noise e is observed, the change in the arrangement of the semiconductor integrated devices 10 and 49 and the modification of the wiring patterns of the wirings 41 to 47 are studied, and the simultaneous switching noise e is determined at the initial stage of the substrate 48 design. It is possible to reduce the influence.

  As described above, according to the present embodiment, simultaneous switching is performed at the actual operation speed by the signal of the forward rotation pulse wave c, and the fluctuation of the ground potential is caused by the simultaneous switching noise e superimposed on the signal of the low level continuous wave a. It can be observed.

  As a result, the semiconductor integrated device 10 having the built-in test circuit 12 capable of the simultaneous switching noise test assuming an actual use environment is obtained, and the substrate on which the semiconductor integrated device 10 is mounted can be reduced by noise countermeasures and optimization of countermeasure components. This shortens the trial period and reduces unnecessary parts.

  As a result, a highly reliable electronic device using the semiconductor integrated device 10 can be obtained. Therefore, it is possible to stably operate an electronic device that requires continuous operation for which a malfunction is not allowed even for a moment over a long period of time.

  Here, the case where the simultaneous switching noise e indicating the fluctuation of the ground potential is observed using the signals of the low level continuous wave a and the normal pulse wave c has been described. However, as shown in FIG. You may make it observe the simultaneous switching noise f which shows the fluctuation | variation of a power supply potential using the signal of the inversion pulse wave d.

  In this case, “0000100” is stored as data 1a to 7a in the first register 15, and “1111111” is stored as data 1b to 7b in the second register 16.

  Moreover, although the case where the normal rotation and the inversion pulse waves c and d are rectangular waves equal to the clock signal of the system circuit 11 has been described, the intermittent waveform is not particularly limited.

  For example, by using a waveform such as a trapezoidal wave, a triangular wave, or a sine wave that is close to the actual use environment, there is an advantage that the accuracy of trial production of the board such as termination circuit design and countermeasure component mounting can be improved.

  Furthermore, although the case where the frequency of the clock signal of the first clock signal CLK1 and the clock signal of the system circuit 11 is the same has been described, it may be different.

  For example, when the observability of the simultaneous switching noises e and f decreases as the clock signal of the system circuit 11 becomes higher in frequency, the observability of the simultaneous switching noise is reduced by reducing the frequency of the first clock signal CLK1. There is an advantage that can be improved.

  FIG. 7 is a timing chart showing simultaneous switching noise by the noise test method according to the second embodiment.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This embodiment is different from the first embodiment in that a pulse wave signal opposite to a terminal that performs simultaneous switching is output to a terminal that observes simultaneous switching noise.

  That is, as shown in FIG. 7, the signal of the forward rotation pulse wave c is output to the terminal 27 for simultaneous switching connected to the wirings 41 to 44, 46 and 47, and the simultaneous switching noise connected to the wiring 45 is generated. A signal of the inverted pulse wave d is output to the terminal 27 to be observed.

  In this case, “1111111” is stored as data 1a to 7a in the first register 15, and “0000100” is stored as data 1b to 7b in the second register 16.

Simultaneous switching noise g superimposed on the rising and falling edges of the inverted pulse wave d signal is induced in the wiring 45.
As a result, when the level of the simultaneous switching noise g is in the vicinity of the threshold value of the internal circuit of the semiconductor integrated device 49, for example, at a half level of the power supply voltage in the CMOS circuit, the rising and falling time of the signal of the inverted pulse wave d is reached. It will affect and cause malfunction.

  Thereby, it is possible to observe the influence of the simultaneous switching noise g on the rise time and fall time of the output signal of the system circuit 11.

  As described above, in this embodiment, since a pulse wave signal opposite to the output terminal that performs simultaneous switching is output to the terminal that observes simultaneous switching noise, the simultaneous switching noise causes the rise of the output signal of the system circuit 11. There is an advantage that the influence on the fall time can be observed.

  Here, the case where the signal of the forward pulse wave c is output to the output terminal that performs the simultaneous switching and the signal of the inverted pulse wave d is output to the terminal that observes the simultaneous switching noise has been described. The signal of the inverted pulse wave c may be output to the terminal, and the signal of the forward pulse wave c may be output to the terminal for observing the simultaneous switching noise.

  FIG. 8 is a timing chart showing switching noise by the noise test method according to the third embodiment.

  In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  This embodiment is different from the first embodiment in that the number of output terminals for simultaneous switching is arbitrarily set.

  That is, as shown in FIG. 8, the signal of the forward rotation pulse wave c is output only to the output terminal 27 connected to the wiring 41 and performing simultaneous switching, and the simultaneous switching connected to the wirings 42 to 44, 46 and 47 is performed. A low level continuous wave a signal is output to the output terminal 27 that is not performed and the terminal 27 that observes simultaneous switching noise connected to the wiring 45.

  In this case, “1000000” is stored in the first register 15 as data 1a to 7a, and “0000000” is stored in the second register 16 as data 1b to 7b.

  In the wiring 45, the simultaneous switching noise h induced in response to the rising and falling of the signal of the normal pulse wave c is observed. However, the simultaneous switching noise observed in the wirings 42 to 44, 46, 47 is not shown.

  Here, if the number of output terminals 27 that perform simultaneous switching is increased or decreased stepwise between 0 and 6, the level of the simultaneous switching noise h also increases or decreases according to the number of output terminals 27 that perform simultaneous switching. It is possible to observe the degree of influence of the switching output terminal 27 on the simultaneous switching noise h step by step.

  As described above, in this embodiment, the number of the output terminals 27 that perform simultaneous switching is arbitrarily set, and the influence of the output terminal 27 that performs simultaneous switching on the simultaneous switching noise h can be observed in stages. .

  Here, a case has been described where a low level continuous wave a is output to a terminal for observing simultaneous switching and a normal pulse wave c is output to an output terminal 27 for performing simultaneous switching. However, a high level is output to a terminal 27 for observing simultaneous switching. You may output the signal of the inversion pulse wave c to the output terminal 27 which performs continuous wave b and simultaneous switching.

  Further, another terminal adjacent to the output terminal 27 connected to the wirings 41 to 47 may be used as a terminal for observing simultaneous switching noise. In this case, the amount of sneak in simultaneous switching noise can be observed.

  In the above-described embodiment, the case where the output terminal 27 connected to the wiring 45 is a terminal for observing simultaneous switching noise has been described. However, the present invention is not limited to this, and any of the terminals connected to the wirings 41 to 47 is used. The output terminal 27 may be used.

1 is a block diagram showing a semiconductor integrated device according to Embodiment 1 of the present invention. 3 is a timing chart showing the relationship between the waveform control signal and the output waveform of the signal generation circuit according to the first embodiment of the present invention. The flowchart which shows the noise test method which concerns on Example 1 of this invention. 1 is a timing chart showing a configuration of a noise test system according to Example 1 of the present invention. 3 is a timing chart showing simultaneous switching noise according to the first embodiment of the present invention. The timing chart which shows the other simultaneous switching noise which concerns on Example 1 of this invention. The timing chart which shows the simultaneous switching noise which concerns on Example 2 of this invention. The timing chart which shows the simultaneous switching noise which concerns on Example 3 of this invention.

Explanation of symbols

10, 49 Semiconductor integrated device 11 System circuit 12 Test circuit 13 Switching means 14 Signal generating circuit 15 First register 16 Second register 17 AND circuit 18 Inverter 19, 21 Selector 20 Buffer 22, 23, 24, 25, 26 Input terminal 27 Output terminals 41 to 47, 51, 52 Wiring 48 Substrate 50 Control signal generator 53 Probe 54 Waveform observer MOD Mode control signal WAV Waveform control signal CLK1, CLK2 Clock signal DATA Data signal ENA Enable signal 1a-7a, 1b-7b Data a Low level continuous wave b High level continuous wave c Forward pulse wave d Reverse pulse wave e, f, g, h Simultaneous switching noise

Claims (5)

A system circuit for performing predetermined logical operation processing;
A test circuit having a plurality of signal generation circuits for generating a continuous wave or pulse wave signal in accordance with the waveform control signal;
Switching means for switching between a normal mode for supplying the output signal of the system circuit to an external circuit and a test mode for supplying the output signal of the test circuit to the external circuit according to a mode control signal;
A semiconductor integrated device comprising: The signal generation circuit is
A first register for storing data indicating that the signal is a continuous wave or a pulse wave;
A second register for storing data indicating a low level continuous wave or a high level continuous wave when the signal is a continuous wave, and storing data indicating a normal pulse or an inverted pulse when the signal is a pulse wave;
An AND circuit for obtaining a logical product of a clock signal and data stored in the first register;
A selector that selects an output signal of the AND circuit or a signal obtained by inverting the output of the AND circuit;
The semiconductor integrated device according to claim 1, comprising: A system circuit for performing a predetermined logical operation process, a test circuit having a plurality of signal generation circuits for generating a continuous wave or pulse wave signal according to a waveform control signal, and an output signal of the system circuit according to a mode control signal A semiconductor integrated device comprising a switching means for switching between a normal mode supplied to a circuit and a test mode for supplying an output signal of the test circuit to the external circuit is connected to the external circuit via a wiring. And the process of
A second step of switching to the test mode according to the mode control signal;
In accordance with the waveform control signal, a first output signal of the test circuit is supplied to a wiring arbitrarily selected from the wiring, and a second different from the first output signal is supplied to other wirings except the selected wiring. A third step of supplying an output signal of
A fourth step of determining noise induced in the selected wiring;
A noise test method comprising:   The noise test method according to claim 3, wherein, in the third step, the first output signal is the continuous wave, and the second output signal is the pulse wave.   4. The method according to claim 3, wherein, in the third step, the first output signal is the pulse wave, and the second output signal is a signal obtained by inverting the first output signal. 5. Noise test method.

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