JP2011002377A - Semiconductor device and testing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To test a semiconductor device in a testing environment using a low-speed test device having few terminals.SOLUTION: The semiconductor device includes an input terminal (122); a termination circuit (121) for specifying the input impedance of the input terminal; and a resistor (113) for fetching the output signal from an input circuit in synchronization with a clock signal. The semiconductor device includes a pattern generation section (109); and a pattern check section (107) for comparing an output signal from the resistor with the expected value. The termination circuit includes a first resistance element (132); a first transistor (131); a second resistive element (133); and a second transistor (134). Use of a low-speed test device having a small number of terminals is made possible, by controlling the first and second transistors according to a pattern signal generated by the pattern generating section, and by providing a self-diagnosis control circuit (115) for transmitting the pattern signal to the input circuit.

Description

  The present invention relates to a semiconductor device and a test method for the semiconductor device, and further relates to a diagnostic technique for an input circuit included in the semiconductor device.

  As a test technique for a semiconductor device, a test method using BIST (Built In Self Test) is known as described in Patent Document 1. According to this test method, the reliability of the operation test in the wafer state can be improved by utilizing BOST (Built Out Self Test) and BIST.

  Patent Document 2 describes a technique (loopback test) in which an output terminal and an input terminal of an LSI, which is a device under test, are connected externally and an operation test of an I / O interface is performed at an actual operation speed.

  Usually, a high-speed tester corresponding to an SRAM capable of high-speed operation is used for a test of an SRAM (Static Random Access Memory) capable of high-speed operation. For example, a test frequency corresponding to 1.0 Gbps is used for an AC test of a high-speed memory that performs a high-speed operation such as 1.0 Gbps by performing a DDR (Double-Data-Rate) operation using a clock signal such as 500 MHz. A high-speed tester with high speed is required, and enormous costs and time are required for its development. Therefore, such a high-speed tester must be expensive.

JP 2003-016799 A JP 2003-028928 A

  As described above, a high-speed tester corresponding to an SRAM capable of high-speed operation is used for a test of an SRAM (Static Random Access Memory) capable of high-speed operation. In an environment using a high-performance high-speed tester, the cost of the tester itself is high, and there is a limit to reducing test costs.

  In the technique such as the loopback test, the same number of output terminals and input terminals are indispensable in order to test all the input circuits. However, if the number of input terminals is larger than the number of output terminals due to the presence of address input terminals and command input terminals as in semiconductor memory, the number of output terminals and the number of input terminals are different. The input circuit cannot be tested by a loopback test.

  In particular, in a shipping test of a semiconductor device, it is desirable to reduce the test cost by performing a test in an inexpensive test environment using a low-speed test apparatus (tester) with a small number of terminals. In order to guarantee the quality of the semiconductor device, it is necessary to reliably test the performance of the semiconductor device, for example, the external AC specifications, even in an inexpensive test system.

  An object of the present invention is to provide a technique for testing the performance of a semiconductor device in an inexpensive test environment using a low-speed test apparatus with a small number of terminals.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the semiconductor device includes an input terminal for capturing a signal, an input circuit to which the captured signal is transmitted, a termination circuit for defining input impedance at the input terminal, and a clock input terminal for capturing a clock signal. A register that captures an output signal of the input circuit in synchronization with the clock signal, a pattern generation unit that generates a pattern signal, and a pattern check unit that compares the output signal of the register with an expected value. The termination circuit pulls down an input side path of the input circuit, a first resistance element for pulling up an input side path of the input circuit, a first transistor connected in series to the first resistance element, and A second resistance element and a second transistor connected in series to the second resistance element. Then, the pattern signal generated by the pattern generation unit is captured in synchronization with the clock signal, and the first transistor and the second transistor are controlled according to the captured pattern signal, whereby the pattern signal is input to the input circuit. A self-diagnosis control circuit for transmission is provided.

  The self-diagnosis control circuit complementarily controls the states of the first transistor and the second transistor based on the test signal generated by the pattern generation unit. As a result, a signal corresponding to the pattern signal generated by the pattern generation unit 109 is supplied to the input circuit via the input signal transmission path, so that the test signal is input from the test device via the data input terminal of the semiconductor device. There is no need to do. This achieves the object of the present invention to provide a technique for testing the performance of a semiconductor device in an inexpensive test environment using a low-speed test apparatus with a small number of terminals.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a technique for testing the performance of a semiconductor device in an inexpensive test environment using a low-speed test apparatus with a small number of terminals.

1 is a circuit diagram illustrating a configuration example of a main part of a semiconductor memory as an example of a semiconductor device according to the present invention. It is explanatory drawing of the test state of the semiconductor memory shown by FIG. It is explanatory drawing about the comparison object of the test state shown by FIG. The operation timing of the main part in the test state of the semiconductor memory shown in FIG. FIG. 6 is a circuit diagram showing another configuration example of a main part in a semiconductor memory as an example of a semiconductor device according to the present invention. FIG. 6 is an explanatory diagram of a test state of the semiconductor memory shown in FIG. 5. FIG. 6 is a circuit diagram showing another configuration example of a main part in a semiconductor memory as an example of a semiconductor device according to the present invention. FIG. 8 is an explanatory diagram of a test state of the semiconductor memory shown in FIG. 7. FIG. 6 is a circuit diagram showing another configuration example of a main part in a semiconductor memory as an example of a semiconductor device according to the present invention. It is explanatory drawing of the test state of the semiconductor memory shown by FIG. FIG. 6 is a circuit diagram showing another configuration example of a main part in a semiconductor memory as an example of a semiconductor device according to the present invention. FIG. 12 is an operation timing chart of a main part in the semiconductor memory shown in FIG. 11. It is another example block diagram of a semiconductor memory as an example of the semiconductor device according to the present invention. FIG. 14 is a circuit diagram illustrating a configuration example of a main part in the semiconductor memory illustrated in FIG. 13. It is an operation | movement timing diagram of the principal part in FIG. FIG. 6 is a circuit diagram showing another configuration example of a main part in a semiconductor memory as an example of a semiconductor device according to the present invention. FIG. 17 is a layout explanatory diagram of a semiconductor chip when the configuration shown in FIG. 16 is adopted. FIG. 17 is an operation explanatory diagram of a main part in the semiconductor memory shown in FIG. 16.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A semiconductor device according to a typical embodiment of the present invention includes an input terminal (122) for capturing a signal, an input circuit (114) for transmitting the captured signal, and the input terminal. A termination circuit (121) for defining an input impedance, a clock input terminal (102) for capturing a clock signal, and a register (113) for capturing an output signal of the input circuit in synchronization with the clock signal are provided. It is done. A pattern generation unit (109) that generates a pattern signal for self-diagnosis and a pattern check unit (107) that compares the output signal of the register with an expected value are provided. The termination circuit includes a first resistance element (132) for pulling up an input side path of the input circuit, a first transistor (131) connected in series to the first resistance element, and an input of the input circuit. A second resistance element (133) for pulling down the side path and a second transistor (134) connected in series to the second resistance element are included. Then, the pattern signal generated by the pattern generation unit is captured in synchronization with the clock signal, and the first transistor and the second transistor are controlled according to the captured pattern signal, whereby the pattern signal is input to the input circuit. A self-diagnosis control circuit (115) is provided for transmission.

  [2] In the above [1], a multiplier circuit (501) for multiplying a clock signal taken in via the clock input terminal can be provided. The register (113) takes in the output signal of the input circuit in synchronization with the clock signal multiplied by the multiplier circuit, and the self-diagnosis control circuit (115) generates the pattern signal generated by the pattern generator. Can be captured in synchronism with the clock signal multiplied by the multiplier circuit.

  [3] In another semiconductor device according to a typical embodiment of the present invention, an input terminal (122) for taking in a signal and an input circuit (in which the signal taken in through the input terminal is transmitted) 114), a termination circuit (121) for defining the input impedance at the input terminal, and a first clock input terminal (102-1) for capturing the first clock signal. Also, a second clock input terminal (102-2) for capturing a second clock signal different from the first clock signal, and a register (113) for capturing the output signal of the input circuit in synchronization with the first clock signal. ), A pattern generation unit (109) that generates a pattern signal for self-diagnosis, and a pattern check unit (107) that compares the output signal of the register with an expected value. The termination circuit includes a first resistance element (132) for pulling up an input side path of the input circuit, a first transistor (131) connected in series to the first resistance element, and an input of the input circuit. A second resistance element (133) for pulling down the side path and a second transistor (134) connected in series to the second resistance element are configured. The pattern signal generated by the pattern generation unit is captured in synchronization with the second clock signal, and the pattern signal is input by controlling the first transistor and the second transistor according to the captured pattern signal. A self-diagnosis control circuit (115) is provided for transmission to the circuit.

  [4] In the above [3], the first multiplication circuit (501-1) for multiplying the first clock signal taken in through the first clock input terminal and the second clock input terminal. And a second multiplication circuit (501-2) for multiplying the second clock signal. At this time, the register takes in the output signal of the input circuit in synchronization with the first clock signal multiplied by the first multiplication circuit, and the self-diagnosis control circuit uses the pattern generated by the pattern generation unit. The signal can be configured to be captured in synchronization with the second clock signal multiplied by the second multiplication circuit.

  [5] Another semiconductor device according to a typical embodiment of the present invention includes an input terminal (122) for capturing a signal, an input circuit (114) for transmitting the captured signal, and the input A termination circuit (121) for defining the input impedance at the terminal is provided. Further, the semiconductor device includes a clock input terminal (102) for capturing a first clock signal, a pattern generation unit (109) for generating a pattern signal, and a pattern check unit (for comparing the output signal of the register with an expected value). 107). The termination circuit includes a first resistance element (132) for pulling up an input side path of the input circuit, a first transistor (131) connected in series to the first resistance element, and an input of the input circuit. A second resistance element (133) for pulling down the side path and a second transistor (134) connected in series to the second resistance element are configured. The semiconductor device further includes a multiplier circuit (501) for multiplying the first clock signal taken in via the clock input terminal and a phase of the first clock signal multiplied by the multiplier circuit to adjust the phase of the first clock signal. And a phase adjustment circuit (1101) for forming a two-clock signal. The semiconductor device captures the pattern signal generated by the pattern generation unit in synchronization with the second clock signal, and controls the first transistor and the second transistor according to the captured pattern signal, A self-diagnosis control circuit (115) for transmitting the pattern signal to the input circuit is provided. The semiconductor device includes a register that captures the output signal of the input circuit in synchronization with the first clock signal multiplied by the multiplication circuit, and a pattern check unit that compares the output signal of the register with an expected value. And are provided.

  [6] In another semiconductor device according to a typical embodiment of the present invention, a memory mat (1303) capable of storing data and an address signal for writing data into or reading data from the memory mat are fetched. One circuit (1301, 1304) is provided. The semiconductor device has a second circuit (1306) for fetching a command signal for instructing an operation related to data writing or reading to the memory mat, and a third circuit for fetching data for writing to the memory match. A circuit (1306).

  The first circuit, the second circuit, and the third circuit each include an input circuit module (111). The input circuit module includes an input circuit (114) to which an input signal is transmitted, a termination circuit (121) for defining an input impedance of an input side path of the input circuit, and an output signal of the input circuit as a clock. A first register (113-2) that captures in synchronization with the rising edge of the signal and a second register (113-1) that captures the output signal of the input circuit in synchronization with the falling edge of the clock signal are provided. Become. The termination circuit includes a first resistance element (132) for pulling up an input side path of the input circuit, a first transistor (131) connected in series to the first resistance element, and an input of the input circuit. A second resistance element (133) for pulling down the side path and a second transistor (134) connected in series to the second resistance element are provided. Further, a self-diagnosis control circuit (115) for supplying the pattern signal to the input circuit by controlling the first transistor and the second transistor in accordance with a self-diagnosis pattern signal is provided. Further, the self-diagnosis control circuit includes a third register (117-2) for capturing the pattern signal in synchronization with the rising edge of the clock signal, and the pattern signal in synchronization with the falling edge of the clock signal. A fourth register (117-1) to be fetched is provided. The self-diagnosis control circuit selects the output signal of the third register in synchronization with the rising edge of the clock signal, and synchronizes the output signal of the fourth register with the falling edge of the clock signal. A selection circuit (1401) for selection is provided. The first transistor and the second transistor are controlled based on the selection output of the selection circuit.

  [7] In the above [1], the first transistor (131) according to the first mode in which the signal taken in through the data input terminal (122) is transmitted to the input circuit (114) and the pattern signal In addition, control logic (116) for switching to the second mode in which the pattern signal is transmitted to the input circuit by controlling the second transistor (134) can be provided. The control logic fixes both the first transistor and the second transistor in the on state in the first mode.

  [8] Another semiconductor device according to a typical embodiment of the present invention includes a signal input terminal (122) for capturing a signal, an input circuit (114) for transmitting the captured signal, and the above Termination circuit (121) for defining the input impedance at the input terminal, clock input terminal (102) for capturing the clock signal, and register (113) for capturing the output signal of the input circuit in synchronization with the clock signal And are provided. The semiconductor device is provided with a pattern generation unit (109) that generates a pattern signal for self-diagnosis and a pattern check unit (107) that compares the output signal of the register with an expected value.

  The termination circuit includes a plurality of first resistance elements (132-1 to 132-n) for pulling up an input side path of the input circuit, and a plurality of first transistors connected in series to the first resistance elements ( 131-1 to 131-n), a plurality of second resistance elements (133-1 to 133-n) for pulling down the input side path of the input circuit, and a plurality of series connected to the second resistance elements, respectively. Second transistors (134-1 to 134-n). The semiconductor device captures the pattern signal generated by the pattern generation unit in synchronization with the clock signal, and controls the first transistor and the second transistor in accordance with the captured pattern signal, whereby the pattern signal is generated. A self-diagnosis control circuit (115) is provided for transmitting a signal to the input circuit. The semiconductor device further includes an external terminal (162) to which an adjustment resistor element (161) is externally attached, and the self-diagnosis control circuit according to a resistance value of the adjustment resistor element connected to the external terminal. And a controller (163) for selecting a transistor to be controlled from the plurality of first transistors and the plurality of second transistors.

  [9] When testing the semiconductor device according to [1] above, the test device is coupled to the semiconductor device. A multiplication circuit for multiplying the clock signal output from the test apparatus is externally attached to the clock input terminal of the semiconductor device, and the pattern signal is generated from the test apparatus to the pattern generation unit of the semiconductor device. Instruct. Further, the clock signal multiplied by the multiplication circuit is transmitted to the clock input terminal in the semiconductor device, and the comparison result in the pattern check unit in the semiconductor device is taken into the test device.

2. Details of Embodiments Embodiments will be further described in detail.

<Embodiment 1>
FIG. 1 shows a configuration example of a main part in a semiconductor memory which is an example of a semiconductor device according to the present invention.

  The semiconductor memory 100 shown in FIG. 1 is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The semiconductor memory 100 includes an output buffer 106, a pattern check unit 107, input buffers 112, 108, and 110, a pattern generation unit 109, and an input circuit module 111, although not particularly limited. In addition, a large number of terminals are provided on the edge of the semiconductor memory 100. In FIG. 1, a test output terminal 101, a clock input terminal 102, a first test input terminal 103, a second test input terminal 104, and a data input terminal 122 are representatively related to self-diagnosis among the above-mentioned many terminals. Indicated.

  Although not shown in FIG. 1, a memory cell array in which a plurality of memory cells are arranged and its peripheral circuit are arranged. The peripheral circuit outputs a decoder for decoding an address signal input from the outside, a control circuit for controlling an internal operation in accordance with a command signal input from the outside, and data read from the memory cell array And an output circuit for the purpose.

  The pattern generation unit 109 generates a pattern signal for a test in BIST (built in self-test), which is a self-diagnosis technique on a semiconductor chip. For this pattern generation unit, a general circuit configuration in BIST, for example, an LFSR (linear feedback shift register) capable of generating pseudo-random numbers can be used. A pattern signal generated by the pattern generation unit 109 is set by a pattern setting signal transmitted via the first test input terminal 103 and the input buffer 108.

  The input circuit module 111 includes an input circuit 114 for capturing an input signal transmitted via the data input terminal 122, and data for capturing an output signal of the input circuit 114 in synchronization with the rising edge of the clock signal CLK. An input register 113 is included. The input circuit 114 includes a differential amplifier circuit using CMOS transistors. The signal input from the data input terminal 122 is transmitted to one input terminal of the differential amplifier circuit. A reference voltage for signal capture is input to the other input terminal of the differential amplifier circuit. The clock signal CLK is transmitted to the data input register 113 through the clock input terminal 102 and the input buffer 112. In the input side path of the input circuit 114, that is, the input signal transmission path 124 from the data input terminal to the input terminal of the input circuit 114, the input impedance at the data input terminal 122 is the impedance in the external signal transmission path. A termination circuit 121 is provided for matching. The termination circuit 121 is not particularly limited, but a pull-up resistor element 132 for pulling up the input signal transmission path 124 to the high potential side power supply Vdd, and pulling down the input signal transmission path 124 to the low potential side power supply Vss. Including a pull-down resistor element 133. A p-channel type MOS transistor 131 is provided between the pull-up resistor element 132 and the high-potential side power supply Vdd, and an n-channel type transistor is provided between the pull-down resistor element 133 and the low-potential side power supply VSS. A MOS transistor 134 is provided. With the p-channel MOS transistor 131 turned on, the pull-up function of the pull-up resistor element 132 is exhibited. With the n-channel MOS transistor 134 turned on, the pull-down function of the pull-down resistance element 133 is exhibited. When write data is taken into the semiconductor memory 100 via the data input terminal 122, both the p-channel MOS transistor 131 and the n-channel MOS transistor 134 are turned on, and the pull-up resistor element 132 and the pull-down resistor 132 are pulled down. The impedance is defined by the resistance element 133 for use.

  The input circuit module 111 is arranged corresponding to a plurality of input terminals 122 for taking data for writing to the memory cell array, address signals, and command signals into the semiconductor memory. FIG. 1 representatively shows a module corresponding to one of a plurality of input terminals 122 for fetching data for writing to the memory cell array.

  The input circuit module 111 is provided with a self-diagnosis control circuit 115. The self-diagnosis control circuit 115 uses the termination circuit 121 to transmit a test pattern signal to the input circuit 114. That is, termination circuit control signals φ 1 and φ 2 are formed according to the pattern signal generated by the pattern generation unit 109, thereby controlling the states of the p-channel MOS transistor 131 and the n-channel MOS transistor 134. With this control, a logic level corresponding to the pattern signal can be supplied to the input circuit 114 via the input signal transmission path 124. For example, when the p-channel MOS transistor 131 is turned on and the n-channel MOS transistor 134 is turned off in accordance with the pattern signal, a high level (logic value “1”) signal is sent to the input circuit. 114 can be supplied. Further, when the p-channel MOS transistor 131 is turned off in accordance with the pattern signal and the n-channel MOS transistor 134 is turned on, a low level (logic value “0”) signal is inputted. The circuit 114 can be supplied.

  The self-diagnosis control circuit 115 includes a self-diagnosis register 117, a NAND gate 118, an AND gate 119, and a NAND gate 120, although not particularly limited. The self-diagnosis register 117 captures the output signal (pattern signal) of the pattern generation unit 109 in synchronization with the falling edge of the clock signal CLK. The output signal of the self-diagnosis register 117 is transmitted to one input terminal of the NAND gate 118 at the subsequent stage. The enable signal transmitted through the second test input terminal 104 and the input buffer 110 is transmitted to the other input terminal of the NAND gate 118. With the enable signal asserted to a high level, the output signal of the self-diagnosis register 117 is transmitted to one input terminal of the AND gate 119 and the NAND gate 120 in the subsequent stage. The output signal of the termination circuit control logic 116 is input to the other input terminal of the AND gate 119 and the NAND gate 120.

  The pattern check unit 107 determines whether the input circuit 114 is operating normally by comparing the logic of the output signal of the data input register 113 in the input circuit module 111 with an expected value. The comparison result is externally output via the output buffer 106 and the test output terminal 101. Since a large amount of comparison result data with the expected value cannot be held in the chip, the comparison result in the pattern check unit 107 can be compressed and output. For the compression of the comparison result, a MISR (multiple input signature register) can be used which has good compression efficiency and few errors are missed.

  The termination circuit control logic 116 is connected to the p-channel MOS transistors 131-1 to 131-n according to a non-test mode in which a signal taken in via the data input terminal 122 is transmitted to the input circuit 114 and a pattern signal. The n-channel MOS transistors 134-1 to 134-n are controlled to switch to the test mode in which the pattern signal is transmitted to the input circuit 114. In the non-test mode, the termination enable signal EN is set to the high level by the termination circuit control logic 116. In the test mode, the termination enable signal EN is set to a low level by the termination circuit control logic 116.

In the test mode, the test enable signal CE is set to high level by the test apparatus 201. Also,
When the termination enable signal EN is set to a low level by the termination circuit control logic 116, the p-channel MOS transistor 131 or the n-channel MOS transistor 134 is individually turned on according to the pattern signal generated by the pattern generation unit 109. By being controlled to be in the off state, a signal equivalent to the pattern signal can be supplied to the input circuit 114. In the non-test mode, the termination enable signal is set to the high level by the termination control logic 116, so that the p-channel MOS transistor 131 or the n-channel MOS transistor 134 is turned on simultaneously. In this state, data input through the input terminal 122 can be transmitted to the input circuit 114. In the non-test state, the output signal of the input circuit 114 is transmitted to an internal circuit (not shown) via the data input register 113 and written into the memory cell array.

  FIG. 2 shows a test state of the semiconductor memory 100 shown in FIG.

  When testing the semiconductor memory 100, the test output terminal 101, the clock input terminal 102, the first test input terminal 103, and the second test input terminal 104 of the semiconductor memory 100 are coupled to the test apparatus 201 as shown in FIG. Is done. A plurality of input terminals 122-1 to 122-n (n is a positive integer of 2 or more) such as the data input terminal 122 shown in FIG. 1 are opened or terminated with an external resistance element or the like. And is not connected to the test apparatus 201. A clock signal CLK, a pattern setting signal PCNT, and a test enable signal CE are supplied from the test apparatus 201 to the semiconductor memory 100 via the clock input terminal 102, the first test input terminal 103, and the second test input terminal 104, respectively.

  FIG. 4 shows the operation timing of the main part in the test state of the semiconductor memory 100.

  The output signal of the pattern generation unit 109 is taken into the self-diagnosis register 117 in synchronization with the falling edge of the clock signal CLK. The test apparatus 201 transmits the output signal of the self-diagnosis register 117 to the AND gate 119 and the NAND gate 120 in a state where the test enable signal CE is set to the high level. In a state where the output signal of the termination circuit control logic 116 is set to the low level, the termination circuit control signals φ1 and φ2 are formed according to the pattern signal generated by the pattern generation unit 109, and thereby the p-channel MOS transistor The states of 131 and n-channel MOS transistor 134 are controlled in a complementary manner. As a result, a signal corresponding to the pattern signal generated by the pattern generation unit 109 is supplied to the input circuit 114 via the input signal transmission path 124. The output signal of the input circuit 114 is taken into the data input register 113 in synchronization with the rising edge of the clock signal CLK supplied from the test apparatus 201. The output signal of the data input register 113 is transmitted to the pattern check unit 107 where it is compared with the expected value. In this comparison, if the output signal of the data input register 113 matches the expected value, the operation of the input circuit 114 is “normal”. However, when the output signal of the data input register 113 does not match the expected value, the operation of the input circuit 114 is “abnormal”. This comparison result is transmitted to the test apparatus 201 via the test output terminal 101.

  According to the first embodiment, the following operational effects can be obtained.

  (1) The test signal generated by the pattern generation unit 109 in a state where the test enable signal CE is set to a high level by the test apparatus 201 and the termination enable signal EN is set to a low level by the termination control logic 116 is a register for self-diagnosis. 117, and the output signal is transmitted to the AND gate 119 and the NAND gate 120, whereby the termination circuit control signals φ1 and φ2 corresponding to the pattern signal are formed. The states of the p-channel MOS transistor 131 and the n-channel MOS transistor 134 are complementarily controlled by the termination circuit control signals φ1 and φ2. As a result, a signal corresponding to the pattern signal generated by the pattern generation unit 109 is transmitted to the input circuit 114 via the input signal transmission path 124. Therefore, in this example, it is not necessary to input a test signal from the external test apparatus 201 via the data input terminal 122 for testing the input circuit 114. For this reason, the test apparatus 201 only needs to be able to output the clock signal CLK, the pattern setting signal PCNT, the test enable signal CE, and the like.

  (2) As shown in FIG. 3, it is conceivable to perform a loopback test by coupling the input terminal and the output terminal of the non-test device 301. However, in order to capture an address signal as in a semiconductor memory. If the number of output terminals differs from the number of input terminals due to the presence of input-only terminals such as address input terminals and command input terminals for capturing command signals, all the input circuits are It cannot be tested. On the other hand, in the semiconductor memory 100 employing the configuration shown in FIG. 1, the input circuit modules 111 are provided corresponding to all the input terminals, so that the input circuits 114 corresponding to all the input terminals are provided. Can be tested.

  (3) Since the termination circuit 121 is originally provided in the semiconductor chip for impedance matching, the pattern signal generated by the pattern generation unit 109 is transmitted to the input circuit 114 by using it. When the configuration shown in FIG. 1 is adopted, the self-diagnosis control circuit 115 is basically provided, so that the design change can be reduced.

<Embodiment 2>
FIG. 5 shows another configuration example of a main part in a semiconductor memory which is an example of a semiconductor device according to the present invention.

  The configuration shown in FIG. 5 is significantly different from that shown in FIG. 1 in that a multiplier circuit 501 that multiplies the frequency of the clock signal taken in via the input buffer 112 and outputs the result is provided. . A PLL (Phase Locked Loop) circuit can be applied to the multiplication circuit 501. The PLL circuit detects the phase difference between the input signal and the output signal, and controls the VCO (Voltage Controlled Oscillator) and the loop of the circuit to oscillate a signal with a precisely synchronized frequency and incorporate a counter. Thus, a signal can be output at a frequency that is an integral multiple of the input signal. Since the multiplication circuit 501 is provided, the clock signal transmitted from the outside to the clock input terminal 102 may have a frequency lower than the frequency of the clock signal CLK input to the data input register 113 or the self-diagnosis register 117. . In other words, according to the configuration shown in FIG. 5, the frequency of the clock signal supplied from the test apparatus 201 to the clock input terminal 102 can be lowered compared to the case where the configuration shown in FIG. 1 is adopted. .

<Embodiment 3>
FIG. 6 shows another test state of the semiconductor memory 100 shown in FIG.

  The test state shown in FIG. 6 is greatly different from that shown in FIG. 2 in that a multiplier circuit 601 is arranged between the test apparatus 201 and the clock input terminal 102 of the semiconductor memory 100. The semiconductor memory 100 shown in FIG. 6 has the same configuration as that shown in FIG.

  The multiplication circuit 601 multiplies the frequency of the clock signal output from the test apparatus 201 and outputs the result. As the multiplication circuit 601, a PLL (Phase Locked Loop) circuit can be applied as in the case shown in FIG. When the multiplier circuit 601 is thus arranged between the test apparatus 201 and the clock input terminal 102 of the semiconductor memory 100, the semiconductor memory 100 adopts the configuration shown in FIG. However, it is possible to obtain the same operation and effect as the configuration shown in FIG.

<Embodiment 4>
FIG. 7 shows another configuration example of a main part in a semiconductor memory which is an example of a semiconductor device according to the present invention.

  The configuration shown in FIG. 7 is significantly different from that shown in FIG. 1 in that the first clock signal CLK1 and the second clock signal CLK2 are taken in through separate clock input terminals 102-1 and 102-2, respectively. It is a point. The first clock signal CLK1 fetched from the first clock signal input terminal 102-1 via the input buffer 112-1 is transmitted to the data input register 113. The data input register 113 captures the output signal of the input circuit 114 in synchronization with the rising edge of the first clock signal CLK1. The self-diagnosis register 117 captures the output signal of the pattern generation unit 109 in synchronization with the rising edge of the second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 may have the same phase or different phases as long as the frequencies are equal to each other. Thus, even when the configuration shown in FIG. 7 is adopted, the same operational effects as those shown in FIG. 1 can be obtained.

<Embodiment 5>
FIG. 8 shows a test state of the semiconductor memory 100 shown in FIG.

  In the semiconductor memory 100 shown in FIG. 7, the first clock signal CLK1 and the second clock signal CLK2 are fetched through the separate clock input terminals 102-1 and 102-2, respectively. A test apparatus 201 used for testing the semiconductor memory 100 has an output terminal for outputting a clock signal corresponding to the clock input terminals 102-1 and 102-2. Also in such a test, the same effect as the case shown in FIG. 2 can be obtained.

<Embodiment 6>
FIG. 9 shows another configuration example of a main part in a semiconductor memory which is an example of a semiconductor device according to the present invention.

  The configuration shown in FIG. 9 is greatly different from that shown in FIG. 7 in that a frequency multiplication circuit 501 that multiplies the frequency of the clock signal taken in via the input buffer 112-1 to a higher frequency and outputs it. -1 is provided, and a frequency multiplication circuit 501-2 is provided which multiplies the frequency of the clock signal taken in via the input buffer 112-2 to a higher frequency and outputs it. A PLL circuit can be applied to the multiplication circuits 501-1 and 501-2. Since the multiplication circuits 501-1 and 501-2 are provided, the first and second clock signals transmitted from the outside to the clock input terminals 102-1 and 102-2 are transmitted to the data input register 113 and the self-diagnosis. The frequency may be lower than the frequency of the clock signals CLK-1 and CLK-2 input to the register 117. That is, according to the configuration shown in FIG. 9, the frequency of the clock signal supplied from the test apparatus 201 to the clock input terminals 102-1 and 102-2 is lower than when the configuration shown in FIG. 7 is adopted. can do.

<Embodiment 7>
FIG. 10 shows another test state of the semiconductor memory 100 shown in FIG.

  Since the first clock signal CLK1 and the second clock signal CLK2 are taken in through the separate clock input terminals 102-1 and 102-2, the test apparatus used for testing the semiconductor memory 100 as described above. Multiplier circuits 601-1 and 601-2 are provided between the first clock signal CLK1 and the second clock signal CLK2, respectively. The multiplication circuits 601-1 and 601-2 multiply the frequency of the clock signal output from the test apparatus 201 to a higher frequency and output it. A PLL circuit can be applied to the multiplication circuits 601-1 and 601-2. When the multiplier circuits 601-1 and 601-2 are thus arranged between the test apparatus 201 and the clock input terminals 102-1 and 102-2 of the semiconductor memory 100, the semiconductor memory 100 is shown in FIG. In spite of adopting the configuration shown in FIG. 9, it is possible to obtain the same operation and effect as the configuration shown in FIG. 9.

<Eighth embodiment>
FIG. 11 shows another configuration example of a main part in a semiconductor memory which is an example of a semiconductor device according to the present invention.

  The configuration shown in FIG. 11 is greatly different from that shown in FIG. 5 in that a phase adjustment circuit 1101 that adjusts and outputs the phase of the output signal of the multiplication circuit 501 is provided. The phase adjustment circuit 1101 adjusts the phase. The second clock signal CLK2 is supplied to the self-diagnosis register 117. The self-diagnosis register 117 captures the output signal of the pattern generation unit 109 in synchronization with the rising edge of the second clock signal CLK2 whose phase is adjusted by the phase adjustment circuit 1101.

  FIG. 12 shows the operation timing of the main part in the configuration shown in FIG.

  FIG. 12A shows an operation waveform when performing a test with respect to the setup time of the input circuit, and FIG. 12B shows an operation waveform when performing a test with respect to the hold time of the input circuit.

  According to the configuration shown in FIG. 11, an input setup test and an input circuit hold test can be performed.

  The phase adjustment circuit 1101 adjusts the phase of the second clock signal CLK2 before the first clock signal CLK1, thereby allowing the input circuit 114 and the data input register 13 to perform a desired test with respect to the input setup specification of the semiconductor memory 100. An input setup test can be performed by discriminating whether or not data is taken in by the pattern check unit 107.

  On the other hand, the phase adjustment circuit 1101 adjusts the phase of the second clock signal CL2 after the first clock signal CLK1, so that the input circuit 114 and the data input register 113 can be set in accordance with the input hold specifications of the semiconductor memory 100. By determining whether or not the test data is taken in by the pattern check unit 107, an input hold test can be performed.

  7 and 9, the test apparatus 201 adjusts the phase of the clock frequency input to the first clock input terminals 102-1 and 102-2, thereby providing the configuration shown in FIG. 11. The input setup test and the input hold test can be performed as in the case of the configuration described above.

<Embodiment 9>
FIG. 13 shows another configuration example of a semiconductor memory which is an example of a semiconductor device according to the present invention.

  The semiconductor memory shown in FIG. 13 is not particularly limited, but is a DDR (Double-Data-Rate) SRAM (Static Random Access Memory), which is a single-crystal silicon substrate or the like by a known semiconductor integrated circuit manufacturing technique. Formed on two semiconductor substrates. In the DDR method, various signals are exchanged at the rising edge / falling edge of the clock signal.

  The DDR SRAM shown in FIG. 13 includes an X decoder circuit group 1301, a word driver group 1302, a memory mat 1303, a Y decoder circuit group 1304, a column selection circuit group 1305, a data bus group, and an I / O circuit group 1306. .

  The memory mat 1303 is formed so that a plurality of word lines and a plurality of bit lines intersect, and a plurality of static memories are coupled to the word lines and the bit lines. The X decoder circuit group 1301 decodes the input X (row system) address. The word driver group 1302 drives the word line of the memory mat 1303 to the selected level based on the decode output of the X decoder circuit group 1301. The Y decoder 1304 decodes the input Y (column system) address. A column selection circuit group 1305 is a column selection circuit that performs column selection based on the decoding result of the Y decoder 1304, a write amplifier (WA) that amplifies a write signal to the memory mat 1303, and amplifies a read signal from the memory mat 1303. Sense amplifier (SA) to be included. The data bus group and I / O circuit group 1306 inputs and outputs input data and output data between the data bus group and the outside based on the input command signal.

  FIG. 14 shows a configuration example of the input circuit module 111 in the data bus group and I / O circuit group 1306.

  The input circuit module 111 is provided for taking in data for writing in the data bus group and the I / O circuit group 1306. The input circuit module 111 is greatly different from that shown in FIG. 1 in that it includes two data input registers 113-1, 113-2, two self-diagnosis registers 117-1, 117-2, and a selection circuit 1401. Is a point provided. The data input registers 113-1 and 113-2 are arranged in the subsequent stage of the input circuit 114. The self-diagnosis registers 117-1 and 117-2 and the selection circuit 1401 are provided in the self-diagnosis control circuit 115.

  The data input register 113-1 takes in the output signal of the input circuit 114 in synchronization with the falling edge of the clock signal CLK. The data input register 113-2 takes in the output signal of the input circuit 114 in synchronization with the rising edge of the clock signal CLK. The output signal Burst0 of the data input register 113-1 and the output signal Burst1 of the data input register 113-2 are transmitted to the pattern check unit 107 (see FIG. 1). The self-diagnosis register 117-1 takes in the pattern signal from the pattern generator 109 in synchronization with the falling edge of the clock signal CLK. The self-diagnosis register 117-2 takes in the pattern signal from the pattern generator 109 in synchronization with the rising edge of the clock signal CLK. The selector 1401 selectively transmits the output signal of the self-diagnosis register 117-1 to the NAND gate 118 when the clock signal CLK is at a low level (logic value “0”), and the clock signal CLK is at a high level. In the case of (logic value “1”), the output signal of the self-diagnosis register 117-2 is selectively transmitted to the NAND gate 118.

  The X decoder 1301 and the Y decoder 1304 include an input circuit module for capturing an address signal, and the data bus group and the I / O circuit group 1306 include an input circuit module for capturing a command signal. Included and are configured in the same manner as shown in FIG.

  FIG. 15 shows the operation timing of the main part in FIG.

  According to the configuration shown in FIG. 14, the self-diagnosis register 117-1 receives the pattern signal from the pattern generation unit 109 in synchronization with the falling edge of the clock signal CLK, and the self-diagnosis register At 117-2, the pattern signal from the pattern generator 109 is taken in synchronization with the rising edge of the clock signal CLK. The selector 1401 transmits the output signal of the self-diagnosis register 117-1 to the NAND gate 118 when the clock signal CLK is at a low level, and the self-diagnosis register when the clock signal CLK is at a high level. The output signal 117-2 is transmitted to the NAND gate 118. The p-channel MOS transistor 131 and the n-channel MOS transistor 134 are controlled by the output signals of the NAND gate 119 and the NAND gate 120, so that the pattern signal (test data) is transmitted to the input circuit 114. The data input register 113-1 takes in the output signal of the input circuit 114 in synchronization with the falling edge of the clock signal CLK, and the data input register 113-2 synchronizes with the rising edge of the clock signal CLK. The output signal of the input circuit 114 is captured. As described above, in the DDR method, signals are exchanged at each of the rising edge / falling edge of the clock signal CLK, so that twice the data is transmitted to the pattern check unit 107 as compared to the configuration example shown in FIG. The

  Even in the configuration corresponding to the DDR system, the same operational effects as in the configuration shown in FIG. 1 and the like can be obtained.

<Embodiment 10>
FIG. 16 shows another configuration example of the input circuit module 111 shown in FIG.

  The input circuit module 111 shown in FIG. 16 is significantly different from that shown in FIG. 1 in that the configuration of the termination circuit 121 and the controller 163 are added. The termination circuit 121 includes a plurality of pull-up resistor elements 132-1 to 132-n, a plurality of pull-down resistor elements 133-1 to 133-n, a plurality of p-channel MOS transistors 131-1 to 131-n, N-channel MOS transistors 134-1 to 134-n. The plurality of pull-up resistor elements 132-1 to 132-n and the corresponding p-channel MOS transistors 131-1 to 131-n are connected in series to each other. The plurality of pull-down resistance elements 133-1 to 133-n and the corresponding n-channel MOS transistors 134-1 to 134-n are connected in series to each other. The source electrodes of the p-channel MOS transistors 131-1 to 131-n are coupled to the high potential side power supply Vddq. The source electrodes of the n-channel MOS transistors 134-1 to 134-n are coupled to the low potential side power source Vss. A level conversion circuit LC that performs level conversion of the output signal of the self-diagnosis control circuit 115 is provided at the gate electrodes of the p-channel MOS transistors 131-1 to 131-n and the n-channel MOS transistors 134-1 to 134-n. Are combined. Thus, the output signal of the self-diagnosis control circuit 115 is level-converted by the level conversion circuit LC and then transmitted to the gate electrode of the corresponding transistor.

  In the self-diagnosis control circuit 115, the AND gate 119 and the NAND gate 120 have a plurality of numbers corresponding to the p-channel MOS transistors 131-1 to 131-n and the n-channel MOS transistors 134-1 to 134-n, respectively. (N) are provided. The plurality of AND gates 119 and NAND gates 120 are individually input with output signals of the termination circuit control logic 116. Thus, the p-channel MOS transistors 131-1 to 131-n and the n-channel MOS transistors 134-1 to 134-n can be individually controlled by the termination circuit control logic 116.

  The termination circuit control logic 116 is connected to the p-channel MOS transistors 131-1 to 131-n according to a non-test mode in which a signal taken in via the data input terminal 122 is transmitted to the input circuit 114 and a pattern signal. The n-channel MOS transistors 134-1 to 134-n are controlled to switch to the test mode in which the pattern signal is transmitted to the input circuit 114. The non-test mode is realized by supplying a high level signal to the AND gate 119 and the NAND gate 120 by the termination circuit control logic 116. The test mode is realized by supplying a low level signal to the AND gate 119 and the NAND gate 120 by the termination circuit control logic 116.

  The semiconductor memory 100 is provided with an external terminal 162 to which the adjustment resistance element 161 is externally attached. The external terminal 162 is coupled to the controller 163. The controller 163 includes the plurality of pull-up resistor elements 132-1 to 132-n and the plurality of n-channel MOS transistors according to the resistance value of the adjustment resistor element 161 externally attached to the external terminal 162. Codes for controlling 134-1 to 134-n are generated and output to the termination circuit control logic 116. Specifically, the transistors to be controlled by the self-diagnosis control circuit are the pull-up resistor elements 132-1 to 132-n and the n-channel MOS transistors 134-1 to 134-n. Is output to the termination circuit control logic 116. The termination circuit control logic 116 determines the logic of signals supplied to the AND gate 119 and the NAND gate 120 according to the output signal of the controller 163 in the test mode. Thereby, a transistor to be controlled by the self-diagnosis control circuit 115 is determined.

  In the above configuration, by changing the resistance value of the adjustment resistor 161 externally attached to the external terminal 162, the high level potential of the pattern signal transmitted to the input circuit 114, the low level potential, Can be adjusted. For example, as shown in FIG. 18, a predetermined high potential side power supply Vtt is supplied to the data input terminal 122 via the signal line 181. Here, the wiring resistance of the signal line 181 is defined as “Rtt”. When the combined resistance value of the plurality of pull-up resistor elements 132-1 to 132-n is “Rup” and the combined resistance value of the plurality of pull-down resistor elements 132-1 to 132-n is “Rdn”, the above input The high level potential VIH and the low level potential VIL of the pattern signal transmitted to the circuit 114 are expressed by the following equations.

  Accordingly, the resistance value of the adjustment resistor 161 externally attached to the external terminal 162 is changed to combine the combined resistance value Rup of the pull-up resistor elements 132-1 to 132-n and the pull-down resistor element 132-1. By adjusting the combined resistance value Rdn of .about.132-n, the high level potential and the low level potential of the pattern signal transmitted to the input circuit 114 can be adjusted. In this way, the high level potential and the low level potential of the pattern signal transmitted to the input circuit 114 are adjusted, and the output signal of the data input register 113 at that time is compared with the expected value by the pattern check unit 107. Thus, an analog test of the input circuit 114 can be performed.

  FIG. 17 shows a layout example of a semiconductor chip when the configuration shown in FIG. 16 is adopted.

  The termination circuit 121 is laid out in the termination circuit layout section. The input circuit 114 is laid out in the input circuit layout section. The level conversion circuit LC is laid out in the level conversion circuit layout section. The self-diagnosis control circuit 115 is laid out in the self-diagnosis control circuit layout section. The termination circuit control logic 116 is laid out in the termination circuit control logic layout section. The data input register 113 and other circuits are laid out in the data input register and other circuit layout sections. Since the self-diagnosis control circuit 115 has fewer constituent elements than the termination circuit control logic 116 and other circuits, the chip occupation area can be reduced. Therefore, when this self-diagnosis control circuit 115 is newly formed, the influence on the layout of the existing circuit is small.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  Further, it goes without saying that the present invention is not limited to SRAM, and can be applied to various semiconductor integrated circuit devices and systems.

DESCRIPTION OF SYMBOLS 100 Semiconductor memory 101 Test output terminal 102 Clock input terminal 103 1st test input terminal 104 2nd test input terminal 106 Output buffer 107 Pattern check part 108,112,110 Input buffer 109 Pattern generation part 111 Input circuit module 122 Data input terminal 113 Data input register 114 Input circuit 115 Self-diagnosis control circuit 116 Termination circuit control logic 117 Self-diagnosis register 118 Nand gate 119 And gate 120 Nand gate 131 P-channel MOS transistor 132 Pull-up resistance element 133 Pull-down resistance element 134 N-channel type MOS Transistor 161 Resistance element for adjustment 163 Controller 201 Test apparatus

Claims (9)

An input terminal for capturing the signal;
An input circuit through which a signal taken in via the data input terminal is transmitted;
A termination circuit for defining the input impedance at the input terminal;
A clock input terminal for capturing a clock signal;
A register for capturing the output signal of the input circuit in synchronization with the clock signal;
A pattern generator for generating a pattern signal for self-diagnosis;
A pattern check unit that compares the output signal of the register with an expected value;
The termination circuit includes a first resistance element for pulling up an input side path of the input circuit;
A first transistor connected in series to the first resistance element;
A second resistance element for pulling down the input side path of the input circuit;
A semiconductor device comprising: a second transistor connected in series to the second resistance element;
The pattern signal generated by the pattern generation unit is captured in synchronization with the clock signal, and the pattern signal is transmitted to the input circuit by controlling the first transistor and the second transistor according to the captured pattern signal. A semiconductor device comprising a self-diagnosis control circuit for the purpose. Including a multiplier circuit for multiplying the clock signal taken in via the clock input terminal;
The register captures the output signal of the input circuit in synchronization with the clock signal multiplied by the multiplication circuit,
2. The semiconductor device according to claim 1, wherein the self-diagnosis control circuit takes in the pattern signal generated by the pattern generation unit in synchronization with the clock signal multiplied by the multiplication circuit. An input terminal for capturing the signal;
An input circuit through which a signal taken in via the input terminal is transmitted;
A termination circuit for defining the input impedance at the input terminal;
A first clock input terminal for capturing a first clock signal;
A second clock input terminal for capturing a second clock signal different from the first clock signal;
A register for capturing an output signal of the input circuit in synchronization with the first clock signal;
A pattern generator for generating a pattern signal for self-diagnosis;
A pattern check unit that compares the output signal of the register with an expected value;
The termination circuit includes a first resistance element for pulling up an input side path of the input circuit;
A first transistor connected in series to the first resistance element;
A second resistance element for pulling down the input side path of the input circuit;
A semiconductor device comprising: a second transistor connected in series to the second resistance element;
The pattern signal generated by the pattern generation unit is captured in synchronization with the second clock signal, and the first transistor and the second transistor are controlled according to the captured pattern signal, whereby the pattern signal is input to the input circuit. And a self-diagnosis control circuit for transmitting the semiconductor device. A first multiplication circuit for multiplying the first clock signal taken in via the first clock input terminal;
A second multiplier circuit for multiplying the second clock signal taken in via the second clock input terminal,
The register takes in the output signal of the input circuit in synchronization with the first clock signal multiplied by the first multiplication circuit,
4. The semiconductor device according to claim 3, wherein the self-diagnosis control circuit takes in the pattern signal generated by the pattern generation unit in synchronization with a second clock signal multiplied by the second multiplication circuit. An input terminal for capturing the signal;
An input circuit through which a signal taken in via the input terminal is transmitted;
A termination circuit for defining the input impedance at the input terminal;
A clock input terminal for capturing the first clock signal;
A pattern generator for generating a pattern signal for self-diagnosis;
A pattern check unit that compares the output signal of the register with an expected value;
The termination circuit includes a first resistance element for pulling up an input side path of the input circuit;
A first transistor connected in series to the first resistance element;
A second resistance element for pulling down the input side path of the input circuit;
A semiconductor device comprising: a second transistor connected in series to the second resistance element;
A multiplier for multiplying the first clock signal taken in via the clock input terminal;
A phase adjustment circuit that forms a second clock signal by adjusting the phase of the first clock signal multiplied by the multiplication circuit;
The pattern signal generated by the pattern generation unit is captured in synchronization with the second clock signal, and the first transistor and the second transistor are controlled according to the captured pattern signal, whereby the pattern signal is input to the input circuit. A self-diagnosis control circuit for transmitting;
A register that captures the output signal of the input circuit in synchronization with the first clock signal multiplied by the multiplication circuit;
A semiconductor device comprising: a pattern check unit that compares an output signal of the register with an expected value. A memory mat capable of storing data;
A first circuit for capturing an address signal for writing or reading data to or from the memory mat;
A second circuit for capturing a command signal instructing an operation relating to data writing or reading to the memory mat;
A third circuit for capturing data for writing to the memory mat,
The first circuit, the second circuit, and the third circuit each include an input circuit module,
The input circuit module includes an input circuit to which an input signal is transmitted,
A termination circuit for defining the input impedance of the input side path of the input circuit;
A first register for capturing the output signal of the input circuit in synchronization with the rising edge of the clock signal;
A second register for capturing the output signal of the input circuit in synchronization with the falling edge of the clock signal;
The termination circuit includes a first resistance element for pulling up an input side path of the input circuit;
A first transistor connected in series to the first resistance element;
A second resistance element for pulling down the input side path of the input circuit;
A semiconductor device comprising: a second transistor connected in series to the second resistance element;
A self-diagnosis control circuit for supplying the pattern signal to the input circuit by controlling the first transistor and the second transistor according to a pattern signal for self-diagnosis;
The self-diagnosis control circuit includes a third register that captures the pattern signal in synchronization with a rising edge of the clock signal;
A fourth register for capturing the pattern signal in synchronization with the falling edge of the clock signal;
A selection circuit that selects an output signal of the third register in synchronization with a rising edge of the clock signal, and selects an output signal of the fourth register in synchronization with a falling edge of the clock signal;
The semiconductor device, wherein the first transistor and the second transistor are controlled based on a selection output of the selection circuit. A first mode in which a signal taken in via the input terminal is transmitted to the input circuit;
Control logic for switching to a second mode in which the pattern signal is transmitted to the input circuit by controlling the first transistor and the second transistor according to the pattern signal;
The semiconductor device according to claim 1, wherein the control logic fixes both the first transistor and the second transistor in an on state in the first mode. A signal input terminal for capturing the signal;
An input circuit through which a signal taken in via the signal input terminal is transmitted;
A termination circuit for defining the input impedance at the input terminal;
A clock input terminal for capturing a clock signal;
A register for capturing the output signal of the input circuit in synchronization with the clock signal;
A pattern generator for generating a pattern signal for self-diagnosis;
A pattern check unit that compares the output signal of the register with an expected value;
The termination circuit includes a plurality of first resistance elements for pulling up an input side path of the input circuit,
A plurality of first transistors each connected in series to the first resistance element;
A plurality of second resistance elements for pulling down the input side path of the input circuit;
A plurality of second transistors each connected in series to the second resistance element,
The pattern signal generated by the pattern generation unit is captured in synchronization with the clock signal, and the pattern signal is transmitted to the input circuit by controlling the first transistor and the second transistor according to the captured pattern signal. A self-diagnosis control circuit for
An external terminal to which an adjustment resistance element is externally attached;
A transistor to be controlled by the self-diagnosis control circuit is selected from the plurality of first transistors and the plurality of second transistors according to a resistance value of the adjustment resistor element connected to the external terminal. And a controller for performing the operation. An input terminal for capturing the signal;
An input circuit through which a signal taken in via the input terminal is transmitted;
A first resistance element for pulling up the input side path of the input circuit;
A clock input terminal for capturing a clock signal;
A register for capturing the output signal of the input circuit in synchronization with the clock signal;
A pattern generator for generating a pattern signal for self-diagnosis;
A pattern check unit that compares the output signal of the register with an expected value;
The termination circuit includes a first transistor connected in series to the first resistance element;
A second resistance element for pulling down the input side path of the input circuit;
A second transistor connected in series to the second resistance element;
The pattern signal generated by the pattern generation unit is captured in synchronization with the clock signal, and the pattern signal is supplied to the input circuit by controlling the first transistor and the second transistor according to the captured pattern signal. A test method for a semiconductor device provided with a self-diagnosis control circuit for
A test device for testing the semiconductor device is coupled to the semiconductor device;
A multiplier circuit for multiplying the clock signal output from the test apparatus is externally attached to the clock input terminal in the semiconductor device,
Instructing the pattern generation unit in the semiconductor device from the test apparatus to generate the pattern signal,
The clock signal multiplied by the multiplier circuit is transmitted to the clock input terminal in the semiconductor device,
A test method of a semiconductor device, wherein a comparison result in the pattern check unit in the semiconductor device is taken into the test device.

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