JP5442522B2 - Test circuit for semiconductor integrated circuit - Google Patents

Description

The present invention converts the serial test data input from the outside of the semiconductor integrated circuit into parallel data, and relates to test circuitry for testing is supplied to the macro or the like of the test subject.

  Generally, when testing a macro mounted on a semiconductor integrated circuit (semiconductor chip), a shift register is prepared so that the input signal to the macro can be controlled independently from the outside during the test. The reset signal, clock signal, and serial data are input from the outside of the integrated circuit via the external connection pins, and each time the clock signal is input, the input serial data is sequentially shifted and held in the shift register. Thereafter, the output signal of the shift register is input to the macro as parallel data for testing.

  However, if the output signal of the flip-flop (hereinafter also referred to as FF) of the shift register is directly input to the macro, the input signal to the macro is frequently toggled during the writing of the serial data to each FF. It is expected that some operations will be adversely affected.

  In order to prevent this, a shift signal is input via another external connection pin, and an AND or MUX (multiplexer) of the shift signal and the output signal of each FF of the shift register is input to a macro (for example, a patent) Using the shift signal as a clock, the output signal of the FF of the shift register is latched by another FF and input to the macro, and the macro input signal toggle is suppressed to perform the test. The method of doing is considered.

  Hereinafter, a conventional test circuit will be described using the test circuit proposed in Patent Document 1 as an example.

  FIG. 13 is an example circuit diagram showing a configuration of a test circuit of a conventional semiconductor integrated circuit. The test circuit 44 shown in the figure is constituted by the shift register 12 and the output control circuit 16.

  The shift register 12 is configured by connecting n + 1 FFs in series. The reset signal RESET and the clock signal CLK are input to the reset terminals and clock terminals of all the FFs of the shift register 12, respectively, and the serial data DIN is input to the data input terminal D of the first stage FF. The output signal from the data output terminal Q of each FF is sequentially input to the data input terminal D of the next stage FF and also to the output control circuit 16.

  The output control circuit 16 performs output control of the output signal of the FF of the shift register 12 using the shift signal SHIFT, and is configured by n + 1 AND gates corresponding to each FF of the shift register 12. A corresponding FF output signal is input to one input terminal of each AND gate, and a shift signal SHIFT is input to the other input terminal. Each AND gate outputs test parallel data D [n: 0].

  Next, an operation when testing a test target macro or the like using the test circuit 44 will be described.

  During the test, the reset signal RESET, the clock signal CLK, the serial data DIN, and the shift signal SHIFT are supplied from the outside of the semiconductor integrated circuit through the external connection pins of the reset terminal, the clock terminal, the serial data terminal, and the shift terminal of the semiconductor integrated circuit. Are input to the test circuit 44.

  First, when a low level is input as the reset signal RESET, the output signals of all the FFs of the shift register 12 are initialized to a low level. When a low level is input as the shift signal SHIFT, the output signal of the output control circuit 16 is initialized to a low level.

  Subsequently, after inputting a high level as the reset signal RESET (after reset release), the clock signal CLK and the serial data DIN are sequentially input. In the shift register 12, every time the clock signal CLK is inputted, the serial data DIN inputted at the same time is held in the first stage FF, and the output signal of the preceding stage FF is sequentially shifted to the succeeding stage FF. In this way, the serial data DIN is held in all the FFs of the shift register 12 by sequentially shifting the n + 1 serial data DIN.

  When the writing of the serial data to the shift register 12 is completed, that is, after inputting n + 1 pieces of serial data, the input of the clock signal CLK is stopped. As a result, the value of the serial data held in the shift register 12 is fixed.

  Thereafter, when the shift signal SHIFT is set to the high level, output signals of the corresponding FFs of the shift register 12 are output from the AND gates of the output control circuit 16. The output signal of the output control circuit 16, that is, test parallel data D [n: 0] is input to a test target macro or the like.

  In the example of FIG. 13, an AND gate is used as the output control circuit 16, but as described above, the same applies to the case where this is a MUX or an FF using the shift signal SHIFT as a clock.

JP-A-1-320545

  As described above, the shift signal SHIFT, that is, the shift terminal is added to the semiconductor integrated circuit and the output signal of the shift register 12 is controlled, so that the serial data is being written to each FF of the shift register 12. Therefore, it is possible to prevent the input signal to the macro from toggling frequently. However, an increase in the number of external connection pins for testing is a big problem, and it is not desirable to increase even if there is only one pin.

Accordingly, an object of the present invention is to provide a testing circuitry of a semiconductor integrated circuit which can test without a test target macro like adding an external connection pins for testing required for the test.

In order to achieve the above object, the present invention is configured by connecting a plurality of flip-flops including a data setting flip-flop in series, and for testing each time a test signal is input, the test target is tested. When the shift register for sequentially shifting the serial data and the serial data of the predetermined pattern determined in advance are set in at least one predetermined flip-flop of the shift register, the output control in the active state is performed Using a setting detection circuit that outputs a signal and an output control signal input from the setting detection circuit, output control of the parallel data output from the plurality of data setting flip-flops of the shift register to the test target is performed. And an output control circuit for performing the operation of the semiconductor integrated circuit. There is provided a preparative circuit.

  Here, when the setting detection circuit detects that the serial data of the predetermined pattern is set in the data setting flip-flop at the final stage of the shift register, the setting detection circuit may output the output control signal in the active state. preferable.

The shift register further includes a test flip-flop connected to a subsequent stage of the data setting flip-flop of the final stage of the plurality of flip-flops,
The setting detection circuit preferably outputs the output control signal in the active state when detecting that the serial data of the predetermined pattern is set in the test flip-flop.

  The setting detection circuit includes a delay circuit that delays the output control signal, and the output control circuit uses the output control signal delayed by the delay circuit to set a plurality of data setting flip-flops of the shift register. It is preferable to perform output control of the output signal.

  The test circuit of the present invention detects the completion of the writing of serial data to the shift register based on the output signal of the data setting flip-flop of the shift register, and outputs the output signal of the shift register as test parallel data To do. Therefore, unlike the conventional test circuit, an external connection pin for inputting the shift signal from the outside of the semiconductor integrated circuit is not necessary, and the external connection pins necessary for the test can be reduced.

It is a circuit conceptual diagram of one Embodiment showing the structure of the test circuit of the semiconductor integrated circuit of this invention. It is a circuit diagram of the 1st example showing the composition of the test circuit of the present invention. 3 is a timing chart showing the operation of the test circuit shown in FIG. It is a circuit diagram of the 2nd example showing the structure of the test circuit of this invention. 5 is a timing chart showing the operation of the test circuit shown in FIG. It is a circuit diagram of the 3rd example showing the composition of the test circuit of the present invention. 7 is a timing chart showing the operation of the test circuit shown in FIG. FIG. 7 is a circuit diagram illustrating a configuration of a modified example of the test circuit illustrated in FIG. 6. FIG. 7 is a circuit diagram illustrating a configuration of a modified example of the test circuit illustrated in FIG. 6. It is a circuit diagram of the 4th example showing the composition of the test circuit of the present invention. It is a timing chart showing operation | movement of the test circuit shown in FIG. It is a circuit diagram of one Embodiment showing the composition of the stop circuit of a clock signal. It is an example circuit diagram showing the structure of the conventional test circuit.

  Hereinafter, a test circuit and a test method for a semiconductor integrated circuit according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a circuit conceptual diagram of an embodiment showing a configuration of a test circuit of a semiconductor integrated circuit according to the present invention. A test circuit 10 shown in FIG. 1 is mounted on a semiconductor integrated circuit, and converts test serial data DIN input from the outside of the semiconductor integrated circuit into parallel data D [n: 0] at the time of testing. And includes a shift register 12, a setting detection circuit 14, and an output control circuit 16.

  The shift register 12 is configured by connecting n + 1 FFs in series as data setting FFs for setting test data. The reset signal RESET and the clock signal CLK are input to the reset terminals and clock terminals of all the FFs of the shift register 12, respectively, and the serial data DIN is input to the data input terminal D of the first stage FF. The output signal output from the data output terminal Q of each FF is sequentially input to the data input terminal D of the next-stage FF and also input to the setting detection circuit 14 and the output control circuit 16.

  When the setting detection circuit 14 detects that the predetermined serial data of the predetermined pattern is set in at least one predetermined FF of the shift register 12 based on the output signal of the FF of the shift register 12. Then, it recognizes that the writing of the test serial data to the shift register 12 is completed, and outputs a high-level output control signal in an active state. The output control signal corresponds to a conventional shift signal SHIFT and is input to the output control circuit 16.

  The output control circuit 16 performs output control of the output signal of the FF of the shift register 12 to the test target macro or the like using the output control signal that is the output signal of the setting detection circuit 14. N + 1 AND gates corresponding to each FF. An output signal of the corresponding FF is input to one input terminal of each AND gate, and an output control signal is input to the other input terminal. Each AND gate outputs test parallel data D [n: 0].

  Next, an operation when testing a test target macro or the like using the test circuit 10 will be described.

  During the test, the reset signal RESET, the clock signal CLK, and the serial data DIN are provided as test patterns from the outside of the semiconductor integrated circuit, such as a semiconductor tester, and the external connection pins of the reset terminal, the clock terminal, and the serial data terminal of the semiconductor integrated circuit. To the test circuit 10.

  First, when a low level is input as the reset signal RESET, the output signals of all the FFs of the shift register 12 are initialized to a low level. As a result, the output control signal output from the setting detection circuit 14 and the parallel data D [n: 0] output from the output control circuit 16 are also initialized to a low level. Thereafter, the operations until the n + 1 serial data are sequentially shifted and held in the shift register 12 and the clock signal CLK is stopped are the same as those of the conventional test circuit 44.

  When the setting detection circuit 14 detects that serial data of a predetermined pattern determined in advance is set in at least one predetermined FF, the setting detection circuit 14 outputs a high-level output control signal in an active state. Thereafter, the operation until the test parallel data D [n: 0] is output from the output control circuit 16 is the same as that of the conventional test circuit 44.

  Further, when the next test parallel data D [n: 0] is input to the test target macro or the like, the above operation is repeated from the beginning.

  The test circuit 10 detects that the writing of serial data to the shift register 12 is completed based on the output signal of the FF of the shift register 12, and uses the output signal of the shift register 12 as parallel data D [n: 0 for testing. ] Is output. Therefore, unlike the conventional test circuit 44, there is no need for an external connection pin for inputting the shift signal SHIFT from the outside of the semiconductor integrated circuit, and the number of external connection pins required for testing can be reduced.

  Note that the specific circuit configuration of the setting detection circuit 14 is not limited as long as the setting detection circuit 14 realizes the above function. For example, the FF used for detection by the setting detection circuit 14 may be the last stage FF of the shift register 12 or may be two or more FFs including the last stage FF. In addition to the data setting flip-flop for setting the test data, one or more test flip-flops connected in series at the subsequent stage of the data setting flip-flop are added, and the shift register 12 is It is also possible to configure. Then, it may be configured that the data output from the data setting flip-flop is controlled by detecting that the predetermined pattern is set in the test flip-flop.

  Further, the active state of the output control signal may be set to a low level. Furthermore, the output control circuit 16 is not limited to an AND gate, and various gate circuits, MUX, FF, and the like can be used.

  Hereinafter, the description will be continued with specific examples of the test circuit of the present invention.

  FIG. 2 is a circuit diagram of a first specific example showing the configuration of the test circuit of the present invention. The test circuit 18 shown in the figure is configured by configuring the setting detection circuit 14 in the test circuit 10 shown in FIG. 1 with wiring that outputs the output signal of the last stage FF of the shift register 12 as an output control signal.

  That is, when the setting detection circuit 14 of the test circuit 18 detects that the high level is set in the FF at the final stage of the shift register 12, the setting detection circuit 14 outputs a high-level output control signal in an active state.

  In the test circuit 18, as shown in the timing chart of FIG. 3, a high level (= '1') is input as the first serial data DIN (= D [0]) after reset release, and then D [1: n] corresponding to serial data DIN is sequentially input. That is, after the reset is released, the n + 1 serial data DIN is shifted to complete the writing of the serial data DIN to the shift register 12.

  The serial data DIN is don't care until the reset signal RESET is released and becomes high level. The parallel data D [n: 0] is undefined until the reset signal RESET becomes low level. The same applies to the subsequent timing charts.

  When the output signal of the FF in the final stage of the shift register 12, that is, the output control signal becomes active high level, the output signal of each FF of the shift register 12 is output from each AND gate of the output control circuit 16 to the test parallel. Data D [n: 0] is output.

  As described above, in the test circuit 18, it is necessary to input a high level as the first serial data DIN after reset release at the time of the test. Therefore, the data D [0] of the parallel data D [n: 0] Fixed to high level. Therefore, the test circuit 18 is suitable when the data D [0] may be fixed at a high level as the test parallel data D [n: 0] for the test target macro or the like.

  Although the test circuit 18 is limited as described above, since the setting detection circuit 14 can be configured only by wiring, there is no increase in the circuit scale.

  In the test circuit 18, the setting detection circuit 14 may output an output control signal in an active state when detecting that the low level is set in the final stage FF. In this case, the configuration of the output control circuit 16 needs to be changed as appropriate.

  The test circuit 18 inputs a high level as the first serial data DIN after reset release at the time of the test, and sets the high level to the final stage FF. Therefore, as shown in FIG. 12, after writing serial data to the shift register 12, the clock signal CLK is ORed with the output signal (high level) of the FF at the final stage to obtain the clock. The input of the clock signal CLK to the shift register 12 can be stopped without stopping the input of the signal CLK.

  Next, FIG. 4 is a circuit diagram of a second specific example showing the configuration of the test circuit of the present invention. The test circuit 20 shown in FIG. 1 is obtained by configuring the setting detection circuit 14 with an AND gate 22 in the test circuit 10 shown in FIG. The output signal of the first stage FF and the output signal of the last stage FF of the shift register 12 are input to the AND gate 22 of the setting detection circuit 14 of the test circuit 20, and the output signal of the AND gate 22 is output as an output control signal. The

  That is, when the AND gate 22 of the setting detection circuit 14 of the test circuit 20 detects that the high level is set to both the first-stage FF and the final-stage FF, the AND-level output control signal in the active state is output. Output.

  In the test circuit 20, as shown in the timing chart of FIG. 5, a high level is input as the first serial data DIN (= D [0]) after the reset is released, and subsequently corresponds to D [1: n−1]. Serial data DIN to be input is sequentially input, and a high level is input as the last serial data DIN (= D [n]). That is, after the reset is released, the n + 1 serial data DIN is shifted to complete the writing of the serial data DIN to the shift register 12.

  When the output signal of the first stage FF and the output signal of the last stage FF of the shift register 12 become high level, the output signal of the AND gate 22 of the setting detection circuit 14, that is, the output control signal becomes high level, which is in an active state, From each AND gate of the output control circuit 16, an output signal of each FF of the shift register 12 is output as test parallel data D [n: 0].

  As described above, in the test circuit 20, it is necessary to input a high level as the first and last serial data DIN after reset release at the time of the test. Therefore, the data D [0 of the parallel data D [n: 0] is required. ] And data D [n] are fixed at a high level. Therefore, the test circuit 20 is suitable when the data D [0] and D [n] may be fixed at a high level. However, when predetermined data is set in both of the two flip-flops as compared with the test circuit 18 that outputs test parallel data only by setting predetermined data in the final flip-flop. By outputting test parallel data, it is possible to prevent erroneous test data from being output due to noise and starting a test.

  Although the test circuit 20 is limited as described above, since the setting detection circuit 14 can be configured by only the AND gate 22, the circuit scale is hardly increased.

  In the test circuit 20, the setting detection circuit 14 detects that a predetermined pattern is set in at least two FFs. The at least two flip-flops are the first-stage and final-stage flip-flops. It is not essential to include

  Next, FIG. 6 is a circuit diagram of a third specific example showing the configuration of the test circuit of the present invention. The test circuit 24 shown in FIG. 1 is connected to the test circuit 10 shown in FIG. 1 by adding a test flip-flop 26 after the data setting flip-flop constituting the shift register 12 and connecting the setting detection circuit 14. The wiring is configured to output the output signal of the test FF 26 as an output control signal.

  That is, when the setting detection circuit 14 of the test circuit 24 detects that the high level is set in the test FF 26, the setting detection circuit 14 outputs a high-level output control signal in an active state.

  In the test circuit 24, as shown in the timing chart of FIG. 7, the high level is input as the first serial data DIN after the reset is released (= the serial data of the test FF 26), and subsequently to D [n: 0]. Corresponding serial data DIN is sequentially input. That is, by shifting n + 2 pieces of serial data DIN after reset release, writing of the serial data DIN to the shift register 12 is completed.

  When the output signal of the test FF 26, that is, the output control signal becomes the active high level, the output signal of each FF of the shift register 12 is output from each AND gate of the output control circuit 16 to the test parallel data D [ n: 0].

  As described above, in the test circuit 24, it is necessary to input a high level as the first serial data DIN after the reset is released and to input n + 2 serial data, which is one more than in the past, at the time of the test. .

  Although the number of serial data inputs increases, the test circuit 24 can be configured only by adding one test FF 26 to the subsequent stage of the shift register 12, so that the circuit scale hardly increases. Further, unlike the test circuit 18 in FIG. 2 and the test circuit 20 in FIG. 4, the test circuit 24 does not fix the data of a predetermined bit of the parallel data D [n: 0] to a predetermined value. It can be applied to any test target macro.

  Note that the setting detection circuit 14 of the test circuit 24 may output an output control signal in the active state when detecting that the low level is set in the test FF 26.

  Further, the output signal of the test FF 26, that is, the output control signal has a wiring length longer than that of the FF output signal for the parallel data D [n: 0], and the change timing is usually the output of the other FF. It will be slower than the signal. Therefore, even if the output signal of the test FF 26 is directly input to the AND gate of the output control circuit 16 as an output control signal, no glitch is generated in the output signal of each AND gate of the output control circuit 16.

  However, as shown in the test circuit 28 of FIG. 8, the setting detection circuit 14 includes a delay circuit 30 that delays the output control signal, that is, the output signal of the test FF 26, and the output control delayed by the delay circuit 30. It is desirable to input the signal to the AND gate of the output control circuit 16. Thereby, the change timing of the output control signal can be surely delayed as compared with the output signals of the other FFs, and the occurrence of glitches in the output signals of the AND gates of the output control circuit 16 can be reliably prevented.

  Further, as shown in the test circuit 32 of FIG. 9, when the output control signal is in the inactive state of low level, the output control signal is changed according to the logic level required as the input signal of the test target macro or the like. Output both output signals so that the output signal of the output control circuit 16 at the low level, that is, the parallel data D [n: 0] can be selected as all 0 or all 1 can be selected. It is desirable to configure so that

  The output control circuit 16 shown in FIG. 9 includes an AND gate and a NAND gate corresponding to each FF of the shift register 12. The configuration of each AND gate is the same as that of the test circuit 24 shown in FIG. Further, an output signal (inverted output signal) from the inverted data output terminal QB of the corresponding FF is input to one inverting input terminal of each NAND gate, and the output of the test FF 26 is input to the other input terminal. A signal, that is, an output control signal is input.

  In the output control circuit 16 shown in FIG. 9, when the output control signal is at a low level, the test parallel data D [n: 0] output from each AND gate is all 0, and the test output from each NAND gate. The parallel data DB [n: 0] for use is all ones. On the other hand, when the output control signal becomes high level, the output signals of the plurality of FFs of the shift register 12 are output as parallel data D [n: 0] and DB [n: 0].

  By using the test circuit 32 shown in FIG. 9, a semiconductor integrated circuit designer can appropriately select a logic level of a signal input to a test target macro or the like when the output control signal is in an inactive state. .

  Next, FIG. 10 is a circuit diagram of a fourth specific example showing the configuration of the test circuit of the present invention. The test circuit 34 shown in the figure is the same as the test circuit 10 shown in FIG. 1 except that the first stage FF of the shift register 12 is located between the i-th stage FF and the i + 1-th stage FF (1 ≦ i ≦ 1). n-1) and test FFs (indicated by square dotted lines in the figure) 36, 38, and 40 are connected to the subsequent stage of the final stage FF, and the setting detection circuit 14 is configured by an AND gate 42. Is. The output signals of the three test FFs 36, 38, and 40 are input to the AND gate 42 of the setting detection circuit 14 of the test circuit 34, and the output signal of the AND gate 42 is output as an output control signal.

  That is, when the AND gate 42 of the setting detection circuit 14 of the test circuit 34 detects that the high level is set to the three test FFs 36, 38, and 40, the high level output control signal in the active state is output. Output.

  In the test circuit 34, as shown in the timing chart of FIG. 11, a high level is input as the first serial data DIN (= test serial data of the test FF 40) after reset release, and then D [n−i: 0. ] Is sequentially input, and a high level is input as n−i + 2nd serial data DIN (= serial data of FF 38 for test), and subsequently corresponds to D [n: n−i + 1]. Serial data DIN to be input is sequentially input, and high level is input as the last serial data DIN (= serial data of the test FF 36). That is, after n + 4 pieces of serial data are shifted after reset is released, writing of serial data to the shift register 12 is completed.

  When the output signals of the three FFs 36, 38, 40 for testing of the shift register 12 become high level, the output signal of the AND gate 42 of the setting detection circuit 14, that is, the output control signal becomes active high level, and output control is performed. The output signal of each FF of the shift register 12 is output from each AND gate of the circuit 16 as test parallel data D [n: 0].

  As described above, in the test circuit 34, at the time of the test, the high level is inputted as the first, n−i + 2nd and last serial data DIN after the reset release, and n + 4 serials which are three more than the conventional ones. You need to enter data. However, compared to the test circuit 24 that outputs test parallel data only when predetermined data is set in the final-stage test flip-flop, it is arranged before and after the data setting flip-flop and in an intermediate position. When predetermined data is set in the test flip-flop, the test parallel data is output, thereby preventing erroneous test data from being output due to noise and starting the test.

  Although the test circuit 34 increases the number of serial data inputs, it can be configured by adding only three FFs 36, 38, and 40 to the shift register 12 and forming only one AND gate 42 as the setting detection circuit 14. There is almost no increase in scale.

  Note that the shift register 12 of the test circuit 34 includes shift register 12 at least in two stages, the first stage FF, the first stage FF to the last stage FF, and the last stage FF. It suffices to have at least two test FFs connected in series to other FFs. In this case, the setting detection circuit 14 may output the output control signal in the active state when detecting that the serial data of the predetermined pattern is set in at least two test FFs. There are no restrictions on the number of test FFs and the arrangement position.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

10, 18, 20, 24, 28, 32, 34 Test circuit 12 Shift register 14 Setting detection circuit 16 Output control circuit 22, 42 AND gate 26, 36, 38, 40 FF
30 delay circuit

Claims (3)

A plurality of flip-flops including data setting flip-flops connected in series, and each time a clock signal is input, a shift register that sequentially shifts test serial data for testing a test object; and A setting detection circuit that outputs an output control signal in an active state upon detecting that the determined serial data of a predetermined pattern is set in at least one flip-flop of the shift register, and the setting detection An output control circuit that performs output control of the parallel data output from the plurality of data setting flip-flops of the shift register to the test target, using an output control signal input from the circuit ;
The setting detection circuit outputs the output control signal in the active state when detecting that the serial data of the predetermined pattern is set in the data setting flip-flop in the final stage of the shift register. Test circuit for semiconductor integrated circuits. A plurality of flip-flops including data setting flip-flops connected in series, and each time a clock signal is input, a shift register that sequentially shifts test serial data for testing a test object; and A setting detection circuit that outputs an output control signal in an active state upon detecting that the determined serial data of a predetermined pattern is set in at least one flip-flop of the shift register, and the setting detection An output control circuit that performs output control of the parallel data output from the plurality of data setting flip-flops of the shift register to the test target, using an output control signal input from the circuit;
The shift register further includes a test flip-flop connected to a subsequent stage of the data setting flip-flop of the final stage of the plurality of flip-flops,
Said setting detection circuit, the serial data of said predetermined pattern, detects that it is set in the flip-flop for the test, you and outputs an output control signal of the active state of the semi-conductor integrated circuit Test circuit. The setting detection circuit includes a delay circuit that delays the output control signal, and the output control circuit uses a plurality of data setting flip-flops of the shift register by using the output control signal delayed by the delay circuit. 3. The semiconductor integrated circuit test circuit according to claim 2 , wherein output control of the output signal is performed .

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