JP5935367B2 - Semiconductor integrated circuit device and electronic apparatus using the same - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device (IC) including a serial input circuit for serially inputting data, and further relates to an electronic device such as a mobile phone or a liquid crystal television using such a semiconductor integrated circuit device.

  For example, when testing a device such as a memory built in a semiconductor integrated circuit device, a serial input circuit or a serial output circuit is used to input / output data with a small number of input / output terminals.

  Generally, in a serial input circuit, a shift register for holding input serial data and a counter for detecting completion of transfer of serial data are used. The counter detects that the transfer of a series of data has been completed by counting the clock signal. However, since the circuit constituting the counter is large in scale, the synchronization between the shift register and the counter may be lost when noise occurs in the clock signal, and the serial input circuit may malfunction. .

  As a related technique, Patent Document 1 discloses a serial I / O circuit that can prevent malfunction when noise occurs in an external synchronous clock signal during serial input of data. In this serial I / O circuit, the coefficient capacity of the counter that counts the synchronous clock is made larger than the number of synchronous clocks necessary for data transfer, and it is detected that the counter has counted the number of synchronous clocks necessary for data transfer. Shift register control means for prohibiting the shift operation of the shift register, and overrun detection means for detecting whether or not the coefficient value of the counter has changed after the detection operation of the control means. Based on the detection result, an error in data transfer can be recognized.

  Patent Document 2 discloses a data interface circuit that can easily realize a data interface simply by inputting data, and can prevent malfunction of the circuit even if noise or hazard is superimposed on a clock signal. Has been. This data interface circuit reads serial data input to the data input terminal according to the clock signal input to the clock terminal, sequentially shifts it, and outputs it as parallel data to the output terminal, and a predetermined time to the data input terminal. Detection means for detecting that a fixed level signal has been input, counting means for counting the number of received data, and when a fixed level signal is detected, control is performed so that a clock signal can be input to the shift register. And a control means for controlling the input of the clock signal to be disabled when the count by the number reaches a predetermined number of data.

  On the other hand, when the counter is not used, the circuit configuration for detecting the completion of serial data transfer becomes very complicated. For example, Patent Document 3 discloses a semiconductor integrated circuit device controlled by a serial input signal pulse train. In this semiconductor integrated circuit device, a serial signal pulse train from a CPU or the like is given to a CS (chip select) input terminal, a SK (serial clock) input terminal, and a DI (data in) input terminal for each function and input. The signal is sequentially sent to the instruction shift register, the address shift register, and the data shift register via the signal control circuit. The contents sent to the instruction shift register and the contents sent to the address shift register are interpreted by the instruction decoder, then sent to the instruction control circuit, and further control the signal flow output from the input signal control circuit. To do.

Japanese Examined Patent Publication No. 4-31420 (Page 2, Fig. 1) Japanese Unexamined Patent Publication No. 2000-196464 (paragraphs 0007-0008, FIG. 1) JP-A-6-314235 (paragraphs 0001-0003, FIG. 2)

  According to some aspects of the present invention, it is possible to provide a semiconductor integrated circuit device that is less likely to malfunction by detecting completion of serial data transfer without using a counter or other complicated circuit. An electronic device using the semiconductor integrated circuit device can be provided.

  In order to solve the above problems, a semiconductor integrated circuit device according to one aspect of the present invention holds data having a first value when a control signal is inactivated, and the control signal is activated First flip-flop that holds input serial data in synchronization with the clock signal and data having a second value different from the first value when the control signal is inactivated After the control signal is activated, a plurality of serially connected flip-flops that sequentially hold the data output from the first flip-flop in synchronization with the clock signal and the control signal are activated. Later, one block worth of data having the first value held in the first flip-flop is output from the flip-flop at the last stage among the plurality of flip-flops. Comprising a transfer detection circuit for outputting a detection signal indicative of the serial data transfer completion.

  The semiconductor integrated circuit device may further include a gate circuit that stops the supply of the clock signal to the first flip-flop and the plurality of flip-flops in response to the detection signal output from the transfer detection circuit. In that case, the semiconductor integrated circuit device includes a first circuit block and a second circuit block each including a first flip-flop, a plurality of flip-flops, a transfer detection circuit, and a gate circuit, In the second circuit block, the gate circuit starts supplying the clock signal to the first flip-flop and the plurality of flip-flops in response to the detection signal output from the transfer detection circuit of the first circuit block. You may do it.

  In the above, the transfer detection circuit holds data having a second value different from the first value when the control signal is inactivated, and after the control signal is activated, the plurality of flip-flops A flip-flop that outputs a detection signal indicating completion of transfer of serial data for one block may be included by holding data output from the flip-flop at the final stage. In that case, the flip-flop of the transfer detection circuit may hold the data output from the final flip-flop among the plurality of flip-flops in synchronization with the inverted clock signal.

  The first flip-flop may be set and the plurality of flip-flops may be reset when the control signal is deactivated, or the first flip-flop may be reset when the control signal is deactivated. These flip-flops may be reset and a plurality of flip-flops may be set. Furthermore, an electronic apparatus according to an aspect of the present invention includes any one of the display control devices described above.

  According to one aspect of the present invention, since the completion of serial data transfer is detected using a plurality of flip-flops that sequentially hold serial data, a counter and other complicated circuits are not required, and the overall circuit scale is reduced. The layout area can be reduced by reducing the size. In addition, there is little risk of malfunction, and serial data can be transferred reliably.

1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention. 2 is a timing chart for explaining the operation of the semiconductor integrated circuit device shown in FIG. FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to a second embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to the first embodiment of the present invention. The semiconductor integrated circuit device is mounted on an electronic device such as a mobile phone or a liquid crystal television, and is used for storing various data.

  As shown in FIG. 1, the semiconductor integrated circuit device 1 includes a chip select circuit 10, a first circuit block (operation code latch circuit block) 20, a second circuit block (address latch circuit block) 30, and a first circuit block. 3 circuit blocks (transfer data latch circuit block) 40 and at least one device such as a memory (not shown) for storing various data.

  The chip select circuit 10 includes an inverter 11, a D flip-flop 12, a delay circuit 13, an AND circuit 14, a NAND circuit 15, and a device code match detection unit 16.

  A negative logic chip select signal CS bar that is activated to a low level when the semiconductor integrated circuit device 1 is selected is input to the inverter 11. The inverter 11 inverts the negative logic chip select signal CS bar and outputs a positive logic chip select signal CS. The chip select signal CS is supplied to the data input terminal of the D flip-flop 12, the delay circuit 13, and the first input terminal of the AND circuit 14. The output signal of the NAND circuit 15 is supplied to the second input terminal of the AND circuit 14. The output signal of the AND circuit 14 is supplied to the reset terminal of the D flip-flop 12.

  When the chip select signal CS is inactivated to the low level, the AND circuit 14 outputs a low level signal, so that the D flip-flop 12 is reset. Therefore, the serial input enable signal (hereinafter referred to as “control signal”) SEN output from the data output terminal of the D flip-flop 12 is inactivated to a low level.

  When the chip select signal CS is activated to a high level when the negative logic deselection signal SR bar output from the NAND circuit 15 is deactivated to a high level, the AND circuit 14 is a high level signal. , The reset of the D flip-flop 12 is released. On the other hand, the delay circuit 13 delays the chip select signal CS by a predetermined delay time D and supplies the delayed chip select signal CS to the clock signal input terminal of the D flip-flop 12.

  Therefore, when a predetermined delay time D elapses after the chip select signal CS is activated to the high level, the D flip-flop 12 holds the high level chip select signal CS. As a result, the control signal SEN activated to the high level is output from the data output terminal of the D flip-flop 12.

  The operation code latch circuit block 20 includes AND circuits 21 and 22, an inverter 23, and D flip-flops 24 to 28 connected in series. The control signal SEN output from the chip select circuit 10 is input to the first input terminals of the AND circuits 21 and 22. The serial data SIN is input to the second input terminal of the AND circuit 21, and the clock signal SCK is input to the second input terminal of the AND circuit 22.

  In the following, the serial data SIN input to the semiconductor integrated circuit device 1 includes operation codes CM to C0 for one block, addresses AN to A0 for one block, and transfer data DN to D0 for one block. The case where it is included will be described (M, N ≧ 2). The operation codes CM to C0 include a device code for identifying a data transfer destination device and commands representing various instructions.

  When the control signal SEN is activated to a high level, the AND circuit 21 outputs serial data SIN. The AND circuit 22 outputs the clock signal SCK while the operation code transfer detection signal (hereinafter simply referred to as “detection signal”) Cend indicating the completion of the transfer of the operation code for one block is at the low level. The inverter 23 inverts the clock signal SCK output from the AND circuit 22 and outputs an inverted clock signal.

  The serial data SIN output from the AND circuit 21 is supplied to the data input terminal of the first D flip-flop 24. The clock signal SCK output from the AND circuit 22 is supplied to the clock signal input terminals of the D flip-flops 24 to 27. On the other hand, an inverted clock signal is supplied to the clock signal input terminal of the D flip-flop 28. Further, the control signal SEN output from the chip select circuit 10 is supplied to the set terminal of the first D flip-flop 24 and the reset terminals of the D flip-flops 25 to 28.

  The first D flip-flop 24 holds data having a first value (high level “1”) when the control signal SEN is inactivated to a low level, and the control signal SEN is at a high level. After being activated, the input serial data SIN is held in synchronization with the clock signal SCK.

  The (M + 1) D flip-flops 25,..., 27 connected in series in the subsequent stage of the first D flip-flop 24 are connected to the first D flip-flop 24 when the control signal SEN is inactivated to a low level. Data having a second value different from the value (low level “0”) is held, and the data output from the first D flip-flop 24 is activated after the control signal SEN is activated to the high level. Hold sequentially in synchronization with SCK.

  The D flip-flop 28 and the inverter 23 constitute a first transfer detection circuit. The D flip-flop 28 holds data having a second value (low level “0”) different from the first value when the control signal SEN is inactivated to the low level, and the control signal SEN After the signal is activated to the high level, the data output from the final stage D flip-flop 27 out of (M + 1) D flip-flops 25,..., 27 is held in synchronization with the inverted clock signal. To do.

  As a result, after the control signal SEN is activated to the high level, the first transfer detection circuit outputs the data having the first value held in the first D flip-flop 24 from the D flip-flop 27. The detection signal Cend indicating the completion of the transfer of the operation code for one block is output from the data output terminal of the D flip-flop 28 based on the timing at which the data is output.

  The detection signal Cend is input to the third input terminal (inverted input terminal) of the AND circuit 22. The AND circuit 22 functions as a gate circuit that stops the supply of the clock signal SCK to the D flip-flops 24 to 27 in response to the detection signal Cend output from the first transfer detection circuit. Accordingly, when the detection signal Cend is activated to a high level, the clock signal SCK is not output from the AND circuit 22, and the D flip-flops 24 to 26 are stopped in a state where the operation codes C0 to CM are being output, respectively. .

  The device code match detection unit 16 of the chip select circuit 10 stores a device code assigned to a related device. The device code coincidence detection unit 16 compares the device codes included in the operation codes C0 to CM output from the D flip-flops 24 to 26 with the stored device codes. The detection signal DET is set to a high level, and when both coincide, the detection signal DET is set to a low level.

  The NAND circuit 15 outputs the high-level selection release signal SR bar in the initial stage, but when both the detection signal Cend and the detection signal DET become high level, the operation code for one block is again output. In order to input, the deselection signal SR bar is activated to a low level. Therefore, the output signal of the AND circuit 14 becomes low level, the D flip-flop 12 is reset, and the control signal SEN is once deactivated to low level. As a result, the D flip-flop 28 is also reset and the detection signal Cend is deactivated to a low level.

  On the other hand, when the device code included in the operation codes C0 to CM output from the D flip-flops 24 to 26 matches the device code stored in the device code match detection unit 16, the selection release signal The SR bar remains high. Therefore, the D flip-flop 12 is not reset, and the detection signal Cend remains activated at a high level, and then an address is input.

  The address latch circuit block 30 includes AND circuits 31 and 32, an inverter 33, and D flip-flops 34 to 38 connected in series. The detection signal Cend output from the operation code latch circuit block 20 is input to the first input terminals of the AND circuits 31 and 32 as a control signal. Further, the serial data SIN is input to the second input terminal of the AND circuit 31, and the clock signal SCK is input to the second input terminal of the AND circuit 32.

  When the detection signal Cend is activated to a high level, the AND circuit 31 outputs serial data SIN. The AND circuit 32 outputs the clock signal SCK while the address transfer detection signal (hereinafter simply referred to as “detection signal”) Aend indicating the completion of the transfer of the address for one block is at the low level.

  In the address latch circuit block 30, the AND circuit 32 supplies a clock signal to the D flip-flops 34 to 37 in response to the detection signal Cend output from the first transfer detection circuit of the operation code latch circuit block 20. Functions as a starting gate circuit. The inverter 33 inverts the clock signal SCK output from the AND circuit 32 and outputs an inverted clock signal.

  The serial data SIN output from the AND circuit 31 is supplied to the data input terminal of the first D flip-flop 34. The clock signal SCK output from the AND circuit 32 is supplied to the clock signal input terminals of the D flip-flops 34 to 37. On the other hand, an inverted clock signal is supplied to the clock signal input terminal of the D flip-flop 38. Further, the detection signal Cend output from the operation code latch circuit block 20 is supplied to the set terminal of the first D flip-flop 34 and the reset terminal of the D flip-flops 35 to 38.

  The first D flip-flop 34 holds data having a first value (high level “1”) when the detection signal Cend is inactivated to a low level, and the detection signal Cend is at a high level. After being activated, the input serial data SIN is held in synchronization with the clock signal SCK.

  The (N + 1) D flip-flops 35,..., 37 connected in series in the subsequent stage of the first D flip-flop 34 are connected to the first D flip-flop 34 when the detection signal Cend is inactivated to a low level. Data having a second value different from the value (low level “0”) is held, and after the detection signal Cend is activated to a high level, the data output from the first D flip-flop 34 is the clock signal. Hold sequentially in synchronization with SCK.

  The D flip-flop 38 and the inverter 33 constitute a second transfer detection circuit. When the detection signal Cend is inactivated to a low level, the D flip-flop 38 holds data having a second value (low level “0”) different from the first value, and the detection signal Cend. After the signal is activated to the high level, the data output from the last D flip-flop 37 among the (N + 1) D flip-flops 35, ..., 37 is held in synchronization with the inverted clock signal. To do.

  As a result, after the detection signal Cend is activated to a high level, the second transfer detection circuit outputs the data having the first value held in the first D flip-flop 34 from the D flip-flop 37. The detection signal Aend indicating completion of the transfer of the address for one block is output from the data output terminal of the D flip-flop 38 based on the timing at which the data is transferred.

  The detection signal Aend is input to the third input terminal (inverted input terminal) of the AND circuit 32. The AND circuit 32 also functions as a gate circuit that stops the supply of the clock signal SCK to the D flip-flops 34 to 37 in response to the detection signal Aend output from the second transfer detection circuit. Therefore, when the detection signal Aend is activated to a high level, the clock signal SCK is not output from the AND circuit 32, and the D flip-flops 34 to 36 are stopped in a state where the addresses A0 to AN are output, respectively. Next, transfer data is input.

  The transfer data latch circuit block 40 includes AND circuits 41 and 42, an inverter 43, and D flip-flops 44 to 48 connected in series. The detection signal Aend output from the address latch circuit block 30 is input to the first input terminals of the AND circuits 41 and 42 as a control signal. The serial data SIN is input to the second input terminal of the AND circuit 41, and the clock signal SCK is input to the second input terminal of the AND circuit 42.

  When the detection signal Aend is activated to a high level, the AND circuit 41 outputs serial data SIN. The AND circuit 42 outputs the clock signal SCK while the transfer data transfer detection signal (hereinafter simply referred to as “detection signal”) Dend indicating transfer completion of transfer data for one block is at a low level.

  In the transfer data latch circuit block 40, the AND circuit 42 supplies a clock signal to the D flip-flops 44 to 47 in response to the detection signal Aend output from the second transfer detection circuit of the address latch circuit block 30. Functions as a starting gate circuit. The inverter 43 inverts the clock signal SCK output from the AND circuit 42 and outputs an inverted clock signal.

  The serial data SIN output from the AND circuit 41 is supplied to the data input terminal of the first D flip-flop 44. The clock signal SCK output from the AND circuit 42 is supplied to the clock signal input terminals of the D flip-flops 44 to 47. On the other hand, an inverted clock signal is supplied to the clock signal input terminal of the D flip-flop 48. Further, the detection signal Aend output from the address latch circuit block 30 is supplied to the set terminal of the first D flip-flop 44 and the reset terminals of the D flip-flops 45 to 48.

  The first D flip-flop 44 holds data having a first value (high level “1”) when the detection signal Aend is inactivated to a low level, and the detection signal Aend is at a high level. After being activated, the input serial data SIN is held in synchronization with the clock signal SCK.

  (N + 1) D flip-flops 45,..., 47 connected in series in the subsequent stage of the first D flip-flop 44 are connected to the first D flip-flop 44 when the detection signal Aend is inactivated to a low level. Data having a second value (low level “0”) different from the value is held, and after the detection signal Aend is activated to a high level, the data output from the first D flip-flop 44 is converted to a clock signal. Hold sequentially in synchronization with SCK.

  The D flip-flop 48 and the inverter 43 constitute a third transfer detection circuit. When the detection signal Aend is inactivated to a low level, the D flip-flop 48 holds data having a second value (low level “0”) different from the first value, and the detection signal Aend , The data output from the last D flip-flop 47 out of (N + 1) D flip-flops 45,... 47 is held in synchronization with the inverted clock signal. To do.

  As a result, the third transfer detection circuit outputs the data having the first value held in the first D flip-flop 44 from the D flip-flop 47 after the detection signal Aend is activated to a high level. The detection signal Dend indicating completion of transfer of the transfer data for one block is output from the data output terminal of the D flip-flop 48 based on the timing at which the data is transferred.

  The detection signal Dend is input to the third input terminal (inverted input terminal) of the AND circuit 42. The AND circuit 42 also functions as a gate circuit that stops the supply of the clock signal SCK to the D flip-flops 44 to 47 in response to the detection signal Dend output from the third transfer detection circuit. Therefore, when the detection signal Dend is activated to a high level, the clock signal SCK is not output from the AND circuit 42, and the D flip-flops 44 to 46 are stopped while the transfer data D0 to DN are being output, respectively. The next operation is controlled.

Next, the operation of the semiconductor integrated circuit device shown in FIG. 1 will be described.
FIG. 2 is a timing chart for explaining the operation of the semiconductor integrated circuit device shown in FIG. First, when the negative logic chip select signal CS bar is deactivated to a high level, the D flip-flop 12 is reset and the control signal SEN is deactivated to a low level. As a result, the D flip-flop (FF) 24 is set, and high-level initial data is output from the data output terminal. On the other hand, the D flip-flops 25 to 28 are reset, and low level data is output from the data output terminal.

  When the chip select signal CS bar is activated to a low level, the reset of the D flip-flop 12 is released. When the chip select signal CS delayed by a predetermined delay time D by the delay circuit 13 is supplied to the clock signal input terminal of the D flip-flop 12, the control signal SEN activated to the high level is output from the data output terminal. The

  As a result, the serial data SIN is supplied to the data input terminal of the D flip-flop 24. The serial data SIN includes (M + 1) -bit operation codes CM to C0, (N + 1) -bit addresses AN to A0, and (N + 1) -bit transfer data DN to D0.

  The clock signal SCK is supplied to the clock signal input terminals of the D flip-flops 24-27. Accordingly, high-level initial data and operation codes CM to C0 are sequentially held in the D flip-flops 24 to 27 in synchronization with the rising edge of the pulse included in the clock signal SCK.

  In synchronization with the rising edge of the (M + 1) th pulse included in the clock signal SCK, the (M + 1) D flip-flops 24 to 26 hold the operation codes C0 to CM, respectively, and the D flip-flop (FF ) High-level initial data is output from the 27 data output terminals.

  The D flip-flop 28 holds the high-level data output from the D flip-flop 27 in synchronization with the falling edge of the (M + 1) th pulse included in the clock signal SCK, whereby the operation code A detection signal Cend indicating completion of transfer of C0 to CM is activated to a high level.

  When the detection signal Cend is inactivated to a low level, the D flip-flop 34 is set and high-level initial data is output from the data output terminal. On the other hand, the D flip-flops 35 to 38 are reset, and low level data is output from the data output terminal.

  After the detection signal Cend is activated to a high level, in synchronization with the rising edge of the (N + 1) th pulse included in the clock signal SCK, the (N + 1) D flip-flops 34 to 36 are address A0. ˜AN are held, and high-level initial data is output from the data output terminal of the D flip-flop 37.

  The D flip-flop 38 holds the high-level data output from the D flip-flop 37 in synchronization with the falling edge of the (N + 1) th pulse included in the clock signal SCK, whereby the address A0. A detection signal Aend indicating completion of transfer of .about.AN is output.

  When the detection signal Aend is inactivated to a low level, the D flip-flop 44 is set and high-level initial data is output from the data output terminal. On the other hand, the D flip-flops 45 to 48 are reset, and low level data is output from the data output terminal.

  After the detection signal Aend is activated to a high level, (N + 1) D flip-flops 44 to 46 are transferred data in synchronization with the rising edge of the (N + 1) th pulse included in the clock signal SCK. D0 to DN are held, and high-level initial data is output from the data output terminal of the D flip-flop 47.

  The D flip-flop 48 holds the high-level data output from the D flip-flop 47 in synchronization with the falling edge of the (N + 1) th pulse included in the clock signal SCK, thereby transferring the transfer data. A detection signal Dend indicating completion of transfer of D0 to DN is output.

  Thereafter, for example, according to the command included in the operation codes C0 to CM, the transfer data D0 is transferred to the storage area specified by the addresses A0 to AN in the memory specified by the device code included in the operation codes C0 to CM. ~ DN is written.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit device according to the second embodiment of the present invention. In the semiconductor integrated circuit device 1a according to the second embodiment, a plurality of D flip-flops included in the operation code latch circuit block 20a, the address latch circuit block 30a, and the transfer data latch circuit block 40a are connected. This embodiment is different from the first embodiment, and the other points are the same as those of the first embodiment.

  In the operation code latch circuit block 20a, the control signal SEN output from the chip select circuit 10 is supplied to the reset terminal of the first D flip-flop 24 and the set terminals of the D flip-flops 25 to 28.

  The first D flip-flop 24 holds data having a first value (low level “0”) when the control signal SEN is inactivated to a low level, and the control signal SEN is at a high level. After being activated, the input serial data SIN is held in synchronization with the clock signal SCK.

  The (M + 1) D flip-flops 25,..., 27 connected in series in the subsequent stage of the first D flip-flop 24 are connected to the first D flip-flop 24 when the control signal SEN is inactivated to a low level. Data having a second value (high level “1”) different from the value is held, and after the control signal SEN is activated to high level, the data output from the first D flip-flop 24 is converted to the clock signal. Hold sequentially in synchronization with SCK.

  The D flip-flop 28 and the inverter 23 constitute a first transfer detection circuit. The D flip-flop 28 holds data having a second value (high level “1”) different from the first value when the control signal SEN is inactivated to a low level, and the control signal SEN After the signal is activated to the high level, the data output from the final stage D flip-flop 27 out of (M + 1) D flip-flops 25,..., 27 is held in synchronization with the inverted clock signal. To do.

  As a result, after the control signal SEN is activated to the high level, the first transfer detection circuit outputs the data having the first value held in the first D flip-flop 24 from the D flip-flop 27. The detection signal Cend indicating completion of transfer of the operation code for one block is output from the inverted data output terminal of the D flip-flop 28 based on the timing at which the data is transferred.

  In the address latch circuit block 30a, the detection signal Cend output from the operation code latch circuit block 20a is supplied to the reset terminal of the first D flip-flop 34 and the set terminals of the D flip-flops 35 to 38. The

  The first D flip-flop 34 holds data having a first value (low level “0”) when the detection signal Cend is inactivated to a low level, and the detection signal Cend is at a high level. After being activated, the input serial data SIN is held in synchronization with the clock signal SCK.

  The (N + 1) D flip-flops 35,..., 37 connected in series in the subsequent stage of the first D flip-flop 34 are connected to the first D flip-flop 34 when the detection signal Cend is inactivated to a low level. Data having a second value (high level “1”) different from the value is held, and after the detection signal Cend is activated to the high level, the data output from the first D flip-flop 34 is changed to the clock signal. Hold sequentially in synchronization with SCK.

  The D flip-flop 38 and the inverter 33 constitute a second transfer detection circuit. The D flip-flop 38 holds data having a second value (high level “1”) different from the first value when the detection signal Cend is inactivated to a low level, and the detection signal Cend After the signal is activated to the high level, the data output from the last D flip-flop 37 among the (N + 1) D flip-flops 35, ..., 37 is held in synchronization with the inverted clock signal. To do.

  As a result, after the detection signal Cend is activated to a high level, the second transfer detection circuit outputs the data having the first value held in the first D flip-flop 34 from the D flip-flop 37. The detection signal Aend indicating completion of the transfer of the address for one block is output from the inverted data output terminal of the D flip-flop 38 based on the timing at which the data is transferred.

  Similarly, in the transfer data latch circuit block 40a, the detection signal Aend output from the address latch circuit block 30a is supplied to the reset terminal of the first D flip-flop 44 and the set terminals of the D flip-flops 45 to 48. Is done.

  The first D flip-flop 44 holds data having a first value (low level “0”) when the detection signal Aend is inactivated to a low level, and the detection signal Aend is at a high level. After being activated, the input serial data SIN is held in synchronization with the clock signal SCK.

  (N + 1) D flip-flops 45,..., 47 connected in series in the subsequent stage of the first D flip-flop 44 are connected to the first D flip-flop 44 when the detection signal Aend is inactivated to a low level. Data having a second value (high level “1”) different from the value is held, and after the detection signal Aend is activated to the high level, the data output from the first D flip-flop 44 is converted to the clock signal. Hold sequentially in synchronization with SCK.

  The D flip-flop 48 and the inverter 43 constitute a third transfer detection circuit. The D flip-flop 48 holds data having a second value (high level “1”) different from the first value when the detection signal Aend is inactivated to a low level, and the detection signal Aend , The data output from the last D flip-flop 47 out of (N + 1) D flip-flops 45,... 47 is held in synchronization with the inverted clock signal. To do.

  As a result, the third transfer detection circuit outputs the data having the first value held in the first D flip-flop 44 from the D flip-flop 47 after the detection signal Aend is activated to a high level. The detection signal Dend indicating completion of transfer of the transfer data for one block is output from the inverted data output terminal of the D flip-flop 48 based on the timing at which the data is transferred.

  According to the embodiment described above, since no counter or other complicated circuit is required to detect completion of serial data transfer, the entire circuit scale can be reduced and the layout area can be reduced. In addition, since the completion of serial data transfer is detected using a plurality of D flip-flops that sequentially hold serial data, there is little risk of malfunction and serial data can be transferred reliably.

  DESCRIPTION OF SYMBOLS 1, 1a ... Semiconductor integrated circuit device, 10 ... Chip select circuit, 11 ... Inverter, 12 ... D flip-flop, 13 ... Delay circuit, 14 ... AND circuit, 15 ... NAND circuit, 16 ... Device code coincidence detection part, 20, 20a ... Operation code latch circuit block, 21, 22 ... AND circuit, 23 ... Inverter, 24-28 ... D flip-flop, 30, 30a ... Address latch circuit block, 31, 32 ... AND circuit, 33 ... Inverter, 34-38 ... D flip-flop, 40, 40a ... Transfer data latch circuit block, 41, 42 ... AND circuit, 43 ... Inverter, 44-48 ... D flip-flop

Claims (7)

A first flip-flop that holds data having a first value when the control signal is inactivated, and holds serial data that is input in synchronization with the clock signal after the control signal is activated And
When the control signal is inactivated, data having a second value different from the first value is held, and the data output from the first flip-flop is clocked after the control signal is activated. A plurality of flip-flops connected in series that sequentially hold in synchronization with the signal;
Based on the timing at which data having the first value held in the first flip-flop is output from the final flip-flop of the plurality of flip-flops after the control signal is activated. A transfer detection circuit for outputting a detection signal indicating completion of transfer of serial data for a block; and
A gate circuit for stopping supply of a clock signal to the first flip-flop and the plurality of flip-flops in response to a detection signal output from the transfer detection circuit;
Comprising a semi conductor integrated circuit device. A first circuit block and a second circuit block each including the first flip-flop, the plurality of flip-flops, the transfer detection circuit, and the gate circuit;
In the second circuit block, the gate circuit responds to a detection signal output from the transfer detection circuit of the first circuit block, and clocks to the first flip-flop and the plurality of flip-flops Start supplying signals,
The semiconductor integrated circuit device according to claim 1.   The transfer detection circuit holds data having a second value different from the first value when the control signal is inactivated, and after the control signal is activated, the plurality of flip-flops 3. The semiconductor integrated circuit device according to claim 1, further comprising a flip-flop that outputs a detection signal indicating completion of transfer of serial data for one block by holding data output from a flip-flop at the last stage in the block .   4. The semiconductor integrated circuit device according to claim 3, wherein the flip-flop of the transfer detection circuit holds data output from a final flip-flop of the plurality of flip-flops in synchronization with an inverted clock signal. .   5. The semiconductor integrated circuit device according to claim 1, wherein when the control signal is deactivated, the first flip-flop is set and the plurality of flip-flops are reset.   5. The semiconductor integrated circuit device according to claim 1, wherein when the control signal is deactivated, the first flip-flop is reset and the plurality of flip-flops are set.   An electronic apparatus comprising the semiconductor integrated circuit device according to claim 1.

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