JP2009054916A - Noise generating circuit, semiconductor integrated circuit, and method of evaluating noise resistance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which generates noise close to such noise as generated in the semiconductor integrated circuit of a product version, when the semiconductor integrated circuit of the product version includes a digital circuit. <P>SOLUTION: The LSI is divided into a plurality of small areas, and includes noise sources (noise generating circuits) 12 in each small area. Each noise generating circuit 12 has a plurality of FFs (flip-flops) 11 in the small areas, which latch noise pattern data NDATA according to a clock signal CLK. In each noise source 12, operation/non-operation can be independently controlled by a noise enable signal EN. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a noise generation circuit and a semiconductor integrated circuit, and more particularly to a noise generation circuit that generates operation noise and a semiconductor integrated circuit having such a noise generation circuit. The present invention also relates to a noise tolerance evaluation method in a semiconductor device.

  There is a semiconductor integrated circuit (LSI) in which a digital circuit and an analog circuit are mixedly mounted. In a digital / analog mixed LSI, an operation failure or characteristic failure may occur in the analog circuit due to electrical noise generated by the digital circuit. How to suppress such operation failure or property failure? This is an important issue in developing digital / analog mixed LSI. In particular, in recent years, analog circuits have been increasingly used for high-speed interface circuits, high-speed SRAMs, PLL circuits, etc. due to high-speed and low-voltage circuits, and it is necessary to suppress malfunctions in analog circuits. Sex is thought to accelerate more and more. Under such circumstances, it is important to evaluate the noise resistance of an analog circuit against noise from peripheral logic.

As a technique for performing a noise immunity test of an analog circuit in a digital / analog mixed LSI, for example, there is one described in Patent Document 1. Patent Document 1 describes a digital noise generation circuit using a ring oscillator as a noise source, and an evaluation method using the digital noise generation circuit. In Patent Document 1, a semiconductor integrated circuit includes a plurality of ring oscillators. By arbitrarily switching the number of ring oscillators to be operated, the amount of noise is controlled quantitatively, and the noise resistance of an analog circuit is quantitatively determined. evaluate.
JP 2001-264394 A

  A problem of the technique described in Patent Document 1 is that the method of generating noise is different from the method of generating noise from a general digital circuit. That is, a general digital circuit operates based on a clock signal, but a noise waveform generated by a ring oscillator does not have a maximum / minimum point. Further, the ring oscillator constantly generates the same amount of noise, and the method of noise generation is different from the noise generated by a general digital circuit. Therefore, even if there is no problem at the time of evaluation, a characteristic defect may appear when it is actually mounted on a clock synchronous LSI.

  Also, in a digital / analog mixed LSI, the clock signal is distributed to the entire LSI by a clock tree or the like, and therefore the entire LSI operates at the same time. However, the noise generated by the ring oscillator is local and is not effective for the entire LSI. Therefore, it is conceivable that the noise arrival path to the analog circuit is completely different between the evaluation using the ring oscillator and the digital / analog mixed LSI, and correct evaluation cannot be performed.

  As described above, a noise generation circuit using a ring oscillator cannot be applied to a digital circuit using a synchronous clock. In particular, there is a situation in which a different method should be proposed for evaluation of a noise generation circuit and an analog circuit mounted on a large-scale LSI of recent high speed and exceeding 10 mm. This is because, in the method using the ring oscillator, it does not occur in the evaluation, but a situation occurs in which a problem occurs when the product version of the LSI is evaluated or actually operated on the product.

  An object of the present invention is to provide a noise generation circuit capable of generating noise close to noise generated in a product version of a semiconductor integrated circuit when the product version of the semiconductor integrated circuit includes a digital circuit. Another object of the present invention is to provide a semiconductor integrated circuit on which such a noise generating circuit is mounted, and a noise tolerance evaluation method in the semiconductor integrated circuit.

  In order to achieve the above object, a noise generating circuit according to the present invention includes a plurality of flip-flops that latch predetermined noise pattern data NDATA in synchronization with a clock signal.

  The semiconductor integrated circuit according to the present invention has a plurality of latch circuits that latch predetermined noise pattern data NDATA in synchronization with a clock signal corresponding to a plurality of small areas obtained by dividing an area in the semiconductor integrated circuit. A plurality of generation circuits are provided.

  The noise tolerance evaluation method of the present invention has a plurality of latch circuits that latch predetermined noise pattern data NDATA in synchronization with a clock signal, corresponding to a plurality of small areas obtained by dividing an area in a semiconductor integrated circuit. A noise tolerance evaluation method using a semiconductor integrated circuit including a plurality of noise generation circuits, wherein a desired noise generation circuit among the noise generation circuits corresponding to each small area is controlled to be in an operating state, and noise tolerance evaluation is performed. It is characterized by that.

  According to the noise generating circuit and the semiconductor integrated circuit of the present invention, when the product version of the semiconductor integrated circuit includes a digital circuit, noise close to the noise generated in the product version of the semiconductor integrated circuit can be generated. In the noise resistance evaluation method of the present invention, noise resistance evaluation can be performed in a state where noise close to noise generated in a product version of a semiconductor integrated circuit is generated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a semiconductor integrated circuit (LSI) including a noise generating circuit according to the first embodiment of the present invention. This LSI is a product evaluation LSI, and the size of the LSI, the arrangement of I / O buffers, and the like are the same as those of the product version of the semiconductor integrated circuit. In the LSI, the area excluding the I / O buffer area in the internal area is functionally divided into a plurality of small areas. In the example of FIG. 1, the LSI is divided into 4 × 4, and is divided into a total of 16 small areas. The semiconductor device has a noise source (noise generation circuit) 12 in each small area. In the example of FIG. 1, a total of 16 noise sources 12 (noise sources # 0 to #F) are provided. Each noise source 12 has a plurality of FFs (flip-flops) arranged evenly in a small area. Each noise source 12 can be controlled to operate / not operate independently.

  In FIG. 1, the number of divisions of the small area is 16 (4 × 4), but the number of divisions is not limited to this. Although not shown in FIG. 1, an analog circuit for evaluating noise tolerance can be arranged in an arbitrary place such as in a small area or a boundary portion between small areas. When the evaluation target is an interface circuit, the circuit is arranged in the I / O area. In addition, when the circuit block to be evaluated is large and the noise source 12 and the circuit to be evaluated cannot coexist, the noise source 12 is not disposed in some small areas, and the circuit to be evaluated is disposed at that location. Also good.

  FIG. 2 shows a circuit configuration of the semiconductor integrated circuit. Each noise source 12 receives common noise pattern data NDATA and a clock signal CLK. The clock signal CLK is a system clock distributed to the entire LSI. Each noise source 12 is individually input with noise enable signals EN0 to ENF for activating the noise source 12. Each noise source 12 controls operation / non-operation by a corresponding noise enable signal EN. The distribution method of the clock signal CLK (distribution wiring route, etc.) is considered to be as similar as possible to the product version LSI in consideration of evaluation with noise equivalent to that of the product LSI. The frequency of the clock signal CLK is also the same as that of the product version LSI.

  FIG. 3 shows the circuit configuration of each noise source. The noise source 12 includes a plurality of FFs 11 (latch circuits) and an AND circuit 13. The noise pattern data NDATA is input to the data input terminal of each FF 11. The noise pattern data NDATA is data of a predetermined pattern / random pattern input from, for example, an external input pin of the LSI. Instead of inputting the noise pattern data NDATA from the external input pin, a generator for generating a predetermined pattern / random pattern may be prepared inside the LSI and given by the generator. The total number of FFs included in the semiconductor integrated circuit (the total number of FFs included in the 16 noise sources 12) is determined by conversion from the number of FFs and the number of gates mounted on the product version LSI. In other words, the evaluation version of the LSI is equipped with as many FFs as necessary to generate noise corresponding to the noise generated in the product version of the LSI.

  The AND circuit 13 takes a logical product of the clock signal CLK and the noise enable signal EN. The result of the logical product of the clock signal CLK output from the AND circuit 13 and the noise enable signal EN is input to the clock terminal of each FF 11. When the noise source 12 is activated, the noise enable signal EN is set to “1”. When the noise enable signal EN is “1”, the clock signal CLK is input to the clock input terminal of each FF 11 via the AND circuit 13. The FF 11 takes in the noise pattern data NDATA in accordance with the clock signal CLK input via the AND circuit 13, and generates noise along the noise pattern data NDATA. That is, the noise source 12 is activated.

  When the noise source 12 is in the activated state and the noise pattern data NDATA is fixed to “0”, the FF 11 captures “0” according to the clock signal CLK. In this case, there is no data inversion in the FF 11, and the noise generated by the noise source 12 is small. The reason why the noise generated by the noise source 12 does not become zero when there is no data inversion inside the FF 11 is that there is a part in the FF 11 that distributes the clock signal CLK in the FF, and that part is synchronized with the clock signal CLK. This is because it operates. The case where the noise pattern data NDATA is fixed to “1” is the same as the case where the noise pattern data NDATA is fixed to “0”.

  When the noise source 12 is in the activated state and the noise pattern data NDATA changes between “0” and “1”, the fetch value of the FF 11 changes and data inversion occurs in the FF 11. At this time, the noise generated by the FF is larger than when no data inversion occurs. Since the noise source 12 includes a plurality of FFs 11 and the FFs 11 operate simultaneously in synchronization with the clock signal CLK, the entire circuit generates large noise in synchronization with the clock signal CLK. The amount of noise generated by the noise source 12 can be controlled by changing the supply pattern of the noise pattern data NDATA. Therefore, it is possible to increase the amount of noise per unit time generated by the noise source 12 in a certain period and to decrease the amount of noise per unit time generated by the noise source 12 in another period.

  When the noise enable signal EN is “0”, the output of the AND circuit 13 is fixed at the L level, and the supply of the clock signal CLK to the FF 11 is stopped. At this time, the FF 11 is in the operation holding state, and it can be considered that the FF 11 is not operating. That is, the noise source 12 is in a non-operating state. When the noise source 12 is in an inactive state, even if the noise pattern data NDATA changes between “0” and “1”, the noise generated by the FF 11 is small, and the noise source 12 generates almost no noise. Does not occur.

  In the semiconductor integrated circuit, as shown in FIG. 2, noise enable signals EN0 to ENF are individually input to each noise source 12, and the operation / non-operation of each noise source 12 can be individually set. In the noise tolerance test of the circuit to be evaluated, it is possible to perform a test in which all the noise sources 12 are in an operating state, and a test in which a noise source at a desired location among a total of 16 noise sources 12 is in an operating state. .

  FIG. 4 shows an example in which operation / non-operation is selected for each small area. In this example, the noise enable signals EN0 to 4, 7, 8, and B to F are set to “1”, and the noise sources # 0 to # 4, # 7, # 8, and #B to #F are 12 noises in total. The source 12 is in the operating state, and the noise enable signals EN5, 6, 9, and A are set to “0”, and the four noise sources of the noise sources # 5, # 6, # 9, and #A are set in the non-operating state. Yes. Which area of the noise source 12 in the small area is to be activated and which area of the noise source 12 is to be deactivated may be appropriately selected depending on the purpose of the evaluation.

  In the present embodiment, the noise source 12 is configured using an FF that operates in synchronization with the clock signal CLK. The FF 11 in the noise source 12 has the largest current change at the time of transition of the clock signal, and generates noise in synchronization with the clock signal. For this reason, noise synchronized with the clock signal CLK can be generated by the noise source 12. By using such a noise source 12, noise peculiar to an LSI including a digital circuit can be reproduced.

  In the present embodiment, the total number of FFs included in the noise source 12 is determined by conversion from the number of FFs and gates mounted on the product version LSI. By doing so, noise equivalent to that of the product version of the LSI can be generated in the evaluation LSI on which the noise source 12 is mounted. Therefore, the evaluation LSI can be evaluated with the noise equivalent amount of the product version of the LSI, and the noise resistance of the analog circuit or the like can be evaluated with the noise of the actual level before mounting the product.

  In the present embodiment, by using the noise enable signal EN, a small area where the noise source 12 is in an operating state and a small area where the noise source 12 is in a non-operating state can be arbitrarily set, and fine noise evaluation is possible. For example, by evaluating the circuit to be evaluated while changing the area of the noise source 12 to be operated, the relationship between the distance and direction to the noise source 12 and the noise tolerance can be examined. Such an evaluation is effective for examining the circuit mounting position in the product version of LSI.

  FIG. 5 shows a configuration of a noise generating circuit according to the second embodiment of the present invention. The noise source 12a in the present embodiment has a configuration in which an inverter 14 and a selector 15 are added to the configuration shown in FIG. The inverter 14 inverts and outputs the noise pattern data NDATA. The selector 15 outputs NDATA or a signal / NDATA obtained by inverting NDATA by the inverter 14 to each FF 11 based on the select signal SEL.

  In the present embodiment, the data captured by the FF 11 during operation can be switched between the noise pattern data NDATA and its inverted pattern data / NDATA in accordance with the select signal SEL input to the selector 15. The select signal SEL can be set individually for each small area. By doing so, it is possible to generate noise based on the noise pattern data NDATA in one noise source 12a while generating noise based on the inverted pattern data / NDATA in another noise source 12a.

  FIG. 6 shows an example in which a small area that generates noise according to the noise pattern data NDATA and a small area that generates noise according to the inverted pattern data / NDATA are combined. In this example, the noise enable signals EN0 to EN3 and C to F are set to “1”, the noise sources # 0 to # 3 and #C to #F are set to the operating state, and the noise enable signals EN4 to B are set to “0”. Noise sources # 4 to #B are in a non-operating state.

  In addition, the select signals supplied to the noise sources # 0 to # 3 and the noise sources #C to #F among the noise sources 12a in the operating state are inverted signals, and the noise sources # 0 to # 3 have noise pattern data. Noise according to NDATA is generated, and noise sources #C to #F generate noise according to the inversion pattern data / NDATA. Thus, in the present embodiment, in addition to the operation / non-operation of the noise source 12a, the inversion / non-inversion of the noise pattern data NDATA can be selected, and noise can be generated with more variations. .

  FIG. 7 shows a configuration of a noise generation circuit according to the third embodiment of the present invention. In the noise source 12b of this embodiment, the selector 17 is used so that the input data of the FF 11 can be switched between the noise pattern data NDATA and the FF 11 in the previous stage. The selector 17 inputs the noise pattern data NDATA and the output data of the previous stage FF 11. The selector 17 selects and outputs either the noise pattern data NDATA or the output data of the preceding FF 11 based on the data select signal SPSEL. Noise pattern data NDATA is input to the data input terminal of the first stage FF 11. The data selected by the selector 17 is input to the data input terminals of the second and subsequent FFs 11 via the buffer 16.

  The point that the operation / non-operation of each noise source 12b can be individually set for the plurality of noise sources 12b is the same as in the first embodiment. In this embodiment, the operation / non-operation of each noise source 12b can be selected by the noise enable signal EN, and the data input to each FF 11 constituting the noise source 12b by the data select signal SPSEL is the noise pattern data NDATA. It can be switched with the output of the FF 11 in the previous stage. Therefore, in this actual child form, noise can be generated with more variations than in the first embodiment.

  In each of the above embodiments, the clock signal CLK and the noise pattern data NDATA are set as one signal and distributed to each noise source 12. However, a plurality of these signals are prepared and distributed to each noise source. Is possible. In each of the above embodiments, the noise enable signal EN is individually input to each noise source 12. However, the present invention is not limited to this. For example, a group may be configured by several noise sources 12 and the noise enable signal EN may be input individually for each group. For example, in FIG. 6, each row may be grouped and the noise enable signal EN may be input for each row to control the operation / non-operation for each row. Although FIG. 7 shows an example in which the buffer 16 that outputs the input data without being inverted is used, the data may be inverted and output by the buffer 16. The circuit to be evaluated is not limited to an analog circuit but may be a digital circuit.

  Although the present invention has been described based on the preferred embodiments, the noise generation circuit, the semiconductor integrated circuit, and the noise tolerance evaluation method of the present invention are not limited to the above embodiments, and Those in which various modifications and changes are made from the configuration of the embodiments are also included in the scope of the present invention.

1 is a block diagram showing a semiconductor integrated circuit including a noise generating circuit according to a first embodiment of the present invention. The block diagram which shows the circuit connection in a semiconductor integrated circuit. The block diagram which shows the structure of a noise source. The block diagram which shows the example of selection of a noise generation area. The block diagram which shows the structure of the noise generation circuit of 2nd Embodiment of this invention. The block diagram which shows the example of a combination of a noise generation area and data inversion. The block diagram which shows the structure of the noise generation circuit of 3rd Embodiment of this invention.

Explanation of symbols

11: Flip-flop (latch circuit)
12: Noise source (noise generation circuit)
13: AND circuit 14: Inverter 15, 17: Selector 16: Buffer

Claims (12)

  A noise generating circuit comprising a plurality of latch circuits for latching predetermined noise pattern data NDATA in synchronization with a clock signal.   The noise generation circuit according to claim 1, wherein the latch circuit is operated when the noise enable signal indicates an operation state based on a noise enable signal for controlling an operation state / non-operation state.   In accordance with a select signal, there is further provided a selector for selecting and outputting the noise pattern data NDATA or the inverted data / NDATA of the noise pattern data NDATA, and the latch circuit includes the noise pattern data NDATA output by the selector or the inverted data / NDATA. The noise generation circuit according to claim 1 or 2, wherein   The plurality of latch circuits are connected in cascade, and a selector that selects and outputs the noise pattern data NDATA or the output data of the previous latch circuit according to the data select signal between two adjacent latch circuits in the cascade connection. 3. The noise generation circuit according to claim 1, further comprising: the latch circuit latches data corresponding to the noise pattern data NDATA output from the selector or the output data of the preceding latch circuit.   Corresponding to a plurality of small areas obtained by dividing an area in the semiconductor integrated circuit, a plurality of noise generation circuits having a plurality of latch circuits that latch predetermined noise pattern data NDATA in synchronization with a clock signal are provided. A semiconductor integrated circuit.   6. The semiconductor integrated circuit according to claim 5, wherein the noise generation circuit operates the latch circuit when the noise enable signal indicates an operation state based on a noise enable signal for controlling an operation state / non-operation state. .   The semiconductor integrated circuit according to claim 6, wherein an operation state / non-operation state of the noise generation circuit can be individually controlled in each small area by the noise enable signal.   The noise generation circuit further includes a selector that selects and outputs noise pattern data NDATA or inverted data / NDATA of the noise pattern data NDATA according to a select signal, and the latch circuit includes noise pattern data NDATA output by the selector. Alternatively, the semiconductor integrated circuit according to claim 5, wherein the inverted data / NDATA is latched.   The semiconductor integrated circuit according to claim 8, wherein the data latched by the latch circuit can be individually selected in each small area by the select signal.   In the noise generation circuit, the plurality of latch circuits are connected in cascade, and the noise generation circuit is connected between two adjacent latch circuits in the cascade connection according to a data select signal according to a data select signal. And a selector that selects and outputs the output data of the latch circuit, wherein the latch circuit latches data corresponding to the noise pattern data NDATA output by the selector or the output data of the latch circuit in the previous stage. The semiconductor integrated circuit according to any one of 5 to 7.   The semiconductor integrated circuit according to claim 10, wherein the data latched by the latch circuit can be individually selected in each small area by the data select signal. A semiconductor integrated circuit comprising a plurality of noise generating circuits having a plurality of latch circuits for latching predetermined noise pattern data NDATA in synchronization with a clock signal corresponding to a plurality of small areas obtained by dividing an area in the semiconductor integrated circuit A noise tolerance evaluation method using
A noise immunity evaluation method, wherein a noise immunity evaluation is performed by controlling a desired noise generation circuit among the noise generation circuits corresponding to each of the small areas to an operating state.

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