JP2015156549A - Drive capability control circuit and drive capability control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive capability control circuit capable of selecting the drive capability of an output buffer which is appropriately operable even under an environment where a simultaneous operation is frequently performed.

SOLUTION: A drive capability control circuit includes: a drive capability setting circuit for setting the drive capabilities of output buffers; a pattern data storage circuit for storing pattern data for allowing the output buffers to simultaneously operate; a memory control circuit for controlling to output the pattern data as write data from the output buffers with set drive capabilities, and to write the write data in a second semiconductor integrated circuit, and to read the write data written in the second semiconductor integrated circuit as read data from the second semiconductor integrated circuit; a data comparator circuit for comparing the write data with the read data, and for, when both data are coincident, storing the set drive capabilities as selection candidates; drive capability selection circuit for selecting the drive capability corresponding to a preliminarily set condition from among the drive capabilities stored as the selection candidates; and an overall control circuit for controlling the overall operation of the drive capability control circuit.

COPYRIGHT: (C)2015,JPO&INPIT

Description

  The present invention provides a semiconductor integrated circuit that controls the drivability of two or more output buffers that operate simultaneously when data is written from the semiconductor integrated circuit to the semiconductor memory, or the semiconductor memory includes The present invention relates to a driving capability control circuit and a driving capability control method for controlling the driving capability of two or more output buffers that operate simultaneously when data is read from a memory to a semiconductor integrated circuit.

  Patent Documents 1 and 2 are prior art documents relating to an apparatus for controlling the drive capability of an output buffer of a semiconductor integrated circuit.

  In Patent Document 1, the frequency of the output signal of the output buffer unit is monitored, a capability selection signal is generated according to the monitoring result, and a plurality of output circuits having different driving capabilities are appropriately selected based on the generated capability selection signal Then, by driving the input signal supplied from the semiconductor device with a predetermined driving capability by the selected output circuit, the optimum output buffer driving capability corresponding to various driving frequencies can be automatically performed by one semiconductor device. What you get is described.

  In Patent Document 2, the phase between the input and output signals of the buffer circuit is detected, a control signal for controlling the driving current of the buffer circuit is generated by a voltage corresponding to the phase difference, and the generated control signal is used. It describes that the buffer circuit is controlled so as to supply an optimum driving current to the load, that is, when the delay time between input and output becomes longer, the driving current increases, and when the delay time becomes shorter, the driving current decreases. .

JP-A-6-132807 JP-A-8-335830

  As in Patent Documents 1 and 2, in the conventional technology, the driving capability is controlled based on the operation of the output buffer alone, and the driving capability suitable for the case where a plurality of output buffers operate simultaneously is not considered. It was.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art and to select a drive capability control circuit and a drive capability control capable of selecting a drive capability of an output buffer that can operate properly even in an environment where simultaneous operations are frequently performed. It is to provide a method.

To achieve the above object, the present invention provides a first semiconductor integrated circuit comprising two or more output buffers operating simultaneously when data is written to a second semiconductor integrated circuit comprising a memory circuit. A driving capability control circuit for controlling the driving capability of
A driving capability setting circuit for setting the driving capability of the output buffer;
A pattern data holding circuit for holding pattern data for operating the output buffer simultaneously;
The pattern data is output as write data from the output buffer with the set drive capability, written to the memory circuit of the second semiconductor integrated circuit, and written to the memory circuit of the second semiconductor integrated circuit. A memory control circuit for controlling the operation of the second semiconductor integrated circuit so as to read the write data as read data from the memory circuit of the second semiconductor integrated circuit;
A data comparison circuit that compares the write data and the read data, and stores the set drive capability as a selection candidate when the write data and the read data match;
A driving capability selection circuit for selecting a driving capability corresponding to a preset condition from the stored driving capabilities of the selection candidates;
An overall control circuit for controlling the overall operation of the drive capability control circuit,
The overall control circuit changes the drive capacity of the output buffer one step from the minimum value to the maximum value of the drive capacity that can be set in the output buffer or one step from the maximum value to the minimum value. When setting, the driving ability corresponding to the preset condition is selected from the stored driving ability of the selection candidate, and the selected driving ability is controlled to be set in the output buffer. The present invention provides a drive capability control circuit characterized by the above.

According to another aspect of the present invention, there is provided a first circuit for reading data from a memory circuit of a second semiconductor integrated circuit including a memory circuit and two or more output buffers that operate simultaneously when outputting data stored in the memory circuit. In a semiconductor integrated circuit, a drive capability control circuit for controlling the drive capability of the output buffer,
The second semiconductor integrated circuit includes:
A driving capability setting circuit for setting the driving capability of the output buffer;
The first semiconductor integrated circuit includes:
A pattern data holding circuit for holding pattern data for operating the output buffer simultaneously;
Write the pattern data as write data to the memory circuit of the second semiconductor integrated circuit, and write to the memory circuit of the second semiconductor integrated circuit output from the output buffer with the set drive capability A memory control circuit for controlling the operation of the second semiconductor integrated circuit so as to read the written data as read data from the memory circuit of the second semiconductor integrated circuit;
A comparison circuit that compares the write data and the read data, and stores the set driving capability as a selection candidate when the write data and the read data match;
A driving capability selection circuit for selecting a driving capability corresponding to a preset condition from the stored driving capabilities of the selection candidates;
An overall control circuit for controlling the overall operation of the drive capability control circuit,
The overall control circuit writes the pattern data as the write data to the storage circuit of the second semiconductor integrated circuit, and sets the drive capacity of the output buffer to the minimum value of drive capacity that can be set in the output buffer. From the stored driving ability of the selection candidate, when the setting is changed by increasing one step from the maximum value to the maximum value, or decreasing by one step from the maximum value to the minimum value, it corresponds to the preset condition. A drive capability control circuit is provided that selects a drive capability and controls the selected drive capability to be set in the output buffer.

According to the present invention, in the first semiconductor integrated circuit including two or more output buffers that operate simultaneously when data is written to the second semiconductor integrated circuit including the memory circuit, the drive capability of the output buffer is controlled. A driving ability control method comprising:
A first step of setting the driving capacity of the output buffer to a minimum value or a maximum value of driving capacity settable in the output buffer;
A second step of outputting pattern data for simultaneously operating the output buffer as write data from the output buffer with the set drive capability, and writing to the storage circuit of the second semiconductor integrated circuit;
A third step of reading the write data written to the storage circuit of the second semiconductor integrated circuit as read data from the storage circuit of the second semiconductor integrated circuit;
A fourth step of comparing the write data and the read data, and storing the set drive capability as a selection candidate when the write data and the read data match;
A fifth step of determining whether or not the output buffer drive capability can be changed to one step stronger or weaker;
In the fifth step, when the driving capacity of the output buffer can be changed one step stronger or weaker, the output buffer driving ability is changed one step stronger or weaker, and the second to fifth steps are set. A sixth step that repeats the steps;
In the fifth step, when the drive capacity of the output buffer cannot be changed to one step stronger or weaker, a drive ability corresponding to a preset condition is selected from the stored drive ability of the selection candidates. A seventh step to select;
And an eighth step of setting the drive capacity of the output buffer to the selected drive capacity.

According to another aspect of the present invention, there is provided a first circuit for reading data from a memory circuit of a second semiconductor integrated circuit including a memory circuit and two or more output buffers that operate simultaneously when outputting data stored in the memory circuit. In a semiconductor integrated circuit, a drive capability control method for controlling the drive capability of the output buffer,
A first step of writing pattern data for simultaneously operating the output buffer as write data to the memory circuit of the second semiconductor integrated circuit;
A second step of setting the drive capacity of the output buffer to a minimum value or a maximum value of drive capacity settable to the output buffer;
Write data written to the memory circuit of the second semiconductor integrated circuit, which is output from the output buffer with the set drive capability, is read from the memory circuit of the second semiconductor integrated circuit as read data. The third step;
A fourth step of comparing the write data and the read data, and storing the set drive capability as a selection candidate when the write data and the read data match;
A fifth step of determining whether or not the output buffer drive capability can be changed to one step stronger or weaker;
In the fifth step, when the drive capacity of the output buffer can be changed one step stronger or weaker, the output buffer drive ability is changed one step stronger or weaker, and the third to fifth steps are set. A sixth step that repeats the steps;
In the fifth step, when the drive capacity of the output buffer cannot be changed to one step stronger or weaker, a drive ability corresponding to a preset condition is selected from the stored drive ability of the selection candidates. A seventh step to select;
And an eighth step of setting the drive capacity of the output buffer to the selected drive capacity.

According to the present invention, when the first semiconductor integrated circuit writes data to the second semiconductor integrated circuit, even if the output buffer included in the first semiconductor integrated circuit operates simultaneously, The driving capability corresponding to a preset condition can be set from among the driving capabilities of selection candidates that the semiconductor integrated circuit can correctly write data to the second semiconductor integrated circuit.
Similarly, according to the present invention, when the first semiconductor integrated circuit reads data from the second semiconductor integrated circuit, even if the output buffer included in the second semiconductor integrated circuit operates simultaneously, The driving capability corresponding to a preset condition can be set from among the driving capabilities of selection candidates from which the first semiconductor integrated circuit can correctly read data from the second semiconductor integrated circuit.

It is a circuit diagram of one embodiment showing composition of a system provided with a drive capability control circuit of the present invention. FIG. 2 is a block diagram illustrating an internal configuration of a drive capability control circuit illustrated in FIG. 1. 6 is a flowchart illustrating an example of an operation when controlling a driving capability of an output buffer included in a semiconductor integrated circuit. 6 is a flowchart illustrating an example of an operation when controlling a driving capability of an output buffer included in a semiconductor memory.

  Hereinafter, a drive capability control circuit and a drive capability control method of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

  FIG. 1 is a circuit diagram showing an embodiment of a system including a drive capability control circuit according to the present invention. FIG. 2 is a block diagram showing an internal configuration of the drive capability control circuit shown in FIG. A system 10 shown in FIG. 1 includes a semiconductor integrated circuit (first semiconductor integrated circuit of the present invention) 12 and a semiconductor memory (second semiconductor integrated circuit of the present invention) 14. The two are connected to each other by a data signal DQ, an address signal Addr, and a control signal Ctrl for controlling writing and reading of data.

  The semiconductor integrated circuit 12 writes and reads data to and from the semiconductor memory 14 via a data signal DQ composed of two or more bits, an address signal Addr, and a control signal Ctrl. Circuit: an application specific integrated circuit). The semiconductor integrated circuit 12 includes two or more input / output buffers 16 that operate simultaneously when data is written to the semiconductor memory 14, a drive capability control circuit 18, and the like.

  The semiconductor memory 14 is, for example, a DRAM (Dynamic Random Access Memory). The semiconductor memory 14 includes two or more input / output buffers 20 that operate simultaneously when outputting data read by the semiconductor integrated circuit 12, a drive capability setting circuit 36, and the like.

  The drive capability control circuit 18 controls the drive capability of the output buffer 16 a of the input / output buffer 16 included in the semiconductor integrated circuit 12 and the output buffer 20 a of the input / output buffer 20 included in the semiconductor memory 14. As shown in FIG. 2, the drive capability control circuit 18 includes a drive capability setting circuit 22, a pattern data holding circuit 24, a memory control circuit, a data comparison circuit 26, a drive capability selection circuit 28, and an overall control circuit 30. And.

The drive capability setting circuit 22 sets the drive capability of the output buffer 16a.
The drive capability setting circuit 22 can set the drive capability within a range that can be set in the output buffer 16a.
The output buffer 16a changes its drive capability by changing the drive voltage change time of its output signal (write data) in accordance with, for example, the drive capability setting signal output from the drive capability setting circuit 22. Is possible.

The pattern data holding circuit 24 outputs pattern data for simultaneously operating the output buffer 16a when data is written from the semiconductor integrated circuit 12 to the semiconductor memory 14, and output when data is read from the semiconductor memory 14 to the semiconductor integrated circuit 12. It holds at least one of pattern data for simultaneously operating the buffer 20a.
In the system 10, the data write from the semiconductor integrated circuit 12 to the semiconductor memory 14 and the data read simulation from the semiconductor memory 14 to the semiconductor integrated circuit 12 are performed to output the data over a predetermined time. Pattern data capable of maximizing the simultaneous operation noise of the buffers 16a and 20a can be created. The created pattern data is held in the pattern data holding circuit 24 in advance.
For example, when the output buffer 16a outputs 10-bit data, the pattern data includes 10-bit data called Victim (for example, Victim = 1101010001) on the side that receives noise, and an aggressor on the side that gives noise A (pseudo) random pattern consisting of 10-bit data called (Aggressor) (for example, Aggressor = 1000111000) can be used.

The memory control circuit writes the pattern data as write data from the semiconductor integrated circuit 12 to the semiconductor memory 14 and the write data written to the semiconductor memory 14 as read data from the semiconductor memory 14 to the semiconductor integrated circuit 12. The operation of the semiconductor memory 14 is controlled so as to read.
The memory control circuit includes a memory control circuit main body 32 shown in FIG. 2 and five multiplexers 34a, 34b, 34c, 34d, and 34e shown in FIG.

  Pattern data is input from the pattern data holding circuit 24 to the memory control circuit body 32. The memory control circuit main body 32 outputs pattern data as write data, and the memory control signal is a switching control signal for switching between the normal operation mode and the drive capability setting mode. Write data, pattern data, and other signals corresponding to the output control signal of the output buffer 16a, the address signal Addr, and the control signal Ctrl are output.

  The multiplexers 34a, 34b, 34c, 34d, and 34e are controlled by the memory control signal output from the memory control circuit body 32, and the signals in the normal operation mode of the semiconductor integrated circuit 12 and the output buffer 16a corresponding to these signals. It switches between signals in the drive capacity setting mode. The multiplexers 34a, 34b, 34c, 34d, and 34e are provided on the signal lines of the write data of the output buffer 16a, the output control signal and its inverted signal, the address signal Addr that controls the operation of the semiconductor memory 14, and the control signal Ctrl, respectively. ing.

  For example, write data in the normal operation mode is input from one internal terminal of the semiconductor integrated circuit 12 (not shown) to one input terminal of the multiplexer 34a provided in the signal line for the write data, and the other input terminal is connected to the other input terminal. The pattern data in the drive capacity setting mode is input from the memory control circuit body 32, and the switching control signal is input from the memory control circuit body 32 to the control input terminal. The output signal of the multiplexer 34a is input to a data input terminal of an FF (flip flop) 38 provided immediately before the output buffer 16a. The same applies to the other multiplexers 34b, 34c, 34d, and 34e.

  The multiplexers 34a, 34b, 34c, 34d, and 34e output the signals in the normal operation mode in the normal operation mode and the signals in the drive capacity setting mode in the drive capability setting mode according to the switching control signal. Is output. Therefore, the drive capability control circuit 18 switches the operation mode of the semiconductor integrated circuit 12 from the normal operation mode to the drive capability setting mode, so that the write data of the output buffer 16a, the output control signal of the output buffer 16a and its inverted signal, The address signal Addr and the control signal Ctrl can be controlled.

  Subsequently, the data comparison circuit 26 compares the write data and the read data, and stores the drive capability set by the drive capability setting circuit 22 as a selection candidate when they match.

The drive capability selection circuit 28 selects a drive capability corresponding to a preset condition from the drive capabilities of the selection candidates stored by the data comparison circuit 26.
Which driving ability is selected from among the driving ability of selection candidates can be set in advance according to the purpose given priority by the user. For example, when there is a concern about malfunction due to power consumption or overshoot / undershoot, it is possible to set so that the minimum one of the selection candidate driving capabilities is selected. Further, depending on the purpose, it may be set so that the middle driving ability among the driving ability of the selection candidates is selected or the largest one is selected.
That is, the preset condition is a condition for setting the driving ability selected according to the purpose given priority by the user as described above. As a preset condition, for example, when it is set to select the smallest driving ability of the selection candidates, the driving ability selection circuit 28 selects the smallest driving ability of the selection candidates. To do.

  The overall control circuit 30 performs overall operations of the drive capability control circuit 18, that is, operations of the drive capability setting circuits 22, 36, the pattern data holding circuit 24, the memory control circuit, the data comparison circuit 26, the drive capability selection circuit 28, and the like. It is something to control.

The drive capability setting circuit 36 provided in the semiconductor memory 14 sets the drive capability of the output buffer 20a provided in the semiconductor memory 14.
The drive capability setting circuit 36 has the same function as the drive capability setting circuit 22. Under the control of the overall control circuit 30, the memory control circuit writes the setting data of the driving capability of the output buffer 20a into the register from the driving capability setting circuit 36 by writing the setting data of the output buffer 20a into the register or the like provided in the semiconductor memory 14, for example. A driving capability setting signal corresponding to the driving capability setting data is output, and the driving capability of the output buffer 20a can be changed according to the driving capability setting signal.

  Next, the operation when the drive capability control circuit 18 controls the drive capability of the output buffer 16a of the semiconductor integrated circuit 12 will be described with reference to the flowchart shown in FIG.

  First, under the control of the overall control circuit 30, the drive capability setting circuit 22 sets, for example, the drive capability of the output buffer 16a to a minimum value (step S1).

  Subsequently, under the control of the overall control circuit 30, the memory control circuit sequentially uses the pattern data held in the pattern data holding circuit 24 as write data from the output buffer 16a with the driving ability set by the driving ability setting circuit 22. Output and write to the semiconductor memory 14 (step S2).

  In this case, it is desirable to perform burst write rather than single write so that simultaneous operation noise is maximized. Therefore, when writing write data to the semiconductor memory 14, depending on the drive capability of the output buffer 16a set by the drive capability setting circuit 22, there is a possibility that correct write data cannot be written.

  Subsequently, under the control of the overall control circuit 30, the memory control circuit sequentially reads the write data written to the semiconductor memory 14 from the semiconductor memory 14 as read data (step S3).

In this case, the driving capability of the output buffer 20a of the semiconductor memory 14 is temporarily set to a driving capability that can reliably output correct read data from the semiconductor memory 14, for example, its maximum value. The driving capability that can reliably output correct read data from the semiconductor memory 14 can be obtained by simulation, for example.
In addition, it is desirable to perform single reading instead of burst reading so that the influence of simultaneous operation noise during reading is reduced and the semiconductor integrated circuit 12 can reliably read correct read data from the semiconductor memory 14.

  Subsequently, under the control of the overall control circuit 30, the data comparison circuit 26 compares the write data with the read data (step S4).

Here, when the write data and the read data match (“Y” in step S5), the data comparison circuit 26 stores the drive capability of the output buffer 16a set by the drive capability setting circuit 22 as a selection candidate ( Step S6).
On the other hand, if the two do not match (“N” in step S5), the process proceeds to the next step S7.

  Subsequently, the overall control circuit 30 determines whether or not the drive capability of the output buffer 16a can be changed by one step and set (step S7).

  Here, when the driving capability of the output buffer 16a can be changed and set strongly by one step (“Y” in step S7), the driving capability setting circuit 22 controls the output buffer 16a under the control of the overall control circuit 30. The driving ability is changed by one step and set (step S8), and the process returns to step S2 to repeat the above operation.

On the other hand, if the driving capability of the output buffer 16a cannot be changed by one step and set (“N” in step S7), the driving capability selection circuit 28 controls the data comparison circuit 26 under the control of the overall control circuit 30. A driving ability corresponding to a preset condition is selected from the stored driving ability of the selection candidates (step S9).
If the drive capability selection circuit 28 is set to select the minimum one of the drive capabilities of the selection candidates as a preset condition, for example, to reduce power consumption and EMI risk, Accordingly, the minimum driving capability is selected from the selection candidates.

  Finally, under the control of the overall control circuit 30, the driving capability setting circuit 22 sets the driving capability of the output buffer 16a to the minimum driving capability selected from the driving capabilities of the selection candidates (step S10).

  As described above, in the drive capability control circuit 18, even when the output buffer 16 a included in the semiconductor integrated circuit 12 operates simultaneously when the semiconductor integrated circuit 12 writes data to the semiconductor memory 14, the semiconductor integrated circuit 12. Can be set to a drive capacity corresponding to a preset condition, for example, a minimum drive capacity, from among the drive powers of selection candidates that can correctly write data to the semiconductor memory 14.

  Next, the operation when the drive capability control circuit 18 controls the drive capability of the output buffer 20a of the semiconductor memory 14 will be described with reference to the flowchart shown in FIG.

  First, under the control of the overall control circuit 30, the memory control circuit writes the pattern data held in the pattern data holding circuit 24 to the semiconductor memory 14 as write data (step S11).

In this case, the drive capability of the output buffer 16a of the semiconductor integrated circuit 12 is provisionally set to a drive capability that can reliably output correct write data to the semiconductor memory 14, for example, its maximum value. The driving capability that can reliably output correct write data to the semiconductor memory 14 can be obtained by simulation, for example.
In addition, it is desirable to perform single write instead of burst write so that the influence of simultaneous operation noise during writing is reduced and the semiconductor integrated circuit 12 can reliably write correct write data to the semiconductor memory 14.

  Subsequently, under the control of the overall control circuit 30, the drive capability setting circuit 36 sets, for example, the drive capability of the output buffer 20a to a minimum value (step S12).

  Subsequently, under the control of the overall control circuit 30, the memory control circuit outputs the write data output from the output buffer 20 a with the driving capability set by the driving capability setting circuit 36 and written to the semiconductor memory 14 as read data. Then, the semiconductor memory 14 is sequentially read (step S13).

  In this case, it is preferable to perform burst reading rather than single reading so that simultaneous operation noise is maximized. Therefore, when reading the read data from the semiconductor memory 14, depending on the drive capability of the output buffer 20a set by the drive capability setting circuit 36, correct read data may not be read.

  Subsequently, under the control of the overall control circuit 30, the data comparison circuit 26 compares the write data with the read data (step S14).

Here, when the write data and the read data match (“Y” in step S15), the data comparison circuit 26 stores the drive capability of the output buffer 20a set by the drive capability setting circuit 36 as a selection candidate ( Step S16).
On the other hand, if the two do not match (“N” in step S15), the process proceeds to the next step S17.

  Subsequently, the overall control circuit 30 determines whether or not the driving capability of the output buffer 20a can be changed by one step and set (step S17).

  Here, when the drive capacity of the output buffer 20a can be changed and set strongly by one step (“Y” in step S17), the drive capacity setting circuit 36 controls the output buffer 20a under the control of the overall control circuit 30. The driving ability is changed by one step and set (step S18), and the process returns to step S13 to repeat the above operation.

On the other hand, if the drive capability of the output buffer 20a cannot be changed by one step and set (“N” in step S17), the drive capability selection circuit 28 controls the data comparison circuit 26 under the control of the overall control circuit 30. A driving capability corresponding to a preset condition is selected from the stored driving capabilities of the selection candidates (step S19).
If the drive capability selection circuit 28 is set as a preset condition, for example, to select the minimum drive capability from among the selection candidate drive capabilities in order to reduce power consumption and EMI risk, Accordingly, the minimum driving capability is selected from the selection candidates.

  Finally, under the control of the overall control circuit 30, the drive capability setting circuit 36 sets the drive capability of the output buffer 20a to the minimum drive capability selected from the selection candidate drive capabilities (step S20).

  As described above, in the drive capability control circuit 18, when the semiconductor integrated circuit 12 reads data from the semiconductor memory 14, even if the output buffer 20 a included in the semiconductor memory 14 operates simultaneously, the semiconductor integrated circuit 12 From the driving ability of selection candidates that can read data from the semiconductor memory 14 correctly, the driving ability corresponding to the preset condition, for example, the minimum driving ability can be set.

The present invention is not limited to the semiconductor memory 14 as the second semiconductor integrated circuit. Various semiconductor integrated circuits including a memory circuit that stores data written from the semiconductor integrated circuit 12 and outputs read data. It is possible to apply to.
Further, the drive capability setting circuits 22 and 36 repeatedly set the drive capability of the output buffers 16a and 20a to the maximum value first, and then change and set the drive capability weakly one step at a time. Also good.

The present invention is basically as described above.
Although the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and it is needless to say that various improvements and modifications may be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 10 System 12 Semiconductor integrated circuit 14 Semiconductor memory 16, 20 Input / output buffer 16a, 20a Output buffer 18 Drive capability control circuit 22, 36 Drive capability setting circuit 24 Pattern data holding circuit 26 Data comparison circuit 28 Drive capability selection circuit 30 Overall control circuit 32 Memory control circuit body 34a, 34b, 34c, 34d, 34e Multiplexer 38 Flip-flop

Claims (4)

A drive capability control circuit for controlling the drive capability of the output buffer in the first semiconductor integrated circuit including two or more output buffers that operate simultaneously when data is written to a second semiconductor integrated circuit including a memory circuit. And
A driving capability setting circuit for setting the driving capability of the output buffer;
A pattern data holding circuit for holding pattern data for operating the output buffer simultaneously;
The pattern data is output as write data from the output buffer with the set drive capability, written to the memory circuit of the second semiconductor integrated circuit, and written to the memory circuit of the second semiconductor integrated circuit. A memory control circuit for controlling the operation of the second semiconductor integrated circuit so as to read the write data as read data from the memory circuit of the second semiconductor integrated circuit;
A data comparison circuit that compares the write data and the read data, and stores the set drive capability as a selection candidate when the write data and the read data match;
A driving capability selection circuit for selecting a driving capability corresponding to a preset condition from the stored driving capabilities of the selection candidates;
An overall control circuit for controlling the overall operation of the drive capability control circuit,
The overall control circuit changes the drive capacity of the output buffer one step from the minimum value to the maximum value of the drive capacity that can be set in the output buffer or one step from the maximum value to the minimum value. When setting, the driving ability corresponding to the preset condition is selected from the stored driving ability of the selection candidate, and the selected driving ability is controlled to be set in the output buffer. A drive capability control circuit characterized by the above. In the first semiconductor integrated circuit that reads the data from the storage circuit of the second semiconductor integrated circuit that includes a storage circuit and two or more output buffers that operate simultaneously when outputting the data stored in the storage circuit, A drive capability control circuit for controlling the drive capability of the output buffer,
The second semiconductor integrated circuit includes:
A driving capability setting circuit for setting the driving capability of the output buffer;
The first semiconductor integrated circuit includes:
A pattern data holding circuit for holding pattern data for operating the output buffer simultaneously;
Write the pattern data as write data to the memory circuit of the second semiconductor integrated circuit, and write to the memory circuit of the second semiconductor integrated circuit output from the output buffer with the set drive capability A memory control circuit for controlling the operation of the second semiconductor integrated circuit so as to read the written data as read data from the memory circuit of the second semiconductor integrated circuit;
A comparison circuit that compares the write data and the read data, and stores the set driving capability as a selection candidate when the write data and the read data match;
A driving capability selection circuit for selecting a driving capability corresponding to a preset condition from the stored driving capabilities of the selection candidates;
An overall control circuit for controlling the overall operation of the drive capability control circuit,
The overall control circuit writes the pattern data as the write data to the storage circuit of the second semiconductor integrated circuit, and sets the drive capacity of the output buffer to the minimum value of drive capacity that can be set in the output buffer. From the stored driving ability of the selection candidate, when the setting is changed by increasing one step from the maximum value to the maximum value, or decreasing by one step from the maximum value to the minimum value, it corresponds to the preset condition. A drive capability control circuit that selects a drive capability and controls the selected drive capability to be set in the output buffer. A drive capability control method for controlling the drive capability of an output buffer in a first semiconductor integrated circuit including two or more output buffers that operate simultaneously when data is written to a second semiconductor integrated circuit including a memory circuit. And
A first step of setting the driving capacity of the output buffer to a minimum value or a maximum value of driving capacity settable in the output buffer;
A second step of outputting pattern data for simultaneously operating the output buffer as write data from the output buffer with the set drive capability, and writing to the storage circuit of the second semiconductor integrated circuit;
A third step of reading the write data written to the storage circuit of the second semiconductor integrated circuit as read data from the storage circuit of the second semiconductor integrated circuit;
A fourth step of comparing the write data and the read data, and storing the set drive capability as a selection candidate when the write data and the read data match;
A fifth step of determining whether or not the output buffer drive capability can be changed to one step stronger or weaker;
In the fifth step, when the driving capacity of the output buffer can be changed one step stronger or weaker, the output buffer driving ability is changed one step stronger or weaker, and the second to fifth steps are set. A sixth step that repeats the steps;
In the fifth step, when the drive capacity of the output buffer cannot be changed to one step stronger or weaker, a drive ability corresponding to a preset condition is selected from the stored drive ability of the selection candidates. A seventh step to select;
And an eighth step of setting the drive capacity of the output buffer to the selected drive capacity. In the first semiconductor integrated circuit that reads the data from the storage circuit of the second semiconductor integrated circuit that includes a storage circuit and two or more output buffers that operate simultaneously when outputting the data stored in the storage circuit, A driving capability control method for controlling the driving capability of an output buffer,
A first step of writing pattern data for simultaneously operating the output buffer as write data to the memory circuit of the second semiconductor integrated circuit;
A second step of setting the drive capacity of the output buffer to a minimum value or a maximum value of drive capacity settable to the output buffer;
Write data written to the memory circuit of the second semiconductor integrated circuit, which is output from the output buffer with the set drive capability, is read from the memory circuit of the second semiconductor integrated circuit as read data. The third step;
A fourth step of comparing the write data and the read data, and storing the set drive capability as a selection candidate when the write data and the read data match;
A fifth step of determining whether or not the output buffer drive capability can be changed to one step stronger or weaker;
In the fifth step, when the drive capacity of the output buffer can be changed one step stronger or weaker, the output buffer drive ability is changed one step stronger or weaker, and the third to fifth steps are set. A sixth step that repeats the steps;
In the fifth step, when the drive capacity of the output buffer cannot be changed to one step stronger or weaker, a drive ability corresponding to a preset condition is selected from the stored drive ability of the selection candidates. A seventh step to select;
And an eighth step of setting the drive capacity of the output buffer to the selected drive capacity.

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