JP2011112894A - Level conversion circuit, electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level conversion circuit which is further reduced in a circuit scale. <P>SOLUTION: The level conversion circuit 300 includes a control section 210 to output a result of a first logic operation; a control section 220 to output a result of a second logic operation; a control section 230 to output a result of a third logic operation; a TFT 241 to supply a first voltage to a data line; a TFT 242 to supply a second voltage to a data line; and a TFT 243 to supply a third voltage to a dataline. Each of the TFT 241, the TFT 242, and the TFT 243 is composed of a transistor having a single conduction type channel. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a level conversion circuit in an electro-optical device.

In an electro-optical device using a liquid crystal or the like, there is a problem that so-called image sticking occurs when a voltage having the same polarity is continuously applied. As one method for preventing image sticking, a method of alternately applying positive and negative voltages to a liquid crystal is known. In this method, a total of three voltages are required: a voltage for writing “1” to the pixel, two voltages of positive and negative polarity, and a voltage for writing “0” to the pixel. As a level conversion circuit for generating these three voltages, for example, the one described in Patent Document 1 is known.

JP 2001-343939 A

In the level conversion circuit described in Patent Document 1, a p-channel transistor and n
A transfer gate combined with a channel transistor has been used as a switching element.
On the other hand, an object of the present invention is to provide a level conversion circuit with a further reduced circuit scale.

The present invention provides a first input terminal to which a first polarity signal is input, a second input terminal to which a binary image data signal is input, a value indicated by the first polarity signal, and the image data signal. A first control unit having a first output terminal for outputting a result of a first logical operation including a negative logical product of the indicated values, and a second in which the polarity is inverted at a timing different from that of the first polarity signal A third input terminal to which a polarity signal is input, a fourth input terminal to which the image data signal is input, a value indicated by the second polarity signal, and a negative logical product of values indicated by the image data signal. A second control unit having a second output terminal for outputting a result of the logical operation of 2, a fifth input terminal to which the image data signal is input, and a third including a negation of a value indicated by the image data And a third output terminal for outputting the result of the logical operation of 3, a first voltage is supplied to one end, the other end is connected to the data line, a control terminal is connected to the first output terminal, and the negative logical product in the first logical operation is When the result is a first value, a first switching element that supplies the first voltage to the data line, a second voltage different from the first voltage is supplied to one end, and the other end is the data And the control terminal is connected to the second output terminal, and the second voltage is applied to the data line when the result of the negative logical product in the second logical operation is the first value. A second switching element to be supplied, the first voltage and a third voltage different from the second voltage are supplied to one end, the other end is connected to the data line, and a control terminal is the third output Connected to the terminal and the negation in the third logic operation And a third switching element for supplying the third voltage to the data line when the result is a second value different from the first value, the first switching element, the second switching Each of the element and the third switching element includes a transistor having a single conductivity type channel, and provides a level conversion circuit.
According to this level conversion circuit, the circuit scale can be reduced as compared with the case where a transfer gate is used as a switching element.

Further, the present invention provides a first input terminal to which a polarity signal is input, a second input terminal to which a binary image data signal is input, a value indicated by the polarity signal, and negation of a value indicated by the image data signal. A first control unit having a first output terminal for outputting a result of a first logical operation including a logical product; a third input terminal to which an inverted signal obtained by inverting the polarity signal; and the image data A fourth input terminal to which a signal is input and a second output terminal for outputting a result of a second logical operation including a negative logical product of a value indicated by the inverted signal and a value indicated by the image data signal. And a third output terminal that outputs a result of a third logical operation including negation of a value indicated by the image data, and a fifth input terminal to which the image data signal is input. The first voltage is supplied to one end and the other end Connected to the data line, the control terminal is connected to the first output terminal, and the first voltage is applied to the data line when the result of the negative logical product in the first logical operation is a first value. A first switching element to be supplied; a second voltage different from the first voltage is supplied to one end; the other end is connected to the data line; a control terminal is connected to the second output terminal; A second switching element for supplying the second voltage to the data line when the result of the negative logical product in the second logical operation is the first value; and the first voltage and the first at one end. A third voltage different from the second voltage is supplied, the other end is connected to the data line, a control terminal is connected to the third output terminal, and the negative result in the third logic operation is the first result In the case of a second value different from the value of 1 A third switching element for supplying the data line to the data line, wherein each of the first switching element, the second switching element, and the third switching element is a single conduction type channel. There is provided a level conversion circuit comprising a transistor having the following.
According to this level conversion circuit, the circuit scale can be reduced as compared with the case where a transfer gate is used as a switching element.

In a preferred embodiment, the level conversion circuit includes a sixth input terminal to which a third polarity signal is input, the first polarity signal generated from the third polarity signal, and the second polarity signal. A polarity signal generation circuit having a fourth output terminal and a fifth output terminal for outputting, wherein the fourth output terminal and the first input terminal are connected, and the fifth output terminal and the first output terminal are connected; 2
Input terminals may be connected.
According to this level conversion circuit, a short circuit can be suppressed.

In another preferable aspect, among the first switching element, the second switching element, and the third switching element, a maximum voltage among the first voltage, the second voltage, and the third voltage. The conduction type of the channel of the switching element for selecting is p-type, and the conduction type of the channel of the switching element for selecting the lowest voltage may be n-type.
According to this level conversion circuit, the circuit scale can be reduced as compared with the case where all the switching elements have the same conduction type.

In still another preferred aspect, each transistor of the switching element, the second switching element, and the third switching element has the first output terminal, the second switching element when the transistor is turned on. The smaller the difference between the voltage applied from the output terminal and the third output terminal and the first voltage, the second voltage, and the third voltage, the larger the channel width may be. .
According to this level conversion circuit, the circuit scale can be reduced as compared with the case where all the switching elements have the same channel width.

In still another preferred aspect, the level conversion circuit may be formed on the same substrate as an electro-optical element that performs display according to a voltage applied to the data line.
According to the level conversion circuit, the size of the entire apparatus can be further reduced as compared with the case where the electro-optical element is configured separately.

In addition, the present invention provides an electro-optical device that includes the level conversion circuit and an electro-optical element that performs display in accordance with a voltage applied to the data line.
Furthermore, the present invention provides an electronic apparatus that includes the electro-optical device described above and a control unit that supplies image data to the electro-optical device.

1 is a block diagram illustrating an overall configuration of an electro-optical device 1 according to an embodiment. 4 is a diagram showing details of a data line driving circuit 140. FIG. 2 is a diagram illustrating a configuration of a level conversion circuit 200. FIG. 2 shows a truth table of first, second and third logical operations. 3 is a timing chart showing the operation of the electro-optical device 1. It is a figure which shows the structure of the level conversion circuit 300 which concerns on 2nd Embodiment. 3 is a diagram illustrating a configuration of a polarity signal generation circuit 310. FIG. 3 is a diagram schematically showing a signal generated by a polarity signal generation circuit 310. FIG. It is a figure explaining the possibility of a short circuit of a circuit by signal delay. FIG. 10 illustrates a projector 2100 according to Modification 3.

1. First embodiment 1-1. Configuration FIG. 1 is a block diagram showing an overall configuration of an electro-optical device 1 according to an embodiment of the present invention. In this example, the electro-optical device 1 is a liquid crystal display element using a liquid crystal element as an electro-optical element. The electro-optical device 1 includes a control circuit 10, a liquid crystal panel 100, a scanning line driving circuit 130, and a data line driving circuit 140.
The control circuit 10 is a circuit that controls the liquid crystal panel 100. In this example, the control circuit 10 outputs a data signal Vx, a control signal Xctr, a control signal Yctr, and a polarity signal Fp based on the video signal Vid-in and the synchronization signal Sync. The data signal Vx is binary (
The image (video) data converted into 0 and 1) is shown. Control signal Xctr and control signal Yc
tr is used to control the data line driving circuit 140 and the scanning line driving circuit 130, respectively.

The liquid crystal panel 100 is a device that displays an image under the control of the control circuit 10. The liquid crystal panel 100 includes an element substrate 100a, a counter substrate 100b, and a liquid crystal layer 105. The element substrate 100a and the counter substrate 100b are bonded to each other while maintaining a certain gap. On the surface of the element substrate 100a facing the counter substrate 100b, m rows (m is an integer of 2 or more) scanning lines 112 and n columns (n is an integer of 2 or more) data lines 114 are provided. Scan line 1
12 and the data line 114 are insulated from each other. In order to distinguish the scanning lines 112, they are referred to as scanning lines 112 in order from the top in FIG. Similarly, when distinguishing each data line 114, 1, 2, 3,... In order from the left in FIG.
(N-1), referred to as the nth column data line 114.

In the element substrate 100a, the scanning lines 112 and the data lines 114 are provided along the X direction and the Y direction in FIG. 1, respectively. When viewed from a direction perpendicular to the X direction and the Y direction, the scanning line 112 and the data line 114 intersect each other. Corresponding to this intersection, TFT (
A set of a thin film transistor 116 and a pixel electrode 118 is provided. Pixel electrode 11
8 has a rectangular shape and is made of a transparent material. In this example, the TFT 116
Is an n-channel field effect transistor. The gate electrode of the TFT 116 is connected to the scanning line 112, the source electrode is connected to the data line 114, and the drain electrode is the pixel electrode 1.
18 is connected.

A common electrode 108 is provided over the entire surface of the counter substrate 100b facing the element substrate 100a. The common electrode 108 has transparency. A voltage LCom is applied to the common electrode 108 by a circuit not shown.

The scanning line driving circuit 130 is a circuit that supplies scanning signals Y 1, Y 2, Y 3,. The scanning signals Y1, Y2, Y3,..., Ym are signals that are H (high) level in a line sequential manner in a pulse manner. For example, when an H level scanning signal is supplied to the first scanning line 112, the TFT 116 connected to the first scanning line 112 is turned on. At this time, a voltage corresponding to image data is written to the pixel electrode 118 in the first column by the data signal supplied to the data line 114. The alignment state of the liquid crystal molecules in the liquid crystal layer 105 (that is, the transmittance of the liquid crystal layer 105) is changed by an electric field generated between the pixel electrode 118 and the common electrode. Thereby, gradation display by light modulation becomes possible.
In FIG. 1, since the facing surface of the element substrate 100a is the back side of the drawing, the scanning lines 112, the data lines 114, the TFTs 116, and the pixel electrodes 118 provided on the facing surface should be indicated by broken lines. Since it becomes difficult, each is shown by a solid line.

FIG. 2 is a diagram showing details of the data line driving circuit 140. The data line driving circuit 140 is
This is a circuit for supplying data signals X1, X2, X3,. The data line driving circuit 140 includes a shift register 141, a data supply line L, and switches SW1 to SW.
n, a latch 142, a latch 143, and a level conversion circuit 200. In this example
The data line driving circuit 140 is formed on the element substrate 100a using so-called SOG (System On Glass) technology.

The shift register 141 receives the sampling pulse S according to the signal from the control circuit 10.
R1, SR2, SR3,..., SRn are sequentially generated. The data supply line L is connected to the latch 142 via the switch SW. A sampling pulse SR is supplied to the control input terminal of the switch SW. With this configuration, the sampling pulses SR1, SR2, SR3
,..., SRn, the image data signal Vx is supplied to the latch 142 in synchronization with each other. The latch 142 latches the image data signal Vx input via the switch SW, and obtains dot sequential image data d1 to dn. Image data d <b> 1 to dn obtained by the latch 142 are input to the latch 143. The latch 143 latches the image data d1 to dn, and obtains line sequential image data D1 to Dn. The level conversion circuit 200 includes two voltages (VHigh and VLow, examples of the first voltage and the second voltage) corresponding to the image data “1”, and a voltage (VMid, third) corresponding to the image data “0”. From a total of three voltages with an example of the voltage of
A signal having a voltage selected based on the image data D1 to Dn and the polarity signal Fp is supplied to the data line 114 as the data signals X1 to Xn.

FIG. 3 is a diagram illustrating the configuration of the level conversion circuit 200. FIG. 3 shows a conversion unit Uk for outputting the data signal Xk to the kth data line. k is 1 ≦
It is an integer that satisfies k ≦ n. The level conversion circuit 200 has n conversion units,
Each conversion unit has the same configuration. Here, the conversion unit Uk will be described as an example. The level conversion circuit 200 includes a control unit 210 (an example of a first control unit) and a control unit 220 (second
3), a control unit 230 (an example of a third control unit), and a selection unit 240. The controller 210 controls the timing for selecting the voltage VHigh. The controller 220 controls the timing for selecting the voltage VLow. The controller 230 controls the timing for selecting the voltage VMid. The selection unit 240 includes the control unit 210 and the control unit 2.
20 and the voltages VHigh, VLow, and VMid according to signals from the control unit 230
Is supplied to the data line 114.

The control unit 210 includes an input terminal 211 (an example of a first input terminal), an input terminal 212 (an example of a second input terminal), and an output terminal 213 (an example of a first output terminal). Input terminal 2
11, a polarity signal Fp (an example of a first polarity signal) is input. The input terminal 212 has
An image data signal Vx is input. The control unit 210 includes a circuit that performs a logical operation (hereinafter referred to as “first logical operation”) using the polarity signal Fp and the image data signal Vx. The first logical operation is a negative logical product (NA) of the value indicated by the polarity signal Fp and the value indicated by the image data signal Vx.
ND). In this example, the first logical operation includes a negative logical product of Fp and Vx and a negative result (NOT) of the result of the negative logical product. The output terminal 213 outputs the result of the first logical operation.

The control unit 220 includes an input terminal 221 (an example of a third input terminal), an input terminal 222 (an example of a fourth input terminal), and an output terminal 223 (an example of a second output terminal). Input terminal 2
A NOT circuit 250 is provided between the signal line 21 and the signal line of the polarity signal Fp. Input terminal 2
An inverted signal of the polarity signal Fp is input to 21. An image data signal Vx is input to the input terminal 222. The control unit 220 generates an inverted signal of the polarity signal Fp and the image data signal Vx.
And a circuit for performing a logical operation using the above (hereinafter referred to as “second logical operation”). The second logical operation includes a negative logical product of the value indicated by the inverted signal and the value indicated by the image data signal Vx. In this example, the second logical operation includes an inverted signal of Fp, a negative logical product (NAND) of Vx, and a negative result (NOT) of the negative logical product. The output terminal 223 outputs the result of the second logical operation.

The control unit 230 includes an input terminal 232 (an example of a fifth input terminal) and an output terminal 233 (an example of a third output terminal). An image data signal Vx is input to the input terminal 232. The control unit 220 includes a circuit that performs a logical operation (hereinafter referred to as “third logical operation”) using the image data signal Vx. The third logical operation includes negation of the value indicated by the image data signal Vx. In this example, the third logical operation consists of negation of Vx (NOT). Output terminal 233
Outputs the result of the third logical operation.

The selection unit 240 includes three switching elements, a TFT 241 (an example of a first switching element), a TFT 242 (an example of a second switching element), and a TFT 243 (an example of a third switching element). In this example, TFT 241, TFT 242, and TFT
Reference numeral 243 denotes a field effect transistor having a single conductivity type channel (here, n-channel), a source terminal (one end), a drain terminal (the other end), and a gate terminal (control terminal).
Have The source terminal of the TFT 241 is connected to a voltage line to which the voltage VHigh is supplied. The drain terminal of the TFT 241 is connected to the data line 114. TFT24
1 gate terminal is connected to the output terminal 213. The TFT 241 has an output terminal 213.
Is turned on when an H level signal is input to the data line 114, the voltage VHigh
h is supplied. In this example, the H level signal is output from the output terminal 213 when the result of the first logical operation is true, that is, the result of the negative logical product in the first logical operation is false (
This is an example of the first value. The source terminal of the TFT 242 is connected to a voltage line to which the voltage VLow is supplied. The drain terminal of the TFT 242 is connected to the data line 114. The gate terminal of the TFT 242 is connected to the output terminal 223. TFT242
Is turned on when an H level signal is input from the output terminal 223, and the data line 1
14 is supplied with a voltage VLow. In this example, the H level signal is output from the output terminal 223 when the result of the second logical operation is true, that is, when the result of the negative logical product in the second logical operation is false. . The source terminal of the TFT 243 is connected to a voltage line to which the voltage VMid is supplied. The drain terminal of the TFT 243 is connected to the data line 114. The gate terminal of the TFT 243 is connected to the output terminal 233. The TFT 243 is turned on when an H level signal is input from the output terminal 233, and the data line 11 is turned on.
4 is supplied with the voltage VMid. In this example, an H level signal is output from the output terminal 233 when the result of the third logical operation is true, that is, the negative result of the third logical operation is true (the second value is Example).

FIG. 4 shows a truth table for the first, second and third logical operations. In the polarity signal Fp and the image data signal Dk, “0” indicates an L (low) level (false) signal, and “1” indicates an H level (true) signal. In the first, second and third logical operations, “0” is false, “1”
Indicates true. The rightmost column in the table of FIG. 4 shows the supplied voltage value. Now, the first, second, and third logical operations using the signal Fp and the signal Vx are respectively expressed as f1 (Fp, Dk), f
2 (Fp, Dk) and f3 (Fp, Dk). As shown in FIG. 4, f1 (1,
1) = 1, f2 (1,1) = f3 (1,1) = 0; f2 (0,1) = 1, f1 (0,1)
= F3 (0, 1) = 0; f3 (1, 0) = 1, f1 (1, 0) = f2 (1, 0) = 0; f
3 (0,0) = 1, f1 (0,0) = f2 (0,0) = 0. That is, when a certain input value is given, the first, second, and third logical operations are configured such that the results of two or more are not simultaneously true. By adopting a circuit that performs such a logical operation, the level conversion circuit 200 selects one voltage from the voltages VHigh, VLow, and VMid.

1-2. Operation FIG. 5 is a timing chart showing the operation of the electro-optical device 1. Scan line drive circuit 13
0 generates scanning signals Y1, Y2, Y3,..., Ym based on the control signal Yctr. The period during which each scanning signal is at the H level (active period) is one horizontal scanning period (1H). The active period sequentially shifts to the adjacent scanning line 112. Thereby, the scanning lines 112 are sequentially selected one by one. The time required for sequentially selecting the m scanning lines 112 is referred to as one field. The value of the polarity signal Fp is different between the odd-numbered field and the even-numbered field. For example, the polarity signal Fp is H level in the odd-numbered field, and the polarity signal Fp is L level in the even-numbered field.

In the data line driving circuit 140, the shift register 141 generates sampling pulses SR1, SR2, SR3,..., SRn based on the control signal Xctr. Switch S
W1 to SWn sample the image data signal Vx based on the sampling pulses SR1 to SRn, respectively. The latch 142 latches the sampling result. That is, the latch 142 latches the value of the image data Vx when the sampling pulse SRk is at the H level as the image data dk. The image data Vx includes data corresponding to the n data lines 114, but the image data Vx is decomposed into dot-sequential image data d1 to dn by the latch 142. The latch 143 receives the image data d1 to d at the start of the horizontal scanning period.
n is latched to obtain line sequential image data D1 to Dn.

The polarity signal Fp supplied from the control circuit 10 is a signal that changes from H level to L level at a predetermined frequency (for example, 60 Hz). Consider a case where the value of the image data Dk is “1” (H level). While the polarity signal Fp is at the H level, an H level signal is output from the output terminal 213, and an L level signal is output from the output terminal 223 and the output terminal 233. In response to these signals, the TFT 241 is turned on, and the TFT 242 and the TFT
243 is turned off. By these switching operations, the voltage VHigh is supplied to the kth data line 114. On the other hand, while the polarity signal Fp is at the L level, the output terminal 22
3 outputs an H level signal, and an output terminal 213 and an output terminal 233 output an L level signal. In response to these signals, the TFT 242 is turned on, and the TFT 24
1 and the TFT 243 are turned off. Through these switching operations, the voltage VLow is supplied to the kth data line 114. That is, the value of the image data Dk is “1”.
In this case, voltages having different polarities are applied to the data line 114 in accordance with the polarity signal Fp.

Next, consider a case where the value of the image data Dk is “0” (L level). in this case,
Regardless of the value of the polarity signal Fp, an H level signal is output from the output terminal 233, and the output terminal 2
13 and the output terminal 223 output an L level signal. In response to these signals, T
The FT 243 is turned on, and the TFTs 241 and 242 are turned off. With these switching operations, the voltage VMid is supplied to the kth data line 114.

As described above, according to the present embodiment, the polarity signal Fp and the image data signal Vx
Accordingly, one voltage is selected from the three voltages (Vhigh, VLow, and VMid). In the selection unit 240, a single transistor is used as a switching element instead of a transfer gate in which an n-channel transistor and a p-channel transistor are combined. According to this embodiment, the circuit scale is reduced as compared with the case where a switching element including a plurality of transistors is used.

2. Second Embodiment FIG. 6 is a diagram showing a configuration of a level conversion circuit 300 according to a second embodiment of the present invention. In the second embodiment, a level conversion circuit 300 is used in place of the level conversion circuit 200 of the first embodiment. Hereinafter, common reference numerals are used for elements common to the first embodiment. The level conversion circuit 300 is different from the level conversion circuit 200 in that it does not have the NOT circuit 250 but has the polarity signal generation circuit 310.

FIG. 7 is a diagram illustrating a configuration of the polarity signal generation circuit 310. Polarity signal generation circuit 310
Are an input terminal to which the polarity signal Fp is input (an example of a sixth input terminal) and a positive polarity signal Fp.
An output terminal (an example of a fourth output terminal) that outputs + (an example of a first polarity signal) and an output terminal (a fifth output) that outputs a negative polarity signal Fp− (an example of a second polarity signal) An example of a terminal). The polarity signal generation circuit 310 generates a positive polarity signal Fp + and a negative polarity signal Fp− based on the polarity signal Fp output from the control circuit 10. Polarity signal generation circuit 310
RC delay circuit 312, NAND circuit 313, and NOT circuit 3 as circuits on the positive polarity side
14 includes a RC delay circuit 315, a NAND circuit 316, and a NOT circuit 317 as a negative polarity side circuit, and a NOT circuit 311 in front of the negative polarity side. The polarity signal Fp is input to the RC delay circuit 312 on the positive polarity side. The NAND circuit 313 includes an RC delay circuit 312.
And the polarity signal Fp are input. The signal S1 has a waveform that is duller than the original polarity signal Fp. The NAND circuit 313 and the NOT circuit 314 output a signal obtained by ANDing the original polarity signal Fp and the signal S1 as a positive polarity signal Fp +. Also,
The polarity signal Fp is inverted by the NOT circuit 311 and this inverted signal is input to the negative polarity side. On the negative polarity side, the inverted signal IFp is input to the RC delay circuit 315. NAND
The circuit S316 receives the signal S2 output from the RC delay circuit 315 and the inverted signal IFp. The signal S2 has a waveform that is duller than the original inverted signal IFp. NAND circuit 3
16 and the NOT circuit 317 output a signal obtained by ANDing the original inverted signal IFp and the signal S2 as a negative polarity signal Fp−.

FIG. 8 is a diagram schematically showing a signal generated by the polarity signal generation circuit 310. With respect to the signals S1 and S2, the broken lines indicate the threshold values of H level and L level. On the positive polarity side, the waveform is blunted by the RC delay circuit 312. Therefore, when the logical product is taken, the time for changing from the L level to the H level is delayed by several clocks from the original signal. R also on the negative polarity side
Since the waveform is blunted by the C delay circuit 315, when the logical product is taken, the time to change from the L level to the H level is delayed by several clocks from the original signal. As described above, the positive polarity signal Fp + and the negative polarity signal Fp− are generated so as not to simultaneously become the H level. That is, there is a margin (tm in the figure) between the time when the positive polarity signal Fp + switches from the H level to the L level and the time when the negative polarity signal Fp− switches from the L level to the H level.

FIG. 9 is a diagram for explaining the possibility of a short circuit due to a signal delay. In FIG. 9, a signal Hc and a signal Lc are respectively a signal output from the control unit 210 and a control unit 22.
The signal output from 0 is shown. When the signal Hc is at the H level, the voltage VHigh is selected, and when the signal Lc is at the H level, the voltage VLow is selected. For example, in the configuration of the first embodiment, when the signal delay td2 in the control unit 220 is longer than the signal delay td1 in the control unit 210, the signal Hc and the signal Lc are simultaneously at the H level, and the voltage VHigh The voltage VLow may be selected at the same time (shaded area in FIG. 9A). That is, the voltage VHigh and the voltage VLow are short-circuited, and the circuit may be destroyed. On the other hand, according to the configuration of the second embodiment, even when the signal delay td2 in the control unit 220 is longer than the signal delay td1 in the control unit 210, the margin tm is sufficient. (Specifically, (tm + td1)> td2, that is, tm> (
td2−td1)), the voltage VHigh and the voltage VLow are not selected at the same time, and a short circuit is prevented (FIG. 9B).

3. Other Embodiments The present invention is not limited to the above-described embodiments, and various modifications can be made. Hereinafter, some modifications will be described. Two or more of the following modifications may be used in combination.

3-1. Modification 1
The channel conductivity types of the TFT 241, TFT 242, and TFT 243 are not limited to those described in the embodiment. The channel conductivity types of the TFT 241, TFT 242, and TFT 243 may not all be the same. Voltage VHigh, VMid and VLo
The magnitude relationship of w is VHigh>VMid> VLow. As described in the embodiment, when n-channel transistors are used as the TFT 241, TFT 242, and TFT 243, the magnitude relationship of the gate-source voltage VGS is TFT 241 <TFT 242 <T.
It is FT243. When the channel widths of the TFT 241, TFT 242, and TFT 243 are designed to be the same, the time required to write data to the data line 114 (charge time) is TFT 241> TFT 242> TFT 243. Here, when the transistor size is determined in accordance with the TFT 241 having the longest charge time, the TFT 242 is determined.
The TFT 243 has a size larger than necessary, and there is a possibility that the circuit scale is wasted. Alternatively, when the transistor size is determined in accordance with the TFT 242 or the TFT 243 having a short charge time, the TFT 241 may be insufficiently charged and display defects may occur.

In the first modification, the TFT 241 is a p-channel transistor, and the TFTs 242 and 243 are n-channel transistors. Since the p-channel transistor is turned on when the signal input to the gate terminal is at the L level, the gate-source voltage when the signal is turned on differs between the n-channel and the p-channel. When the H level voltage input to the gate terminal of the transistor is expressed as VGH and the L level voltage is expressed as VGL, the voltages VGH, VHigh, VMid, VLow and VGL are VGH> VHi.
There is a relationship of gh>VMid>VLow> VGL. The gate-source voltage when the TFT 241 is turned on is (VGH-VHigh) for the n-channel, and (VGL-VHigh) for the p-channel. VGH>VHigh>VMid> VLo
Considering the relationship of w> VGL, | (VGL−VHigh) |> | (V
GH−VHigh) |. In this case, the charge time is shortened by using a p-channel transistor instead of the n-channel transistor as the TFT 241.

In another example, TFT 241, TFT 242, and TFT 243 may all be p-channel transistors. Further, in this case, for the same reason as described above, an n-channel transistor may be used as the TFT 243 instead of the p-channel transistor.

In summary, the transistor for selecting the highest voltage and the transistor for selecting the lowest voltage among the TFT 241, TFT 242, and TFT 243 are:
The channel conductivity types may be different. In this case, the transistor for selecting the highest voltage is a p-channel transistor, and the transistor for selecting the lowest voltage is an n-channel transistor.

3-2. Modification 2
In order to compensate for the difference in charge time described in the first modification, transistors having different channel widths may be used. In this case, the channel width may be designed so that TFT 241> TFT 242> TFT 243 in accordance with the magnitude relationship of the gate-source voltage in the on state. That is, the smaller the difference between the gate voltage and the source voltage (VHigh, VMid, or VLow) when the transistor is turned on, the larger the channel width may be.

3-3. Modification 3
FIG. 10 is a diagram illustrating a projector 2100 according to the third modification. The projector 2100 is an example of an electronic device that uses the electro-optical device 1. Projector 2100
The liquid crystal panel 100 is used as a light valve.
As shown in this figure, a lamp unit 2102 having a white light source such as a halogen lamp is provided inside the projector 2100. The projection light emitted from the lamp unit 2102 is converted into three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. To be separated.
The separated projection lights are light valves 100R, 100G and 100B corresponding to the respective primary colors.
Each led to B light has a long optical path compared to other R and G colors.
In order to prevent the loss, the incident lens 2122, the relay lens 2123, and the exit lens 2
It is guided through a relay lens system 2121 having 124.

In the projector 2100, the liquid crystal display device including the liquid crystal panel 100 has R color, G
Three sets are provided corresponding to each of color and B color. The configuration of the light valves 100R, 100G, and 100B is the same as that of the liquid crystal panel 100 described above. Video signals are respectively supplied from the external upper circuits to specify the gradation levels of the primary color components of R, G, and B, and the light valves 100R, 100G, and 100 are driven. The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, and the G light beam travels straight. Accordingly, after the primary color images are combined, a color image is projected onto the screen 2120 by the projection lens group 2114.

The light valves 100R, 100G, and 100B include a dichroic mirror 2
Since light corresponding to each of R color, G color, and B color is incident by 108, there is no need to provide a color filter. In addition, the transmission images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the light valve 100G
The transmitted image is projected as it is. Accordingly, the horizontal scanning direction by the light valves 100R and 100B is opposite to the horizontal scanning direction by the light valve 100G, and an image in which left and right are reversed is displayed.

In addition to the projector illustrated in FIG. 10, the electronic apparatus in which the electro-optical device 1 is used is a television, a viewfinder type / monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, Examples thereof include a word processor, a workstation, a videophone, a POS terminal, a digital still camera, a mobile phone, and a device equipped with a touch panel.

The configuration of the circuit for performing the first to third logical operations is not limited to that described in the embodiment. A circuit having any configuration may be used as long as the circuit can perform an operation corresponding to the truth table described in FIG. 4 shows TFT 241, TFT 242, and T
Since an example in which an n-channel transistor is used as the FT 243 is shown, when a p-channel transistor is used as a switching element, it is necessary to invert the truth value.

In the embodiment, the example in which the level conversion circuit 200 is formed on the same substrate as the liquid crystal panel 100 by the SOG technique has been described. However, the level conversion circuit 200 includes the liquid crystal panel 10.
It may be formed as a separate part from zero.
In addition, the configuration of the polarity signal generation circuit 310 is not limited to that described in the embodiment. If two polarity signals having a margin tm as illustrated in FIG. 8 can be generated,
Any configuration of circuit may be used.
The electro-optic element is not limited to a liquid crystal display element. Organic Light Emitting Diode (Organic
An electro-optical element other than a liquid crystal display element such as a light-emitting diode (OLED) or a light emitting polymer (LEP) may be used.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 10 ... Control circuit, 100 ... Liquid crystal panel, 105 ... Liquid crystal layer, 108 ... Common electrode, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 1
30 ... Scanning line driving circuit, 140 ... Data line driving circuit, 141 ... Shift register, 142
... Latch, 143 ... Latch, 200 ... Level conversion circuit, 210 ... Control unit, 211 ... Input terminal, 212 ... Input terminal, 213 ... Output terminal, 220 ... Control unit, 221 ... Input terminal, 222
... input terminal, 223 ... output terminal, 230 ... control unit, 232 ... input terminal, 233 ... output terminal, 240 ... selection unit, 241 ... TFT, 242 ... TFT, 243 ... TFT, 250 ... NOT
Circuit, 300 ... level conversion circuit, 310 ... polarity signal generation circuit, 311 ... NOT circuit, 31
2 ... RC delay circuit, 313 ... NAND circuit, 314 ... NOT circuit, 315 ... RC delay circuit, 316 ... NAND circuit, 317 ... NOT circuit, 2100 ... projector, 2102 ...
Lamp unit, 2121 ... relay lens system, 2122 ... incident lens, 2123 ... relay lens, 2124 ... exit lens

Claims (8)

A first input terminal to which a first polarity signal is input and a second input to which a binary image data signal is input
And a first output unit that outputs a result of a first logical operation including a negative logical product of the value indicated by the first polarity signal and the value indicated by the image data signal. When,
A third input terminal to which a second polarity signal whose polarity is inverted at a timing different from that of the first polarity signal is input, a fourth input terminal to which the image data signal is input, and the second polarity signal A second control unit having a second output terminal for outputting a result of a second logical operation including a negative logical product of the value indicated and the value indicated by the image data signal;
A third control unit having a fifth input terminal to which the image data signal is input and a third output terminal for outputting a result of a third logical operation including negation of a value indicated by the image data;
The first voltage is supplied to one end, the other end is connected to the data line, the control terminal is connected to the first output terminal, and the result of the negative logical product in the first logical operation is a first value. A first switching element for supplying the first voltage to the data line in the case of
A second voltage different from the first voltage is supplied to one end, the other end is connected to the data line, a control terminal is connected to the second output terminal, and the negative logic in the second logic operation A second switching element for supplying the second voltage to the data line when a product result is the first value;
A third voltage different from the first voltage and the second voltage is supplied to one end, the other end is connected to the data line, a control terminal is connected to the third output terminal, and the third voltage A third switching element that supplies the third voltage to the data line when the negative result in the logical operation is a second value different from the first value;
Each of the first switching element, the second switching element, and the third switching element comprises a transistor having a single conductivity type channel. A first input terminal to which a polarity signal is input; a second input terminal to which a binary image data signal is input; a first AND including a value obtained by the polarity signal and a negative logical product of the value indicated by the image data signal;
A first control unit having a first output terminal for outputting a result of the logical operation of
The third input terminal to which the inverted signal obtained by inverting the polarity signal, the fourth input terminal to which the image data signal is input, the value indicated by the inverted signal, and the negative logical product of the value indicated by the image data signal A second control unit having a second output terminal that outputs a result of a second logical operation including:
A third control unit having a fifth input terminal to which the image data signal is input and a third output terminal for outputting a result of a third logical operation including negation of a value indicated by the image data;
The first voltage is supplied to one end, the other end is connected to the data line, the control terminal is connected to the first output terminal, and the result of the negative logical product in the first logical operation is a first value. A first switching element for supplying the first voltage to the data line in the case of
A second voltage different from the first voltage is supplied to one end, the other end is connected to the data line, a control terminal is connected to the second output terminal, and the negative logic in the second logic operation A second switching element for supplying the second voltage to the data line when a product result is the first value;
A third voltage different from the first voltage and the second voltage is supplied to one end, the other end is connected to the data line, a control terminal is connected to the third output terminal, and the third voltage A third switching element that supplies the third voltage to the data line when the negative result in the logical operation is a second value different from the first value;
Each of the first switching element, the second switching element, and the third switching element comprises a transistor having a single conductivity type channel. A sixth input terminal to which a third polarity signal is input; a fourth output terminal for outputting the first polarity signal and the second polarity signal generated from the third polarity signal; A polarity signal generation circuit having an output terminal of
The fourth output terminal and the first input terminal are connected;
The level conversion circuit according to claim 1, wherein the fifth output terminal and the second input terminal are connected. Switching for selecting a maximum voltage among the first voltage, the second voltage, and the third voltage among the first switching element, the second switching element, and the third switching element. The channel conductivity type of the element is p-type, and the channel conductivity type of the switching element for selecting the lowest voltage is n-type. Level conversion circuit. Each of the transistors of the switching element, the second switching element, and the third switching element has the first output terminal, the second output terminal, and the third output terminal when the transistor is turned on. 5. The channel width is larger as the difference between the voltage applied from the output terminal and the first voltage, the second voltage, and the third voltage is smaller. 5. The level conversion circuit according to any one of the items. 6. The level conversion circuit according to claim 1, wherein the level conversion circuit is formed on the same substrate as an electro-optical element that performs display according to a voltage applied to the data line. Level conversion circuit. A level conversion circuit according to any one of claims 1 to 6;
An electro-optical device comprising: an electro-optical element that performs display according to a voltage applied to the data line. An electro-optical device according to claim 7,
An electronic apparatus comprising: control means for supplying image data to the electro-optical device.

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