JP2001343939A - Level converting circuit, data line driving circuit, electrooptic device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level converting circuit having low power consumption. SOLUTION: This level converting circuit is constituted of plural converting units. The level converting unit Ua1 generates control signals having small amplitudes based on line sequential picture data D1, odd numbered and even numbered field signals FLOD, FLEV. The control signals are level-shifted by a level shift part 142. A selection part 143 is provided with transfer gates Ga, Gb, Gc and selects certain voltage from among white level voltage VW, first black level voltage VK+ and second black level voltage VK- based on the control signals and outputs these voltages as a data line signal X1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to drive an electro-optical panel having a plurality of scanning lines and a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to their intersections. The present invention relates to a level conversion circuit, a data line driving circuit, an electro-optical device, and an electronic apparatus used for the electronic device.

[0002]

2. Description of the Related Art A conventional electro-optical panel, for example, an active matrix type liquid crystal display panel mainly includes an element substrate in which pixel electrodes arranged in a matrix are provided with switching elements and a color filter. And a liquid crystal filled between the two substrates. In such a configuration, when a scanning signal (selection voltage) is applied to the switching element via the scanning line, the switching element is turned on. When a signal is applied to the pixel electrode via the data line in the conductive state, predetermined charges are accumulated in the liquid crystal layer between the pixel electrode and the counter electrode (common electrode). After the charge accumulation, even if a non-selection voltage is applied to turn off the switching element, if the resistance of the liquid crystal layer is sufficiently high, the accumulation of charge in the liquid crystal layer is maintained. Then, when the amount of electric charge to be accumulated by driving each switching element is controlled,
The alignment state of the liquid crystal changes for each pixel, so that predetermined information can be displayed.

In such a liquid crystal display panel, a data line driving circuit that outputs a ternary voltage to drive each data line is sometimes used. For example, if the liquid crystal display panel operates in a normally white mode, the white level voltage VW
Is supplied to the data line, while the white level voltage VW,
A selected one of the first black level voltage VK + and the second black level voltage VK− is supplied. Here, the first black level voltage VK + and the second black level voltage VK− have inverted polarities around the white level voltage VW. Since the transmittance of the liquid crystal changes according to the effective voltage between the common electrode and the pixel electrode, the first black level voltage VK +
And the second black level voltage VK- is supplied with the same transmittance.

However, the liquid crystal has a property that its composition changes when a DC voltage is applied and its characteristics are degraded. Therefore, the voltage supplied to the data line is driven by an AC drive centering on the voltage of the common electrode. It is common to do. For this reason,
Focusing on a certain data line, the first black level voltage VK + is selected when displaying a black level in a certain field, while the second black level voltage VK + is selected in the next field.
K- is selected.

In such a conventional data line driving circuit, input image data is converted into line sequential image data corresponding to the number of data lines, and the level of each line sequential image data is converted by a level conversion circuit. Supplied to the data line. FIG. 14 is a circuit diagram of a level conversion circuit used in a conventional data line drive circuit.

As shown in FIG. 1, a level conversion circuit corresponding to a certain data line includes inverters INV1 to INV3, a level shifter LS, and transfer gates G1 to G4. The odd field signal FLOD becomes "1" only when the field is an even field, and the even field signal FLEV becomes "1" only when the field is an odd field.

[0007] According to the above configuration, the transfer gate G1 is connected to the first black level voltage VK in the odd field.
+, While the transfer gate G2 outputs the second black level voltage VK- in the even field.
The transfer gate G3 supplies the output voltage of the transfer gate G1 to the data line when the line-sequential image data D is "0", and enters a high impedance state when the line-sequential image data D is "1". In addition, the transfer gate G4 sets the line-sequential image data D to "0".
When the line sequential image data D is "1", the white level voltage VW is supplied to the data line.

Here, since the voltages supplied to the data lines via the transfer gate G3 are the first and second black level voltages VK + and VK-, the levels of the control signals are the second black level voltages VK + and VK. It is necessary to have a large amplitude so that-can be switched. Level shifter LS
Is used for this purpose, and the line-sequential image data D
Functions as a converter for converting the into a large amplitude.

[0009]

By the way, in the conventional level conversion circuit, the transfer gates G1 and G2
Switches the first and second black level voltages VK + and VK-, similarly to the transfer gate G3. Therefore, it is necessary to make the amplitudes of the odd field signal FLOD and the even field signal FLEV large.

However, when these signals are driven with a large amplitude, there is a problem that the circuit scale of the driving circuit becomes large and power consumption increases. Further, in the conventional level conversion circuit, since four transfer gates are used, there is a problem that the circuit scale is large.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a level conversion circuit and the like in which power consumption is reduced and a circuit scale is reduced.

[0012]

In order to achieve the above object, a level conversion circuit according to the present invention is adapted to handle a plurality of scanning lines, a plurality of data lines, and an intersection of the scanning lines and the data lines. And a small-amplitude field signal indicating a small-amplitude image data corresponding to a certain data line and a field type. A control section that generates a small-amplitude control signal based on the small-amplitude control signal; a level shift section that generates a large-amplitude control signal by converting the logical amplitude level into a large amplitude based on the small-amplitude control signal; A selection unit that outputs a voltage selected from a plurality of voltages to the data line based on the amplitude control signal.

According to the present invention, the control unit generates a small amplitude control signal based on the small amplitude image data and the small amplitude field signal, and the selection unit operates by the large amplitude control signal subjected to the level shift processing. . Therefore, the amplitude of the field signal can be made small, and a driving circuit having a small driving ability can be used as a driving circuit for driving the field signal. Further, power consumption of the driving circuit can be reduced. In addition, since the control section only needs to operate with a small amplitude, the power consumption of the level conversion circuit itself can be reduced.

Here, the plurality of voltages are a reference voltage, a positive voltage having a potential difference on the positive side with the reference voltage as the center voltage, and a negative voltage having the potential difference on the negative side with the reference voltage as the center voltage. The control unit controls the selection unit to select the reference voltage when the small-amplitude image data indicates one digit, and when the small-amplitude image data indicates the other digit, It is preferable that the selector is controlled so as to select one of the positive polarity voltage and the negative polarity voltage depending on whether the small-amplitude field signal indicates an odd field or an even field. Further, it is desirable that the reference voltage is a voltage of a common electrode sandwiching a pixel electrode and a liquid crystal serving as an electro-optical material. In this case, the data line can be AC-driven around the reference voltage.

In the above-described level conversion circuit,
The selector includes a first transfer gate connected to a data line having one input / output terminal, a positive transfer voltage supplied to the other input / output terminal, and one input / output terminal connected to the data line. A second transfer gate having the other input / output terminal supplied with the reference voltage, a third transfer gate having one input / output terminal connected to the data line, and the other input / output terminal supplied with the negative voltage. It is preferable that the control unit controls the selection unit by supplying the large-amplitude control signal to each control input terminal of the first, second, and third transfer gates. According to this configuration, since each transfer gate is controlled by the large-amplitude control signal, the field signal is not directly supplied to the control input terminal of the transfer gate. Therefore, a signal having a small amplitude can be used as the field signal.

According to another aspect of the present invention, there is provided a level conversion circuit comprising: a plurality of scanning lines; a plurality of data lines; pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A level conversion circuit used for a drive circuit for driving an electro-optical panel having
A control unit that generates a small-amplitude control signal based on small-amplitude image data corresponding to a certain data line and a small-amplitude field signal indicating a type of an odd field or an even field; a reference voltage as the power supply voltage; A positive voltage having a potential difference on the positive side as a center voltage, a negative voltage having the potential difference on the negative side with the reference voltage as the center voltage is fed, and based on the small amplitude control signal, And a level shifter for outputting a voltage selected from the above to the data line.

According to the present invention, since the level shifter operates using the reference voltage, the positive voltage, and the negative voltage as the power supply voltage, it is possible to select and output a desired voltage from these voltages. it can. As a result, the data line can be driven in three values without using the selection unit,
The circuit scale of the level conversion circuit can be significantly reduced.

Here, the control section includes: a first small-amplitude control signal that is active when the small-amplitude image data indicates one digit and the small-amplitude field signal indicates one field; A second signal that is active when the small-amplitude image data indicates one digit and the small-amplitude field signal indicates the other field;
A low-amplitude control signal, wherein the level shift unit is supplied with the positive voltage as a positive power supply voltage, is supplied with the reference voltage as a negative power supply voltage, and the first small-amplitude control signal is active. When the positive polarity voltage is output from an output terminal, the output terminal is set to a high impedance state when the first small amplitude control signal is inactive and the second small amplitude control signal is active, and the first small amplitude control signal is A first circuit for outputting the reference voltage from an output terminal when the reference voltage is inactive and the second small amplitude control signal is inactive;
A level shifter, while the reference voltage is supplied as a positive power supply voltage, the negative voltage is supplied as a negative power supply voltage, and the negative voltage is output from an output terminal when the second small amplitude control signal is active; When the second small amplitude control signal is inactive and the first small amplitude control signal is active, the output terminal is set to a high impedance state, and the first small amplitude control signal is inactive and the second small amplitude control signal is inactive. It is preferable that a second level shifter that outputs the reference voltage from an output terminal when active is provided, and a connection point between an output terminal of the first level shifter and an output terminal of the second level shifter be connected to the data line. Thus, the data lines can be directly driven by the first level shifter and the second level shifter.

Next, in the data line driving circuit of the present invention, a plurality of scanning lines, a plurality of data lines, and a matrix are arranged corresponding to intersections of the scanning lines and the data lines. A first conversion unit for converting input image data into point-sequential image data, and converting the point-sequential image data into line-sequential image data, wherein the first conversion unit is used for an electro-optical panel having pixel electrodes and switching elements. And a plurality of level conversion circuits described above, and the line-sequential image data is supplied to the level conversion circuits as the small-amplitude image data. According to the data line driving circuit, the amplitude of the field signal can be reduced to a small value, and a driving circuit having a small driving capability can be used as a driving circuit for driving the field signal. Further, power consumption of the driving circuit can be reduced. In addition, the power consumption of the level conversion circuit itself can be reduced and the circuit size can be reduced, and the power consumption and the circuit size of the data line drive circuit can be reduced.

Next, the electro-optical device according to the present invention comprises a plurality of scanning lines, a plurality of data lines, pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A pixel region having an element, the above-described data line driving circuit, a scanning line driving circuit for driving the scanning line, and a timing generation circuit for generating the small amplitude field signal and supplying the small amplitude field signal to the data line driving circuit And characterized in that: According to this electro-optical device, since the small-amplitude field signal generated by the timing generation circuit requires only a small amplitude, the circuit scale of the drive circuit can be reduced and the power consumption of the entire electro-optical device can be reduced. In this case, the switching element formed in the pixel region is a thin film transistor, and the driving circuit is preferably formed of a thin film transistor.

An electronic apparatus according to the present invention includes the above-described electro-optical device, and includes, for example, a viewfinder, a mobile phone, a notebook computer, and a video projector used for a video camera. I do.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

<1. First Embodiment><1-1: Overall Configuration of Liquid Crystal Device> First, a liquid crystal device using liquid crystal as an electro-optical material will be described as an example of an electro-optical device according to the present invention. The main part of the liquid crystal device is
As will be described later, an element substrate on which a thin film transistor (hereinafter, referred to as a “TFT”) is formed as a switching element and a counter substrate are attached to each other with an electrode forming surface facing each other and a constant gap. The liquid crystal panel has a liquid crystal sandwiched in the gap.

FIG. 1 is a block diagram showing the overall configuration of the liquid crystal device according to the first embodiment. This liquid crystal device has an image display area A and a data line driving circuit 1 on a liquid crystal panel element substrate.
00, a scanning line driving circuit 200, and a timing generation circuit 300 as an external processing circuit.

In this example, it is assumed that the number of bits of the input image data Din supplied to the liquid crystal device is 1 bit. However, the present invention is not limited to this, and it goes without saying that a plurality of bits may be used. In this example, the input image data D is described as corresponding to one color, but it is needless to say that the input image data D may correspond to three primary colors of RGB.

Here, the timing generation circuit 300 synchronizes the Y clock signal YCK,
Inverted Y clock signal YCKB, X clock signal XCK,
Inverted X clock signal XCKB, Y transfer start pulse DY,
In addition to the X transfer start pulse DX and the latch pulse LAT, an odd field signal FLOD and an even field signal
The FLEV is generated and supplied to the data line driving circuit 100 and the scanning line driving circuit 200. Various signals generated by the timing generation circuit 300 have small amplitudes in order to reduce power consumption. For example, when the logic level is "0", 0V, and when the logic level is "1", 5V.
V.

Next, the scanning line driving circuit 200 includes a Y shift register and a level shifter (not shown).
The Y shift register sequentially transfers the Y transfer start pulse DY in accordance with the Y clock signal YCK and the inverted Y clock signal YCKB, and sequentially generates signals that become active in each horizontal scanning period. The level shifter level-shifts each output signal of the Y shift register so as to control on / off of the TFT 50 and outputs the signals as scanning signals Y1 to Ym.

<1-2: Image Display Area> Next, as shown in FIG. 1, the image display area A has m scanning lines 3a.
Are arranged in parallel along the X direction, while n
The data lines 6a are arranged in parallel along the Y direction. Near the intersection of the scanning line 3a and the data line 6a, the gate of the TFT 50 is connected to the scanning line 3a.
While the source of the TFT 50 is connected to the data line 6a.
And the drain of the TFT 50 is connected to the pixel electrode 9a. Each pixel has a pixel electrode 9a and a common electrode (described later) formed on a counter substrate.
And a liquid crystal sandwiched between these electrodes. As a result, the pixels are arranged in a matrix corresponding to each intersection of the scanning line 3a and the data line 6a.

The scanning signals Y1, Y2,..., Ym are applied to each scanning line 3a to which the gate of the TFT 50 is connected in a pulsed line-sequential manner. For this reason, when a scanning signal is supplied to a certain scanning line 3a, the TFT 50 connected to the scanning line is turned on, so that the image signals X1 and X1 supplied from the data line 6a at a predetermined timing.
X2,..., Xn are written in the corresponding pixels in order, and are held for a predetermined period.

Here, since the orientation and order of the liquid crystal molecules change according to the voltage level applied to each pixel, gradation display by light modulation becomes possible. For example, in a normally white mode, the amount of light passing through the liquid crystal is limited as the applied voltage increases, while in a normally black mode, the amount of light is reduced as the applied voltage increases. Then, light having a contrast according to the image data is emitted for each pixel. For this reason, a predetermined display is possible.

To prevent the held image signal from leaking, a storage capacitor 51 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the common electrode. For example, since the voltage of the pixel electrode 9a is held by the storage capacitor 51 for a time that is three orders of magnitude longer than the time during which the source voltage is applied, the holding characteristics are improved, and a high contrast ratio is realized. Become.

<1-3: Data Line Driving Circuit> Next, as shown in FIG. 1, the data line driving circuit 100 includes an X shift register 110, an image data supply line L to which input image data Din is supplied, and a switch SW1. To SWn, first latch 1
20, a second latch 130, and a level conversion circuit 140A. The active elements constituting the data line driving circuit 100 are constituted by TFTs, and are formed at the same time when the TFTs 50a of the image display area A are formed.

First, the X shift register 110 sequentially shifts the X transfer start pulse DX according to the X clock XCK and the inverted X clock XCKB to sequentially generate the sampling pulses SR1, SR2,..., SRn. .

Next, the image data supply line L1 is connected to the first latch 120 via the switches SW1 to SWn, and each control input terminal of the switches SW1 to SWn has:
The sampling pulses SR1, SR2,..., SRn are supplied. Therefore, the input image data Din is supplied to the first latch 120 in synchronization with the sampling pulses SR1, SR2,..., SRn.

Next, the first latch 120 is connected to the switch SW
The input image data Din supplied from 1 to SWn is latched, whereby dot-sequential image data d1 to dn scanned in dot-sequential manner are obtained. The second latch 130 latches the dot sequential image data d1 to dn by a latch pulse LAT. Here, the latch pulse LAT is a signal that becomes active every one horizontal scanning period. Therefore, the second latch 130 converts the dot-sequential image data d1 to dn into the line-sequential image data D1 to Dn.
Has been converted to.

Next, the level conversion circuit 140A generates a white level voltage V based on the line-sequential image data D1 to Dn, the odd field signal FLOD and the even field signal FLEV.
A selected one of W, the first black level voltage VK +, and the second black level voltage VK− is supplied to each data line 6a as data line signals X1 to Xn. Note that the white level voltage VW acts as a voltage supplied to the common electrode 158 (see FIG. 6) of the opposite substrate, and the first black level voltage VK +
Acts as a positive voltage having a potential difference ΔV on the positive side with the white level voltage VW as the center voltage, and the second black level voltage VK− has a negative voltage having a potential difference ΔV on the negative side with the white level voltage VW as the center voltage. Act as

<1-4: Level Conversion Circuit> Next, the configuration of the level conversion circuit 140A will be described. FIG. 2 is a circuit diagram showing a detailed configuration of the level conversion circuit 140A.
As shown in the figure, the level conversion circuit 140A
n conversion units Ua1 to Uan corresponding to the total number of a
It has. Further, each conversion unit Ua1 to Uan
Includes a control unit 141, a level shift unit 142, and a selection unit 143. Then, for each of the conversion units Ua1 to Uan, the line-sequential image data D1 to Dn, the odd field signal FLOD and the even field signal FLEV
, The data line signals X1 to Xn are generated.

FIG. 3 is a circuit diagram of the conversion unit Ua1. Note that the other conversion units Ua2 to Uan are configured in the same manner as the conversion unit Ua1, and a description thereof will be omitted. First, the control unit 141 includes AND circuits a1, a2 and inverters inv1 to inv3, and controls the control signals Ca1, Ca2, Cb1, based on the line-sequential image data D1, the odd field signal FLOD, and the even field signal FLEV.
Cb2, Cc1 and Cc2 are generated and the level shift unit 14
2 is output. Further, the logic circuit constituting the control unit 141 operates with a small amplitude. Therefore, the amplitude of each of the control signals Ca1 to Cc2 is, for example, 0 V at the L level, and 3 to 5 V at the H level.
Becomes

Next, the level shift section 142 includes level shifters LSa, LSb, LSc and inverters inv4 to inv9 functioning as buffers, and each control signal Ca1
~ Cc2 are converted and output. Here, VHH is supplied as a positive power supply voltage to the level shifters LSa, LSb, LSc and the inverters inv4 to inv9, while VSS is supplied as a negative power supply voltage. Therefore, the output signals of the inverters inv4 to inv9 fluctuate between the voltage VHH and the voltage VSS. In this example, three level shifters LSa, LS
b and LSc are required, but since they are composed of TFTs, power is consumed only when the logic level changes. Therefore, the level shifter LSc does not consume power in the odd field, and the level shifter Ga does not consume power in the even field. Therefore, when the logical level of the line-sequential image data D1 changes, power is consumed in the two level shifters.

Next, the selection section 143 includes three transfer gates Ga, Gb, Gc, and one input / output terminal of each transfer gate Ga, Gb, Gc is connected at a connection point P, and The voltage of P is the data line signal X1
Is output. The other input / output terminals of the transfer gates Ga, Gb, Gc are connected to the first black level voltage V via voltage supply lines L1 to L3.
K +, white level voltage VW, and second black level voltage VK
− Are each supplied. In this example, the positive power supply voltage VHH and the negative power supply voltage VSS are set so that VHH> VK + and VSS <VK- so that the on / off operation of the transfer gates Ga, Gb, and Gc can be performed reliably. . The values of the first black level voltage VK +, the white level voltage VW, and the second black level voltage VK− depend on the characteristics of the liquid crystal used, but for example, VW is 10 V, VK + is 20 V, and VK−. Is 0V.

In the above configuration, the level shifter LSa
The positive input terminal is supplied with the output signal of the AND circuit a1, and the negative input terminal is supplied with an inverted version of the output signal via the inverter inv1. Therefore, the transfer gate Ga is turned on, and the first black level voltage V
K + is supplied to the connection point P because the line-sequential image data D
1 digit and odd field signal FLOD are both '1'
Only when Here, the case where the transfer gate Ga is turned on is represented by “1”, and the case where the transfer gate Ga is turned off is represented by “0”, and the truth table thereof is shown in FIG.
It becomes what is shown in.

Further, line-sequential image data D1 is supplied to a negative input terminal of the level shifter LSb, and an inverted version of the line-sequential image data D1 is supplied to its positive input terminal via an inverter inv2. Therefore, the transfer gate Ga is turned on and the white level voltage VW is supplied to the connection point P only when the line-sequential data D1 becomes "0". Here, if the transfer gate Gb is turned on and represented by “1”, and the transfer gate Gb is turned off by “0”, the truth table is as shown in FIG. 4B.

In addition, the output signal of the AND circuit a2 is supplied to the positive input terminal of the level shifter LSc, and the inverted output signal is supplied to the negative input terminal via the inverter inv3. Therefore, the transfer gate G
c is turned on and the second black level voltage VK− is supplied to the connection point P only when both the digit of the line-sequential image data D1 and the even field signal FLEV become “1”. Here, when the transfer gate Gc is turned on, and the transfer gate Gc is turned off, it is represented by '0', and the truth table is as shown in FIG. 4C.

As a result, when the line-sequential image data is "0", only the transfer gate Gb is turned on regardless of the field type, and the voltage of the data line signal X1 becomes the white level voltage VW. On the other hand, when the line-sequential image data is “1”, the voltage of the data line signal X1 is determined according to the field type. Specifically, the voltage of the data line signal X1 in the odd field is equal to the first black level voltage VK.
+, And the voltage of the data line signal X1 becomes the second black level voltage VK− in the even field.

Therefore, the level conversion circuit 140A
According to the method, the voltage supplied to a certain data line 6a can be inverted on a field basis, and deterioration of the characteristics of the liquid crystal can be prevented.

According to this example, the level conversion circuit 1
In each of the conversion units Ua1 to Uan of 40A, the control unit 141 operates with a small amplitude. Therefore, the logic amplitude of the odd field signal FLOD and the even field signal FLEV need only be a small amplitude (3 to 5 V) enough to operate the logic circuit of the control unit 141, and the transfer gates Ga and
The large amplitude required to control Cb and Gc (20
V) is unnecessary. The odd field signal FLOD and the even field signal FLEV are generated by the timing generation circuit 300 which is an external circuit for the liquid crystal panel 100, and the circuits operate with a small amplitude. Therefore, according to the level conversion circuit 140A, it is not necessary to convert the signal amplitude into a large amplitude by a level shifter or the like, and the output signal of the timing generation circuit 300 can be directly used. Thereby, the level shifter can be omitted, and the configuration can be simplified.

The odd field signal FLOD and the even field signal FLEV are connected to the signal supply line L as shown in FIG.
Since the signal is supplied to the n conversion units Ua1 to Uan via o and Le, the signal supply lines Lo and Le have stray capacitances corresponding to their wiring lengths. Input capacitance is attached. Therefore, from the viewpoint of the driving circuit that supplies both signals, the signal supply lines Lo and Le are provided.
Acts as a heavy capacitive load. However, as described above, the amplitudes of the odd field signal FLOD and the even field signal FLEV need only be small, so that the level conversion circuit 140
A and power consumption can be greatly reduced.

<1-5: Configuration Example of Liquid Crystal Panel> Next, the overall configuration of the liquid crystal panel according to the above-described electrical configuration will be described with reference to FIGS. Here, FIG.
FIG. 6 is a perspective view illustrating a configuration of a liquid crystal panel, and FIG. 6 is a cross-sectional view taken along line ZZ ′ in FIG.

As shown in these figures, the liquid crystal panel comprises an element substrate 151 such as glass or semiconductor on which the pixel electrodes 9a and the like are formed, and a transparent counter substrate 152 such as glass on which the common electrodes 158 and the like are formed. And a sealing material 154 in which spacers 153 are mixed so as to keep a certain gap therebetween so that the electrode forming surfaces face each other, and a liquid crystal 155 as an electro-optical material is sealed in this gap. I have. Note that the sealant 154 is formed along the periphery of the counter substrate 152,
5 is partially open to enclose it. Therefore, after the liquid crystal 155 is sealed, the opening is sealed by the sealing material 156.

Here, the data line drive circuit 100 described above is formed on one side of the seal member 154 opposite to the element substrate 151 to drive the data line 6a extending in the Y direction. It has become. further,
A plurality of connection electrodes 157 are formed on one side to receive various signals from the timing generation circuit 300 and input image data Din. A scanning line driving circuit 200 is formed on one side adjacent to the one side, and drives the scanning lines 3a extending in the X direction from both sides.

On the other hand, the common electrode 158 of the opposite substrate 152
Of the four corners of the portion to be bonded to the element substrate 151
By the conductive material provided in at least one place,
Electrical continuity with the element substrate 151 is achieved. In addition, depending on the use of the liquid crystal panel,
For example, first, color filters arranged in a stripe, mosaic, triangle, or the like are provided. Second, for example, a metal material such as chromium or nickel, or carbon or titanium is dispersed in a photoresist. Third, a black matrix such as resin black is provided.
A backlight for irradiating the liquid crystal panel with light is provided.
In particular, in the case of color light modulation, a black matrix is provided on the counter substrate 152 without forming a color filter.

In addition, an alignment film or the like that has been rubbed in a predetermined direction is provided on the opposing surfaces of the element substrate 151 and the opposing substrate 152, and a polarizing plate (corresponding to the alignment direction) is provided on each back surface thereof. (Not shown) are provided. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 155, the above-described alignment film, polarizing plate, and the like become unnecessary, and the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

Instead of forming part or all of the peripheral circuits such as the data line driving circuit 100 and the scanning line driving circuit 200 on the element substrate 151, for example, TAB (Tape A)
The driving IC chip mounted on the film using the utomated bonding technique may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position on the element substrate 151. The IC chip itself is mounted on the element substrate 1 using COG (Chip OnGrass) technology.
A predetermined position 51 may be electrically and mechanically connected via an anisotropic conductive film.

<1-6: Operation of Liquid Crystal Device> Next, the operation of the liquid crystal device will be described. FIG. 7 is a timing chart showing the operation of the liquid crystal device.

First, when the Y transfer start pulse DY is supplied to the scanning line driving circuit 200, the scanning line driving circuit 200
The Y transfer start pulse DY is sequentially transferred based on the Y clock signal YCK and the inverted Y clock signal YCKB to generate the scanning line signals Y1, Y2,..., Ym shown in FIG. The active period of each scanning line signal Y1, Y2,.
This is a horizontal scanning period, which is sequentially shifted. Thereby, each scanning line 3a is sequentially selected.

On the other hand, when the X transfer start pulse DX is supplied to the data line driving circuit 100, the X shift register 110
Sequentially shifts them to generate sampling pulses SR1, SR2,..., SRn shown in FIG. Switches SW1 to SWn are connected to sampling pulses SR1, SR
, SRn, the input image data Din is sampled and the first latch 120 latches the sampling result, so that the dot-sequential image data d1, d2,.
Is as shown in FIG.

Thereafter, at the start of the horizontal scanning period, the second latch 130 sets the point-sequential image data d1d1, d2,.
By latching n, line-sequential image data D1, D2,..., Dn shown in FIG.

Here, it is assumed that the digit of the line-sequential image data D1 is "1" in the first horizontal scanning period in the even field. In this case, the odd field signal
Since FLOD is “0” and the even field signal FLEV is “1”, G of the transfer gates Ga, Gb, and Gc in the conversion unit Ua1 shown in FIG.
Only c is turned on. Therefore, the data line signal X1
Becomes the second black level voltage VK-, and the second black level voltage VK- is applied to the pixel electrode 9a at the upper right corner shown in FIG. Here, since the white level voltage VW is applied to the common electrode 158, the liquid crystal of the pixel displays black.

On the other hand, assuming that the digit of the line-sequential image data D1 is "0" during the period, only Gb of the transfer gates Ga, Gb, Gc is turned on, and the voltage of the data line signal X1 becomes the white level. Voltage VW
Becomes Therefore, the voltage of the pixel electrode 9a of the pixel and the voltage of the common electrode 158 match, and the applied voltage of the liquid crystal becomes 0V. As a result, the pixel displays white.

In such an operation of the conversion unit Ua1, since the control section 141 operates with a low logic amplitude, a small amplitude is sufficient for the odd field signal FLOD and the even field signal FLEV. Accordingly, first, there is no need to convert the amplitudes of both signals into a large amplitude by a level shifter or the like, and the timing generation circuit 300
Can be directly used. Second, both signals can be supplied to the level conversion circuit 140A by using a driving circuit having a small driving capability, and power consumption can be significantly reduced.

<2. Second Embodiment> The overall configuration of a liquid crystal device according to a second embodiment is substantially the same as the liquid crystal device according to the first embodiment shown in FIG. 1, and a level conversion circuit 140A of the data line driving circuit 100 is used instead of the level conversion circuit 140A. Circuit 140B
Is different.

FIG. 8 is a block diagram showing the configuration of the level conversion circuit 140B used in the liquid crystal device according to the second embodiment. As shown in this figure, the level conversion circuit 140B
It has n conversion units Ub1 to Ubn, and each of the conversion units Ub1 to Ubn includes line-sequential image data D1 to Db1.
The data line signals X1 to Xn are generated based on Dn and the odd field signal FLOD and the even field signal FLEV. Furthermore, each conversion unit Ub1
Ubn includes a control unit 144 and a level shift unit 145, respectively.

FIG. 9 is a circuit diagram of the conversion unit Ub1. Note that the other conversion units Ub2 to Ubn are configured in the same manner as the conversion unit Ub1, and a description thereof will be omitted. First, the control unit 144 includes AND circuits a3 and a4, and stores line-sequential image data D1 and odd-numbered field signals.
Control signals C1 and C2 are generated based on the FLOD and the even field signal FLEV and output to the level shift unit 145. Also, the AND circuits a3 and a4 operate with a small amplitude. Therefore, the amplitude of each of the control signals C1 and C2 is, for example, 0 V at the L level and 5 V at the H level.

Next, the level shift section 145 includes level shifters LSd and LSe. Level shifter LSd
Is supplied with the first black level voltage VK + as the positive power supply voltage, and is supplied with the white level voltage VW as the negative power supply voltage, and the control signals C1 and C2 are supplied to the input terminals IN1 and IN2.
Are supplied respectively. The level shifter LSe is supplied with the white level voltage VW as a positive power supply voltage, while the second black level voltage VK as a negative power supply voltage.
Is supplied with power, and a control signal C is supplied to each of the input terminals IN1 and IN2.
2 and C1 are respectively supplied.

First, the level shifter LSd is connected to the input terminal I
When the voltage Vin1 of N1 is "1", the first black level voltage VK + which is a positive power supply voltage is output, the voltage Vin1 of the input terminal IN1 is "0", and the voltage Vin2 of the input terminal IN2 is "1".
In this case, the output terminal is set to a high impedance state, and when the voltage Vin1 of the input terminal IN1 is "0" and the voltage Vin2 of the input terminal IN2 is "0", the white level voltage VW which is a negative power supply voltage is output. ing.

Next, the level shifter LSe is connected to the input terminal I
When the voltage Vin1 of N1 is "1", the second black level voltage VK- which is a negative power supply voltage is output, and the voltage Vin1 of the input terminal IN1 is "0" and the voltage Vin2 of the input terminal IN2 is "1".
In this case, the output terminal is set to a high impedance state, and when the voltage Vin1 of the input terminal IN1 is "0" and the voltage Vin2 of the input terminal IN2 is "0", the white level voltage VW which is a positive power supply voltage is output. ing. Therefore, the truth table of the output signals of the level shifters LSd and LSe is shown in FIG.
0 (a) and (b).

Here, the logical level of the control signal C1 is given by the logical product of the line-sequential image data D1 and the odd field signal FLOD, while the logical level of the control signal C2 is the logical product of the line-sequential image data D1 and the even field signal FLEV. Given by the logical product of

Therefore, when the digit of the line-sequential image data D1 is "0", the level shifters LSd and LSe both output the white level voltage VW regardless of the field type. As a result, the voltage of the data line signal X1 becomes the white level voltage VW.

In the odd field, when the digit of the line-sequential image data D1 is "1", the control signal C1 becomes "1" and the control signal C2 becomes "0". In this case, while the first black level voltage VK + is output from the level shifter LSd, the level shifter LSe enters a high impedance state, so that the data line signal X1 is output.
Is the first black level voltage VK +.

When the digit of the line-sequential image data D1 is "1" in the even field, the control signal C1 becomes "0" and the control signal C2 becomes "1". In this case, while the level shifter LSd is in the high impedance state, the second black level voltage VK− is output from the level shifter LSe.
Is the second black level voltage VK-.

Therefore, level conversion circuit 140B
According to the method, the voltage supplied to a certain data line 6a can be inverted on a field basis, and deterioration of the characteristics of the liquid crystal can be prevented.

According to this example, the level conversion circuit 1
In each of the conversion units Ua1 to Uan of 40B, since the control unit 144 is operated with a low logical amplitude, the logical amplitude of the odd field signal FLOD and the even field signal FLEV requires only a small amplitude as in the first embodiment. Thus, the output signal of the timing generation circuit 300 can be directly used. In addition, the odd field signal FLOD and the even field signal FLEV can be supplied to the level conversion circuit 140B using a driving circuit having a small driving ability,
In addition, power consumption can be significantly reduced.

Further, in this example, the level shifter LS
d, LSe as a positive / negative power supply, a first black level voltage VK
+, White level voltage VW, and second black level voltage VK−
, Transfer gates for selecting these voltages can be omitted. For example, when the total number of the data lines 6a is 1024, if the level conversion circuit of the first embodiment shown in FIG.
Although a number of transfer gates are required, in this example, these can be omitted, so that the circuit scale can be significantly reduced.

<3. Application example><3-2: Case where input image data is a plurality of bits> In each of the above-described embodiments, the number of bits of input image data Din is 1 bit, that is, the number of gradations displayed by each pixel is Although the case of two gradations has been described, the input image data D
in may be composed of a plurality of bits. In this case, for example, in the data line driving circuit 100 shown in FIG. 1, first, each of the switches SW1 to SWn to which the sampling pulses SR1 to SRn are supplied, the first latch 120, and the second latch 130 are formed by a plurality of bits. Thus, the input image data Din is converted into line-sequential image data D1 to Dn. Second, between the level conversion circuit 140A (140B) and the second latch 130, a PWM circuit that varies the pulse width of each output signal according to the data value of the line-sequential image data D1 to Dn is provided. A signal having a pulse width corresponding to the data value may be input to the level conversion circuit 140A (140B).

Further, one field period is divided into a plurality of periods, m scanning lines 3a are sequentially selected in each divided period, and each divided period is converted into each bit of line-sequential image data. The voltage of the data line signal in each divided period may be determined according to whether the bit is “1” or “0”.

<3-2: Configuration of Element Substrate, etc.> In each of the above embodiments, the element substrate 151 of the liquid crystal panel is formed of a transparent insulating substrate such as glass, and a silicon thin film is formed on the substrate. In addition, the switching elements (TFTs 50) of the pixels, the elements of the data line driving circuit 100, and the elements of the scanning line driving circuit 200 are described as being constituted by the TFTs having a source, a drain, and a channel formed on the thin film. The present invention is not limited to this.

For example, the element substrate 151 is formed of a semiconductor substrate, and the switching element of the pixel and the elements of various circuits are formed by the insulated gate field effect transistor having the source, drain and channel formed on the surface of the semiconductor substrate. You may comprise. When the element substrate 151 is formed of a semiconductor substrate as described above, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 9a is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 151 may simply be a transparent substrate and the pixel electrode 9a may be of a reflection type.

Further, in the above embodiment,
Although the switching element of the pixel has been described as a three-terminal element represented by a TFT, it may be configured with a two-terminal element such as a diode. However, when a two-terminal element is used as the switching element of the pixel, the scanning line 3a is formed on one substrate, the data line 6a is formed on the other substrate, and the two-terminal element is connected to the scanning line 3a or the data line. 6a and the pixel electrode.
In this case, the pixel is composed of a liquid crystal and a two-terminal element connected in series between the scanning line 3a and the data line 6a.

Although the present invention has been described as an active matrix type liquid crystal display device, the present invention is not limited to this.
It is also applicable to a passive type using an N (Super Twisted Nematic) liquid crystal or the like. Further, as the electro-optical material, in addition to the liquid crystal, the present invention can be applied to a display device which uses an electroluminescence element or the like to perform display by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described liquid crystal device.

<3-3: Electronic Apparatus> Next, a case where the above-described liquid crystal device is applied to various electronic apparatuses will be described.

<3-3-1: Projector> First, a projector using this liquid crystal device as a light valve will be described. FIG. 11 is a plan view showing a configuration example of the projector.

As shown in FIG.
Inside 100, a lamp unit 1102 composed of a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and is used as a light valve corresponding to each primary color. Liquid crystal panels 1110R, 1110B and 1110
G is incident.

The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the above-described liquid crystal panel, and include R, R, and R supplied from an image signal processing circuit (not shown).
It is driven by G and B primary color signals, respectively. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112,
The R and B lights are refracted at 90 degrees, while the G light goes straight. Therefore, as a result of combining the images of each color, a color image is projected on a screen or the like via the projection lens 1114.

Here, each liquid crystal panel 1110R, 111
Focusing on the display images by 0B and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally inverted with respect to the display image by the liquid crystal panels 1110R and 1110B.

The liquid crystal panels 1110R, 1110B
And 1110G have a dichroic mirror 1108
Accordingly, light corresponding to each of the primary colors R, G, and B is incident, so that it is not necessary to provide a color filter.

<3-4-2: Mobile Computer>
Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 12 is a perspective view showing the configuration of the personal computer.
In the figure, a computer 1200 includes a keyboard 12
02 with the liquid crystal display unit 12
06. This liquid crystal display unit 12
Reference numeral 06 is configured by adding a backlight to the back surface of the liquid crystal panel 1005 described above.

<3-5-3: Mobile Phone> Further, an example in which this liquid crystal panel is applied to a mobile phone will be described.
FIG. 13 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 has a plurality of operation buttons 13.
02 and a reflective liquid crystal panel 1005. In this reflection type liquid crystal panel 100,
A front light is provided on the front surface as needed.

In addition to the electronic devices described with reference to FIGS. 11 to 13, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, Word processor, workstation, videophone, POS terminal,
A device including a touch panel is exemplified. It goes without saying that the present invention can be applied to these various electronic devices.

[0089]

As described above, according to the present invention, the amplitude of the signal input to the level conversion circuit can be made small, so that the power consumption can be reduced in the driving circuit for the signal and the driving power can be reduced. Smaller abilities can be used. Further, the circuit scale of the level conversion circuit itself can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a level conversion circuit 140A of the device.

FIG. 3 is a circuit diagram of a conversion unit Ua1 of the same level conversion circuit.

FIG. 4 is a truth table of the conversion unit Ua1.

FIG. 5 is a perspective view for explaining a structure of a liquid crystal panel in the device.

FIG. 6 is a timing chart showing the operation of the same device.

FIG. 7 is a timing chart of the same X shift register 110 ′.

FIG. 8 is a block diagram of a level conversion circuit 140B according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram of a conversion unit Ub1 of the same level conversion circuit.

FIG. 10 is a truth table of the conversion unit Ub1.

FIG. 11 is a cross-sectional view of a video projector as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 12 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 13 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 14 is a circuit diagram of a conversion unit constituting a conventional level conversion circuit.

[Explanation of symbols]

3a ... scanning line 6a ... data line 9a ... pixel electrode 50 ... TFT (switching element) D1 to Dn ... line-sequential image data (small amplitude image data) FLOD ... odd field signal (small amplitude field signal) FLEV: Even field signal (small amplitude field signal) Ca1, Ca2, Cb1, Cb2, Cc1, Cc2, C
1, C2 control signal (small amplitude control signal) 100 data line drive circuit 140A, 140B level conversion circuit 141 control section 142 level shift section 143 selection section 200 scanning line drive Circuit 300 Timing generation circuit Ga, Gb, Gc, Ge, Gd Transfer gate LSa, LSb, LSc, LSd, LSe Level shifter VK + First black level voltage (positive voltage), second black level Voltage VW: White level voltage (reference voltage) VK +, VK-: Second black level voltage (negative voltage)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623B F term (Reference) 2H093 NA16 NA33 NA43 NA56 NC11 NC13 NC21 NC22 NC23 NC26 NC34 ND06 ND39 ND42 NE06 NF11 NG02 5C006 AA15 BB16 BC12 BF24 BF26 BF46 FA43 FA47 5C080 AA10 BB05 DD22 DD26 FF11 JJ02 JJ03 JJ04 JJ05 JJ06 KK02 KK43

Claims (8)

[Claims] 1. An electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A level conversion circuit used in a driving circuit that performs a small amplitude control signal based on small amplitude image data corresponding to a certain data line and a small amplitude field signal indicating a field type; A level shifter that converts a logical amplitude level into a large amplitude based on the amplitude control signal to generate a large amplitude control signal, and a voltage selected from a plurality of voltages based on the large amplitude control signal. A level conversion circuit comprising: a selection unit that outputs the data to a data line. 2. The plurality of voltages are a reference voltage, a positive voltage having a potential difference on the positive side with the reference voltage as a center voltage, and a negative voltage having the potential difference on the negative side with the reference voltage as a center voltage. The control unit controls the selection unit to select the reference voltage when the small-amplitude image data indicates one digit, and controls the small-amplitude value when the small-amplitude image data indicates the other digit. 2. The selection unit according to claim 1, wherein the selection unit is controlled to select one of the positive polarity voltage and the negative polarity voltage according to whether an amplitude field signal indicates an odd field or an even field. 3. Level conversion circuit. A first transfer gate connected to a data line having one input / output terminal and the positive input voltage supplied to the other input / output terminal; A second transfer gate connected to the data line and supplying the reference voltage to the other input / output terminal; one input / output terminal connected to the data line and the negative input voltage supplied to the other input / output terminal And a third transfer gate, wherein the control unit transmits the large amplitude control signal to the first, second,
3. The level conversion circuit according to claim 2, wherein the selection unit is controlled by supplying the control signal to each control input terminal of a third transfer gate. 4. An electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A low-amplitude control signal that is generated based on small-amplitude image data corresponding to a certain data line and a small-amplitude field signal indicating a type of an odd field or an even field. And a power supply voltage, a reference voltage, a positive voltage having a potential difference on the positive side with the reference voltage as the center voltage, a negative voltage having the potential difference on the negative side with the reference voltage as the center voltage, A level shift unit that outputs a voltage selected from the power supply voltages to the data line based on the small amplitude control signal. Level conversion circuit. 5. The small-amplitude control signal, which is activated when the small-amplitude image data indicates one digit and the small-amplitude field signal indicates one field, the control unit includes: A second small amplitude control signal that is active when the amplitude image data indicates one digit and the small amplitude field signal indicates the other field; While the positive voltage is supplied, the reference voltage is supplied as a negative power supply voltage, and the positive voltage is output from an output terminal when the first small amplitude control signal is active, and the first small amplitude control signal is When the second small amplitude control signal is inactive and the second small amplitude control signal is active, the output terminal is set to a high impedance state, and the first small amplitude control signal is inactive and A first level shifter that outputs the reference voltage from an output terminal when the second small amplitude control signal is inactive, and the reference voltage is supplied as a positive power supply voltage, and the negative voltage is supplied as a negative power supply voltage, The negative voltage is output from an output terminal when the second small amplitude control signal is active, and the output terminal is in a high impedance state when the second small amplitude control signal is inactive and the first small amplitude control signal is active. A second level shifter that outputs the reference voltage from an output terminal when the first small amplitude control signal is inactive and the second small amplitude control signal is inactive; and an output terminal of the first level shifter, 5. The level conversion circuit according to claim 4, wherein a connection point between the second level shifter and an output terminal is connected to the data line. 6. An electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. 2. A data line driving circuit, comprising: a first conversion unit that converts input image data into dot-sequential image data; and a second conversion unit that converts each dot-sequential image data into line-sequential image data. A data line drive circuit comprising a plurality of level conversion circuits according to any one of claims 5 to 5, wherein the line-sequential image data is supplied to each level conversion circuit as the small-amplitude image data. 7. A pixel region having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. Item 6. A data line driving circuit according to item 6, a scanning line driving circuit for driving the scanning line, and a timing generating circuit for generating the small amplitude field signal and supplying the small amplitude field signal to the data line driving circuit. An electro-optical device characterized by the above-mentioned. 8. An electronic apparatus comprising the electro-optical device according to claim 8.