JPH096295A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an output circuit highly reliable and reduce the power consumption of a level shifter and decoder by making the signal amplitude of a level conversion circuit and decoder circuit in two kinds of positive polarity and negative polarity taking nearly the center between on-voltage or off-voltage of positive polarity and on voltage or off voltage of negative polarity of liquid crystal driving voltage as reference. SOLUTION: The liquid crystal display device has level shifters LVC 1, 2 which receive display data, decoders G1-G3 which receive output signals of the level shifters LVC 1, 2 and an a.c-converted signal, and an output circuits MOSFETQ1-Q3 which receive the output signal of the decoders G1-G3 to drive a signal line electrode of the liquid crystal display device. The signal amplitude of the level shifters LVC 1, 2 and that of the decoders G1-G3 are made two kinds of positive polarity and negative polarity taking nearly the center between on voltage or off voltage of positive polarity and on voltage or off voltage of negative polarity of liquid crystal driving voltage as reference. The signal amplitude formed by the level shifters LVC 1, 2 is reduced to almost half the output signal amplitude, and the power consumption can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal driving device and, for example, to a technique effectively used for forming a driving signal of a signal line in a liquid crystal display device having an active matrix structure.

[0002]

2. Description of the Related Art In a conventional liquid crystal drive circuit, for example, as shown in FIG. 4, display data D formed by a 5V system circuit such as a line memory is changed to a high level of 5V and a low level of -20V by a level shifter LVC. To the signal amplitude. The level-converted output is supplied to a decoder circuit composed of gate circuits G1 and G2 that receive an AC conversion signal M for AC driving the liquid crystal and a gate circuit G3 that receives an inverted output signal, and a MOSF that constitutes the output circuit.
It is transmitted to the gates of ETQ1 to Q3. As a liquid crystal driver having such a drive circuit, a semiconductor integrated circuit device “HD611” sold by Hitachi, Ltd.
04, HD66106 and HD66107 ”(Hitachi LC
D driver LSI data book, published in March 1987)
There is. Further, Japanese Patent Application Laid-Open No. 62-31825 discloses that an alternating signal M is supplied from a controller circuit to a liquid crystal drive circuit to drive a liquid crystal display element with alternating current.

[0003]

In the liquid crystal drive circuit described above, no consideration is given to the voltage amplitude of the drive voltage after the level shifter, and the gate breakdown voltage of the high breakdown voltage portion and the current consumption are not reasonable. is there. For example, MOSFE
As for TQ1, when it is in the ON state, a high voltage of about 21V is applied between the gate and the source, and when it is in the OFF state and the output is −15V, a high voltage of about 20V is applied between the gate and the drain. It takes. This gives the output M
The OSFETs Q1 to Q3 need to have a high breakdown voltage in their element structure. Further, the decoder circuit forms a signal with a large amplitude such as 5V and -20V as described above, and the consumption current increases due to a relatively large through current flowing when the signal changes.

An object of the present invention is to provide a liquid crystal drive circuit in which the voltage applied to the output MOSFET is reduced, and
An object of the present invention is to provide a liquid crystal driving device that realizes low power consumption.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a level conversion circuit that receives display data, a decoder circuit that receives the output signal of this level conversion circuit and an AC signal, and an output circuit that receives the output signal of this decoder circuit and drives the signal line electrodes of the liquid crystal display device. And a signal amplitude of the level conversion circuit and a decoder circuit that receives the output signal of the level conversion circuit between the positive and negative on-voltages and negative and on-voltages and off-voltages of the liquid crystal drive voltage, respectively. There are two types of positive and negative polarities based on the approximate center.

According to the above means, the signal amplitude formed by the level shifter can be reduced to almost half of the output signal amplitude, the voltage applied to the output MOSFET can be reduced accordingly, and the consumption in the decoder circuit and the level shifter can be reduced. The current can be reduced.

[0008]

1 is a circuit diagram of an embodiment of a liquid crystal drive circuit according to the present invention. Each circuit block and circuit element in FIG.
(OS) Depending on the manufacturing technology of the integrated circuit, it is formed on one semiconductor substrate such as, but not limited to, single crystal silicon.

A liquid crystal drive circuit of the TFT active matrix type will be described below.

In this embodiment, the following voltages are set in order to reduce the voltage applied to the output MOSFET. Although not particularly limited, the off-voltage of the liquid crystal is set to the ground potential such as 0V. With this ground potential as a reference, the positive lighting level written in the liquid crystal is + 8V.
Then, the negative lighting level is set to -8V. The positive and negative non-lighting levels are set to 0V. A P-channel type output MOSFET Q1 and N-channel type output MOSFETs Q2 and Q3 are provided corresponding to the liquid crystal drive signal based on the three-valued level. The source of the P-channel type output MOSFET Q1 is +8.
It is connected to a positive voltage terminal V1 such as V. The source of the N-channel type output MOSFET Q2 is -8.
It is connected to a negative voltage terminal V2 such as V. The source of the N-channel type output MOSFET Q3 is connected to the ground potential terminal V3 (0V).

In this embodiment, a P channel type output MO
To turn on and off SFETQ1, 0V
And a high level such as 12 V. In other words, the intermediate voltage 0 between the positive ON voltage V1 and the negative ON voltage is 0.
High level is 12V and low level is 0V based on V
A drive voltage having a signal amplitude such as is supplied to its gate. Therefore, the gate circuit G1 which forms the drive voltage transmitted to the gate of the MOSFET Q1 has a CMOS configuration NAND (N) in which the operating voltage is + 12V and the ground potential.
AND) gate circuit.

The gate circuit G1 is formed by the same level shifter as the non-inverted output signal Q of the level shifter LVC1 for converting the 5V system pixel data D including a line memory or the like into the 12V system signal as described above. The converted AC signal M1 is supplied. The gate circuit G1 has a logic "1" indicating that the display data D (non-inverted output signal Q of the level shifter LVC1) is turned on, and the alternating signal M
When 1 is a high level logic "1" indicating positive polarity,
It becomes a low level like the ground potential of the circuit and turns on the P-channel type output MOSFET Q1. In response to this, the drive output signal Y is set to a positive high level (lighting level) such as + 8V. Even when the display data D is a logic "1" which means lighting, the gate circuit G1 is a low level logic "0" indicating a negative polarity or the alternating signal M1 indicates a positive polarity. Even if it is at a high level, when the display data D is a logic "0" which means non-lighting, a high level output signal such as 12V is formed and a P channel type output MOSF is formed.
Turn off ETQ1.

In order to turn on and off the N-channel type output MOSFET Q2, basically, a high level signal such as a ground potential and a low level signal of -8 V or less may be formed. However, the display data D is a 5V system signal, and cannot be converted into the above discontinuous level. Therefore, 5 which is the high level of 5V system
Taking V as the reference potential, and a high level like 5V, -1
Form a high level such as 3V. Therefore, this M
The gate circuit G2 that forms the drive voltage transmitted to the gate of the OSFET Q2 is composed of a NOR gate circuit of CMOS configuration having operating voltages of + 5V and -13V. The gate circuit G2 has an inverted output signal bar Q of a level shifter LVC2 for converting the 5V system pixel data D including a line memory or the like into a signal having the above-mentioned amplitude at its input, and an alternating current formed by a similar level shifter. The signal M2 is supplied. The gate circuit G2 displays the display data D
Is a logic "1" which means lighting, that is, the inverted output signal Q of the level shifter LVC2 is a low level logic "0".
In addition, when the AC signal M2 is low level ethics "0" indicating negative polarity, it becomes a high level such as + 5V to turn on the N-channel type output MOSFET Q2. In response to this, the drive output signal Y is set to a negative high level (lighting level) such as -8V. Even when the display data D is the logic "1" which means the lighting, the gate circuit G2 is at the high level logic "1" which indicates the positive polarity, or the alternating signal M2.
Is -13V when the display data D is a logic "0" meaning non-lighting, even when is a low level indicating negative polarity.
A low-level output signal like that is formed to turn off the N-channel type output MOSFET Q2.

In order to turn on and off the N-channel type output MOSFET Q3, the N-channel M
A drive signal having the same signal amplitude as the OSFET Q2 can be used. Therefore, the gate circuit G3 that forms the drive voltage transmitted to the gate of the MOSFET Q3 is composed of an inverter circuit of CMOS configuration that uses + 5V and -13V as operating voltages. The gate circuit G3 forms a drive signal instructing non-lighting corresponding to positive and negative polarities. Therefore, the gate circuit G3 receives at its input the non-inverted output signal Q of the level shifter LVC2 which converts the 5V system pixel data D consisting of a line memory or the like into a signal of the above amplitude, and it is not lit. Is low level regardless of the alternating signal M, a high level output signal such as + 5V is formed and the N-channel type output MOSFET Q3 is turned on. In response to this, the drive output signal Y is set to a low level (non-lighting level) like the ground potential. In this embodiment, since the positive and negative non-lighting levels are set to the common ground potential, the alternating signal M2 is set as described above.
Level shifter LVC that receives display data D regardless of
The output MOSFET Q is provided only by the non-inverted output Q of 2.
3 switch control is performed.

FIG. 2 shows a circuit diagram of an embodiment of the level shifter. In this embodiment, as shown in FIG. 1, a level shifter for converting a 5V system signal into a 12V system signal is shown as an example. That is, the 5V signal D is supplied to the gate of the N-channel MOSFET Q5 whose source is coupled to the ground potential 0V. The signal D is inverted by the 5V inverter circuit N,
Similarly to the above, the source is supplied to the gate of the N-channel MOSFET Q7 coupled to the ground potential 0V. As a result, the MOSFETs Q5 and Q7 are complementarily turned on according to the high level and the low level of the signal D. The drains of these MOSFETs Q5 and Q7 are provided with latch-type P-channel MOSFETs Q4 and Q6 whose gates and drains are cross-connected. An operating voltage such as 12V is supplied to the sources of these P-channel MOSFETs Q4 and Q6.

The level conversion operation of this embodiment is as follows. N-channel MOS when signal D is high level
FETQ5 is turned on, N-channel MOSFETQ
7 is off. Therefore, P channel MO
S-channel Q4 turned off, P-channel MOSFET
Q6 is turned on. At this time, the non-inverting output Q outputs a low level such as the ground potential of the circuit depending on the ON state of the N-channel MOSFET Q5, and the inverting output bar Q outputs a high level such as 12V depending on the ON state of the P-channel MOSFET Q6. It

When the signal D changes from high level to low level, the N-channel MOSFET Q5 is turned off,
P-channel MOSFET Q7 is turned on. Since the conductance of the N-channel MOSFET Q7 is set larger than that of the P-channel MOSFET Q6, the non-inverting output Q changes from the high level to the low level as described above. In response to the change of the signal Q to the low level, the P-channel MOSFET Q4 changes from the off state to the on state, and the inverted output bar Q is pulled up from the low level to the high level. As a result, the P-channel MOSFET Q6 is turned off. As a result, the output signal is reversed from the above state and the inverted output bar Q
Changes to a high level such as 12 V, and the non-inverted output Q changes to a low level such as the ground potential.

In the case of converting a 5V system signal such as 5V and 0V like the level shifter LVC2 into a signal such as 5V and -13V, the P channel MOSFET is complementarily switch controlled by the signal D. However, a latch type N-channel MOSFET may be provided at the drain thereof. In this case, the conductance of the P-channel MOSFET is set larger than that of the N-channel MOSFET, contrary to the above embodiment.

In the liquid crystal drive circuit of this embodiment, the output MOS
Since the voltage applied between the gate and the source or drain of the FET is 13V to 7V, which can be greatly reduced as compared with the conventional circuit, the burden of the gate breakdown voltage in the high breakdown voltage portion can be reduced and the reliability can be improved.

However, a high voltage of 21 V to 20 V is applied between the gate and drain of the MOSFET in the off state in the output stage MOSFET.

In the level shifter and the decoder for decoding the output signal and forming the switching control signal of the output MOSFET, the operating voltage can be reduced as described above. Since the power consumption of the CMOS circuit is proportional to the square of the voltage amplitude of the gate, the power consumption can be reduced by about 60% as compared with the conventional circuit as described above.

The effects of the operation obtained from the above embodiment are as follows.
It is as follows. That is, (1) a level conversion circuit that receives display data, a decoder circuit that receives the output signal of this level conversion circuit and an AC signal, and a signal line electrode of the liquid crystal display device that receives the output signal of this decoder circuit. In the liquid crystal drive circuit having an output circuit for outputting the signal level, the signal amplitudes of the level conversion circuit and the decoder circuit that receives the output signal are set to approximately the center of the positive ON voltage and the negative ON voltage of the liquid crystal drive voltage, respectively. By using two types of positive polarity and negative polarity as the reference, the signal amplitude formed by the level shifter becomes
The effect is that the output signal amplitude can be reduced to almost half, the voltage applied to the gate of the output MOSFET can be reduced, and the current consumption in the decoder circuit and the level shifter can be reduced accordingly.

(2) Due to the above (1), it is possible to obtain an effect that a highly reliable drive circuit can be obtained after reducing the gate voltage.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
The drive voltage of the liquid crystal may be a signal having four values as shown in FIG. That is, the positive ON voltage + ON (V
1), positive polarity OFF state + OFF (V2), negative polarity ON voltage -ON (V3), negative polarity OFF state -OFF (V
4). That is, in such a level setting, + OFF and -OFF AC signals are supplied to the liquid crystal even when the lamp is not lit.

Further, the center of the driving voltage does not have to be the ground potential as in the above embodiment. Any voltage may be used as long as it is grounded at approximately the center of the positive or negative ON voltage or OFF voltage. However, in this case, it may be necessary to perform the level shifter for both the high level and the low level from the binary data D of 5V and 0V as described above.

The present invention can be similarly applied to a liquid crystal display device having a simple matrix structure in addition to the liquid crystal display device having an active matrix structure as described above.

[0027]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a level conversion circuit that receives display data, a decoder circuit that receives the output signal of this level conversion circuit and an AC signal, and an output circuit that receives the output signal of this decoder circuit and drives the signal line electrodes of the liquid crystal display device. And a signal amplitude of the level conversion circuit and a decoder circuit that receives the output signal of the level conversion circuit between the positive and negative on-voltages and negative and on-voltages and off-voltages of the liquid crystal drive voltage, respectively. By adopting two types of positive polarity and negative polarity based on the approximate center, the signal amplitude formed by the level shifter can be reduced to almost half of the output signal amplitude, and the high reliability of the output circuit and the level shifter and decoder are achieved. Low power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a liquid crystal drive circuit according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a level shifter.

FIG. 3 is a level setting diagram of an output signal showing another embodiment of the liquid crystal drive circuit according to the present invention.

FIG. 4 is a circuit diagram showing an example of a conventional technique.

[Explanation of symbols]

LVC to LVC2 ... Level shifter, G1 to G3 ... Gate circuit (decoder), N ... Inverter circuit

Claims (2)

[Claims] 1. A liquid crystal display device comprising a liquid crystal display element, a drive circuit for driving the liquid crystal display element, and a control circuit for controlling the drive circuit, wherein the liquid crystal display element has a first lighting voltage level, The driving circuit is driven by the liquid crystal driving signal having the second lighting voltage level, and the driving circuit outputs the first lighting voltage level and the second lighting voltage level. Output circuit, a first level shifter that outputs a first voltage level that drives the first output circuit, and a second level shifter that outputs a second voltage level that drives the second output circuit. And a control signal output from the control circuit for switching between outputs from the first output circuit and the second output circuit. 2. A liquid crystal display device comprising a liquid crystal display element, a drive circuit for driving the liquid crystal display element, and a power supply circuit for supplying a voltage to the drive circuit.
Driven by the liquid crystal drive signal of the second lighting voltage level, the driving circuit outputs the first lighting voltage level of the first output circuit, and the second lighting circuit. A second output circuit that outputs a voltage level, a first level shifter that outputs a first voltage level that drives the first output circuit, and a second voltage level that drives the second output circuit. A second level shifter for outputting, and a voltage corresponding to the first lighting voltage level and a voltage corresponding to the second lighting voltage level are supplied from the power supply circuit to the drive circuit. A liquid crystal display device characterized by the above.