JP2011090327A - Video signal conversion device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video signal conversion device which can maintain a synchronization signal of an output side of the device almost constant regardless of scaling by scan line conversion. <P>SOLUTION: When a scan line conversion processor 4 is arranged after a memory controller 2, regardless of whether vertical frequency conversion is performed or not, a horizontal synchronization signal H2 which becomes a reference pulse of an output side of the memory controller 2 is remade by an H counter 76, and a reference pulse of a phase locked loop (PLL) circuit 72 which generates a third clock CK3 by an H counter 77 which is different from the H counter 76 is generated. The H counters 76 and 77, and a frequency dividing ratio counter 74 for determining a frequency dividing ratio of the PLL circuit 72 are reset by a vertical synchronization signal V2 which becomes the reference pulse after the output side of the memory controller 2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a video signal conversion device that converts a video signal into a video signal suitable for a display device, and more particularly to a video signal conversion device that converts a video signal into a video signal suitable for a display device that performs matrix display. .

  Dot matrix display display panels include PDP (plasma display panel) and liquid crystal panel. IP (interlace / progressive) conversion, scanning line conversion, horizontal pixel conversion are essential signal processing technologies for these display panels. And vertical frequency conversion.

  IP conversion is a process of converting an interlace signal into a progressive signal. Scan line conversion is a process of performing enlargement and reduction in the vertical direction of a display image. Horizontal pixel conversion is a process of performing enlargement and reduction in the horizontal direction of a display image. Each of these conversions is an indispensable technique for a dot matrix display device in which the number of pixels in the horizontal and vertical directions is determined.

  The vertical frequency conversion is a process for converting the vertical frequency of the video signal to a vertical frequency suitable for the display device. In the PDP, the gradation expression method and its operation speed are limited in the liquid crystal panel. Due to limitations, the vertical frequency is most preferably 60 Hz. Therefore, when the vertical frequency of the video signal is higher than 60 Hz, a vertical frequency conversion circuit that converts this vertical frequency to 60 Hz is very useful.

  FIG. 18 is a block diagram showing a configuration of a conventional video signal conversion apparatus that performs scanning line conversion without performing vertical frequency conversion.

  18 includes a field memory 201, a memory control processing unit 202, a scanning line conversion processing unit 203, PLL (Phase Locked Loop) circuits 211 and 212, frequency division ratio counters 213 and 214, and a crystal oscillator 215. H counter 216 and V counter 217.

  The PLL circuit 211 receives a horizontal synchronization signal HS of the digital video signal DV from the outside, and receives the same clock CK1 as a sampling clock of an AD (analog / digital) conversion circuit (not shown) provided in the preceding stage of the memory control processing unit 202. generate. The frequency division ratio counter 213 determines the frequency division ratio of the PLL circuit 211, that is, divides the first clock CK1, generates a feedback pulse to the PLL circuit 211, and inputs the pulse to the memory control processing unit 202. Is output to the memory control processing unit 202 as a horizontal synchronization signal H1 serving as a reference pulse on the side.

  The horizontal synchronizing signal H1 is used as a horizontal synchronizing signal H2 that becomes a reference pulse before scanning line conversion, that is, an output side reference pulse of the memory control processing unit 202 and an input side reference pulse of the scanning line conversion processing unit 203, and a third clock. It is also used as a reference pulse for the PLL circuit 212 that generates CK3.

  The PLL circuit 212 receives the horizontal synchronization signal H1 as a reference pulse, and generates a third clock CK3 that is used to create a reference pulse on the output side of the scanning line conversion processing unit 203. The division ratio counter 214 determines the division ratio of the PLL circuit 212, that is, divides the third clock CK3, generates a feedback pulse to the PLL circuit 212, and converts the pulse into a scan line, that is, a scan line. The signal is output to the scanning line conversion processing unit 203 as a horizontal synchronization signal H3 that serves as a reference pulse on the output side of the conversion processing unit 203.

  As the vertical synchronization signals V1 to V3, the vertical synchronization signal VS of the digital video signal DV input from the outside to the video signal converter is used. Since the video signal converter shown in FIG. 18 does not perform vertical frequency conversion, the path indicated by the broken line in FIG. 18 is not used, and the internal crystal oscillator 215, H counter 216, and V counter 217 are used. Not.

  The memory control processing unit 202 writes the externally input digital video signal DV to the field memory 201 in accordance with the horizontal synchronization signal H1 and the vertical synchronization signal V1, and writes the written digital video signal to the horizontal synchronization signal H2 and the vertical synchronization signal V2. In response to the data from the field memory 201 and output to the scanning line conversion processing unit 203. The scanning line conversion processing unit 203 receives the video signal read from the field memory 201 in accordance with the horizontal synchronizing signal H2 and the vertical synchronizing signal V2, converts the number of scanning lines of the input video signal, and generates a horizontal synchronizing signal. Output according to H3 and vertical synchronizing signal V3.

  With the above configuration, the video signal conversion apparatus shown in FIG. 18 performs only scanning line conversion without performing vertical frequency conversion. It should be noted that such a circuit configuration is required when the video signal is a moving image, and when the motion of the moving image is not allowed to be distorted due to omission of a field or writing twice. is there.

  FIG. 19 is a block diagram showing a configuration of a conventional video signal conversion apparatus that performs vertical frequency conversion and scanning line conversion.

  The basic configuration of the video signal converter shown in FIG. 19 is the same as that of the video signal converter shown in FIG. 18, but the video signal converter shown in FIG. 19 does not use the path indicated by the broken line in FIG. First, a crystal oscillator 215, an H counter 216, and a V counter 217 are used.

  The PLL circuit 211 and the frequency division ratio counter 213 are the same as the PLL circuit 211 and the frequency division ratio counter 213 shown in FIG.

  The crystal oscillator 215 outputs a second clock CK2 for performing processing inside the apparatus, and the H counter 216 divides the second clock CK2, and before scanning line conversion, that is, on the output side of the memory control processing unit 202 The horizontal synchronization signal H2 that is the reference pulse and the reference pulse on the input side of the scanning line conversion processing unit 203 is output. The V counter 217 divides the horizontal synchronizing signal H2 output from the H counter 216, and before scanning line conversion, that is, the reference pulse on the output side of the memory control processing unit 202 and the reference pulse on the input side of the scanning line conversion processing unit 203. The vertical synchronizing signal V2 is output. The vertical synchronizing signal V2 is also used as a vertical synchronizing signal V3 that becomes a reference pulse on the output side of the scanning line conversion processing unit 203 after the scanning line conversion.

  The PLL circuit 212 receives the horizontal synchronization signal H2 as a reference pulse, and generates a third clock CK3 that is used to create a reference pulse on the output side of the scanning line conversion processing unit 203. The division ratio counter 214 determines the division ratio of the PLL circuit 212, that is, divides the third clock CK3, generates a feedback pulse to the PLL circuit 212, and converts the pulse into a scan line, that is, a scan line. The signal is output to the scanning line conversion processing unit 203 as a horizontal synchronization signal H3 that serves as a reference pulse on the output side of the conversion processing unit 203.

  The memory control processing unit 202 writes the externally input digital video signal DV to the field memory 201 in accordance with the horizontal synchronization signal H1 and the vertical synchronization signal V1, and writes the written digital video signal to the horizontal synchronization signal H2 and the vertical synchronization signal V2. Accordingly, the vertical frequency conversion is performed by reading from the field memory 201 and the converted video signal is output to the scanning line conversion processing unit 203. The scanning line conversion processing unit 203 receives a video signal that has been subjected to vertical frequency conversion in accordance with the horizontal synchronizing signal H2 and the vertical synchronizing signal V2, converts the number of scanning lines of the input video signal, and converts the horizontal synchronizing signal H3 and the vertical synchronizing signal H3 to vertical. Output in response to the synchronization signal V3.

  With the above configuration, the video signal conversion apparatus shown in FIG. 19 performs vertical frequency conversion and scanning line conversion. When performing such scanning line conversion, the horizontal synchronization signals H2 and H3 before and after the scanning line conversion have the same frequency as the scanning line conversion rate in order to minimize the storage capacity of the line memory used for the scanning line conversion. Set to a ratio. For example, in the case of 2: 3 scanning line conversion, that is, when the output of 3 lines is synthesized from the input of 2 lines, the frequency ratio between the horizontal synchronization signal H2 on the input side and the horizontal synchronization signal H3 on the output side is also 2: 3, The frequency of the horizontal synchronization signal H3 on the output side becomes faster.

  FIG. 20 shows a conventional video signal conversion apparatus as shown in FIG. 19 which is created by LSI (Large Scale Integrated Circuit), and the two created LSIs are operated in synchronization to perform vertical frequency conversion and scanning line conversion. It is a block diagram which shows the structure of a video signal converter.

  The video signal conversion device shown in FIG. 20 includes two LSIs 301 and 302 and a crystal oscillator 303. In the LSIs 301 and 302, only the H counter 216 and the V counter 217 are illustrated, and other blocks are not illustrated.

  The two LSIs 301 and 302 are LSIs created by omitting the crystal oscillator 215 from the video signal converter as shown in FIG. The crystal oscillator 303 is connected to the H counter 216 of the LSI 301. The H counter 216 and V counter 217 of the LSI 302 are not used, and the horizontal synchronization signal H2 and vertical synchronization output from the H counter 216 and V counter 217 of the LSI 301, respectively. The signal V2 is supplied to the LSI 302.

  Accordingly, the horizontal synchronization signal and the vertical synchronization signal are supplied to the two LSIs 301 and 302 in a synchronized state, and the two LSIs 301 and 302 can be operated in parallel in synchronization.

  With the above configuration, when the number of pixels of the display panel increases, the amount of data written to the field memory increases, and one LSI is insufficient, or the conversion speed is slow for one LSI, 2 The data can be divided by the LSIs 301 and 302 and the vertical frequency conversion and the scanning line conversion can be performed in synchronization, and the video signal displayed on the display panel can be output in synchronization.

Japanese Patent Laid-Open No. 10-322626 Japanese Patent Laid-Open No. 9-291652

  In the conventional video signal conversion apparatus shown in FIGS. 18 and 19, since the memory control processing unit 202 connected to the field memory 201 is arranged in the front stage of the apparatus, the video signal is captured in advance with a small number of horizontal pixels, and the memory The amount of data stored in the field memory 201 by suppressing the amount of information at the time of AD (analog / digital) conversion before the control processing unit 202 and performing enlargement processing as horizontal pixel conversion after the scanning line conversion processing unit 203 Can be reduced. However, in this case, the amount of information before conversion decreases, and the image quality of the finally converted video signal deteriorates.

  Also, when performing enlargement processing as scanning line conversion, the amount of information tends to increase, so the amount of data stored in the field memory 201 can be reduced. However, in the case of reduction processing, the amount of information is ultimately reduced. However, the data having a large amount of information before conversion is stored in the field memory 201, and the storage capacity of the field memory 201 cannot be used effectively.

  In addition, since the scanning line conversion processing unit 203 is provided at the subsequent stage of the memory control processing unit 202, when the enlargement processing is performed as the scanning line conversion processing regardless of the presence or absence of the vertical frequency conversion, the horizontal synchronization after the scanning line conversion is performed. The frequency of the signal increases. For example, when the 1: 2 enlargement process is performed, the frequency of the horizontal synchronization signal after the scanning line conversion is doubled, so that the frequency of the horizontal synchronization signal and the clock on the output side of the apparatus is increased. For this reason, in order to operate the entire system including the display panel satisfactorily, the operating frequency range of the signal processing circuit and the driving circuit in the subsequent stage of the scanning line conversion processing unit 203 must be widened. On the other hand, if the range of the corresponding video signal and the expansion and reduction range of the scanning line conversion are narrowed, the performance of the apparatus is lowered.

  Also, if the last horizontal period of the vertical period is shortened and an abnormal vertical synchronization signal is supplied to each block, processing in each block may not be possible or malfunction may occur. Further, when the last horizontal period of the vertical period becomes extremely short and the vertical synchronization signals are generated with a shift of one horizontal period, processing in each block becomes impossible or malfunctions.

  In the conventional video signal conversion apparatus shown in FIG. 20, since the horizontal synchronization signal H2 and the vertical synchronization signal V2 after the vertical frequency conversion must be supplied from the LSI 301 to the LSI 302, the wiring on the printed circuit board to which the LSI 301 and the LSI 302 are attached. Will increase. Further, when the number of LSIs to which the horizontal synchronization signal H2 and the vertical synchronization signal V2 are supplied increases, the horizontal synchronization signal H2 and the vertical synchronization signal V2 are delayed due to the wiring capacity and pin capacity of each LSI, and a plurality of LSIs can be accurately set. It becomes impossible to operate in synchronism, and the video output on the display cannot be output completely in synchronism.

  An object of the present invention is to provide a video signal conversion apparatus capable of keeping the synchronization signal on the output side of the apparatus substantially constant regardless of enlargement / reduction by scanning line conversion.

  Another object of the present invention is to provide a video signal converter capable of generating a vertical synchronizing signal at an accurate timing and always operating stably.

  Still another object of the present invention is to provide a video signal conversion apparatus that can operate a plurality of integrated circuits in synchronization with each other without passing a synchronization signal between the plurality of integrated circuits.

(1) First invention A video signal converter according to a first invention is a video signal converter for converting an input video signal into a video signal suitable for a display device, and storing means for storing the video signal. The input video signal is stored in the storage means, the vertical frequency conversion means for converting the vertical frequency of the video signal stored in the storage means, and the number of scanning lines of the video signal output from the vertical frequency conversion means A scanning line conversion means for conversion, and a synchronization control means for outputting a synchronization control signal for controlling operations of the vertical frequency conversion means and the scanning line conversion means to the vertical frequency conversion means and the scanning line conversion means, and a synchronization control means. Are a first horizontal synchronizing signal generating means for generating a horizontal synchronizing signal serving as a reference on the output side of the vertical frequency converting means and the input side of the scanning line converting means, and a first horizontal synchronizing signal generating means. Vertical synchronizing signal generating means for generating a vertical synchronizing signal using the horizontal synchronizing signal generated from the second scanning signal converting means, second horizontal synchronizing signal generating means for generating a horizontal synchronizing signal serving as a reference on the output side of the scanning line converting means, The vertical synchronization signal of the video signal input to the vertical frequency conversion means and the vertical synchronization signal output from the vertical synchronization signal generation means are received, and the vertical serving as a reference on the output side of the vertical frequency conversion means and the input side of the scanning line conversion means As the synchronizing signal, when the vertical frequency converting means performs vertical frequency conversion, the vertical synchronizing signal of the vertical synchronizing signal generating means is selected and output, and when the vertical frequency converting means does not perform vertical frequency conversion, the vertical frequency converting means Selecting means for selecting and outputting a vertical synchronizing signal of an input video signal, and the first and second horizontal synchronizing signal generating means are vertical outputs outputted from the selecting means. It is those reset by the synchronization signal.

  In the video signal conversion apparatus according to the first aspect of the present invention, when the scanning line conversion means is arranged after the vertical frequency conversion means, the vertical frequency conversion is performed by the first horizontal synchronizing signal generation means regardless of the presence or absence of the vertical frequency conversion. Generating a horizontal synchronizing signal as a reference on the output side of the means and the input side of the scanning line converting means, and outputting the scanning line converting means by a second horizontal synchronizing signal generating means different from the first horizontal synchronizing signal generating means A horizontal synchronizing signal serving as a reference on the side is generated, and the first and second horizontal synchronizing signal generating means are reset by the vertical synchronizing signal on and after the output side of the vertical frequency converting means. Therefore, the synchronization signal on the output side of the apparatus can be kept substantially constant regardless of enlargement / reduction by scanning line conversion.

(2) Second invention The video signal converter according to the second invention is the configuration of the video signal converter according to the first invention, wherein the first horizontal synchronizing signal generating means is the output side of the vertical frequency converting means. And a first counter that generates a horizontal synchronization signal that serves as a reference on the input side of the scanning line conversion means, and the vertical synchronization signal generation means divides the horizontal synchronization signal generated from the first counter to perform vertical synchronization. A second counter for generating a signal, and a second horizontal synchronization signal generating means determines a third counter for generating a reference pulse of the PLL circuit for generating a predetermined clock and a frequency division ratio of the PLL circuit. And a fourth counter that divides the clock output from the PLL circuit and generates a horizontal synchronizing signal serving as a reference on the output side of the scanning line conversion means. The first and third counters are selected from the selection means. output It is reset by the vertical synchronization signal.

  In this case, the first counter regenerates a horizontal synchronizing signal that serves as a reference for the output side of the vertical frequency conversion means and the input side of the scanning line conversion means, and a third counter different from the first counter serves as a reference for the PLL circuit. Since the pulse is generated and the first and third counters are reset by the vertical synchronizing signal after the output side of the vertical frequency conversion means, the enlargement and reduction processing by the scanning line conversion means is not performed. It becomes possible to keep the horizontal synchronizing signal and the clock substantially constant. In addition, since the setting of each counter after the vertical frequency conversion is always determined only by the conversion ratio in the scanning line conversion regardless of the frequency of the input video signal and the number of pixels, the setting of each counter becomes easy. .

(3) Third invention A video signal conversion device according to a third invention is the configuration of the video signal conversion device according to the second invention, wherein the fourth counter is reset by a vertical synchronization signal output from the selection means. Is done.

  In this case, since the third and fourth counters that output the reference pulse and the feedback pulse of the PLL circuit can be reset at the same time, the oscillation operation of the PLL circuit can be stabilized.

(4) Fourth invention A video signal converter according to a fourth invention is a video signal converter for converting an input video signal into a video signal suitable for a display device, and scanning the input video signal. A scanning line conversion means for converting the number of lines, a storage means for storing the video signal, a video signal output from the scanning line conversion means is stored in the storage means, and a vertical frequency of the video signal stored in the storage means is set. And a synchronization control means for outputting a synchronization control signal for controlling operations of the scanning line conversion means and the vertical frequency conversion means to the scanning line conversion means and the vertical frequency conversion means. Includes a first horizontal synchronizing signal generating means for generating a horizontal synchronizing signal serving as a reference on the output side of the scanning line converting means and the input side of the vertical frequency converting means, and a pulse for generating a predetermined reference pulse. Generating means, vertical synchronizing signal generating means for generating a vertical synchronizing signal using the reference pulse generated from the pulse generating means, and reference on the output side of the vertical frequency converting means using the reference pulse generated from the pulse generating means A second horizontal synchronizing signal generating means for generating a horizontal synchronizing signal, a vertical synchronizing signal of a video signal inputted to the scanning line converting means and a vertical synchronizing signal outputted from the vertical synchronizing signal generating means, and receiving a vertical frequency When the vertical frequency conversion means performs vertical frequency conversion as the reference vertical synchronization signal on the output side of the conversion means, the vertical synchronization signal of the vertical synchronization signal generation means is selected and output, and the vertical frequency conversion means is the vertical frequency conversion Selecting means for selecting and outputting the vertical synchronizing signal of the video signal input to the scanning line converting means when the first horizontal synchronizing signal is not generated. It is reset by the vertical synchronizing signal of the video signal inputted to the scanning line conversion means, pulse generating means is intended to be reset by the vertical synchronizing signal outputted from the selection means.

  In the video signal conversion apparatus according to the fourth aspect of the invention, when the vertical frequency conversion means is arranged after the scanning line conversion means, the first horizontal synchronizing signal generation means performs the scanning line conversion regardless of the presence or absence of the vertical frequency conversion. A horizontal synchronizing signal serving as a reference on the output side of the scanning line converting means and on the input side of the vertical frequency converting means is generated at a frequency corresponding to the conversion rate of the second horizontal synchronizing signal and generated from the pulse generating means by the second horizontal synchronizing signal generating means. Using the reference pulse, a horizontal synchronizing signal that is a reference on the output side of the vertical frequency converting means is generated, and the first horizontal synchronizing signal generating means is reset by the vertical synchronizing signal of the video signal input to the scanning line converting means, The pulse generating means is reset by the vertical synchronizing signal output from the selecting means. Therefore, the vertical frequency conversion can be performed after the scanning line conversion, and the synchronizing signal on the output side of the apparatus can be kept substantially constant regardless of the enlargement / reduction by the scanning line conversion.

(5) Fifth Invention A video signal conversion device according to a fifth invention is the configuration of the video signal conversion device according to the fourth invention, wherein the first horizontal synchronizing signal generating means is the output side of the scanning line conversion means. And a first counter that generates a horizontal synchronizing signal that serves as a reference on the input side of the vertical frequency converting means, and the pulse generating means generates a horizontal synchronizing signal that serves as a reference pulse of a PLL circuit that generates a predetermined clock. The vertical synchronization signal generation means includes a third counter that divides the horizontal synchronization signal generated from the second counter to generate a vertical synchronization signal, and includes a second horizontal synchronization signal generation means. Includes a fourth counter that determines the frequency division ratio of the PLL circuit, divides the clock output from the PLL circuit, and generates a horizontal synchronization signal that serves as a reference on the output side of the vertical frequency conversion means. The 1 counter is reset by the vertical synchronization signal of the video signal input to the scanning line conversion means, and the second counter is reset by the vertical synchronization signal output from the selection means.

  In this case, a first counter that generates a horizontal synchronizing signal at a frequency corresponding to the conversion rate of the scanning line conversion and a second counter that generates a reference pulse on the output side of the vertical frequency converting means are provided. The output of the counter is used as a reference pulse of a PLL circuit that outputs a clock input to the fourth counter, the first counter is reset by a vertical synchronizing signal of the video signal input to the scanning line conversion means, and a vertical frequency conversion means Since the second counter is reset by the vertical synchronization signal on the output side, vertical frequency conversion can be performed after the scanning line conversion, and the output side of the apparatus can be performed regardless of the enlargement and reduction processing by the scanning line conversion means. It is possible to keep the horizontal synchronizing signal and the clock of the signal substantially constant.

(6) Sixth Invention A video signal converter according to a sixth invention is the video signal converter according to the fifth invention, wherein the fourth counter is reset by a vertical synchronization signal output from the selection means. Is done.

  In this case, since the second and fourth counters that output the reference pulse and the feedback pulse of the PLL circuit can be reset at the same time, the oscillation operation of the PLL circuit can be stabilized.

(7) Seventh Invention A video signal converter according to a seventh invention is a video signal converter for converting an input video signal into a video signal suitable for a display device, and storing means for storing the video signal. The operations of the vertical frequency converting means for converting the vertical frequency of the video signal stored in the storage means, the scanning line converting means for converting the number of scanning lines of the video signal, and the operations of the vertical frequency converting means and the scanning line converting means. And a synchronization control means for outputting a synchronization control signal for control to the vertical frequency conversion means and the scanning line conversion means. The synchronization control means generates a horizontal synchronization signal that is reset by the vertical synchronization signal, and also generates a horizontal synchronization signal. Includes a horizontal synchronizing signal generating means for extracting the last pulse immediately before the horizontal synchronizing signal is reset by the vertical synchronizing signal.

  In the video signal converter according to the seventh aspect of the invention, a horizontal synchronizing signal that is reset by the vertical synchronizing signal is generated, and the last pulse immediately before the horizontal synchronizing signal is reset by the vertical synchronizing signal is extracted from the horizontal synchronizing signal. Therefore, the width of the last horizontal period can be sufficiently widened, and the vertical synchronization signal can be generated at an accurate timing to always operate stably.

(8) Eighth Invention The video signal converter according to the eighth invention is the video signal converter according to the seventh invention, wherein the horizontal synchronizing signal generating means counts the input pulses at a predetermined timing. Pulse generating means for generating pulses, pulses output from the pulse generating means are counted, maximum value detecting means for detecting the last pulse with the maximum counter value, and pulses output from the pulse generating means are delayed The delay means for generating the delay pulse and the extraction means for extracting the delay pulse obtained by delaying the last pulse detected by the maximum value detection means from the delay pulse output from the delay means.

  In this case, the pulse generation means for counting the input pulses and generating the pulse, and the last pulse with the maximum counter value of the pulse output from the pulse generation means are detected, and the pulse output from the pulse generation means is detected. Since the delayed pulse of the last detected pulse is extracted from the delayed delayed pulse, the last pulse just before the horizontal synchronization signal is reset by the vertical synchronization signal can be extracted, and the width of the last horizontal period is sufficient. Can be spread.

(9) Ninth Invention A video signal converter according to a ninth invention is a video signal converter for converting an input video signal into a video signal suitable for a display device, and the operation of the video signal converter is as follows. Decoding means for decoding the control signal for setting, reset means for detecting the timing at which the vertical frequency conversion is switched from the off state to the on state from the decoding result of the decoding means, and a reset pulse that is output from the reset means A first counter that generates a horizontal synchronization signal after vertical frequency conversion that is reset by a reset pulse and a second counter that generates a vertical synchronization signal after vertical frequency conversion that is reset by a reset pulse output from the reset means. And a counter.

  In the video signal converter according to the ninth aspect of the invention, the control signal for setting the operation of the video signal converter is decoded, and the reset pulse is output at the timing when the vertical frequency conversion is turned from the OFF state to the ON state from the decoded result. Then, the horizontal synchronizing signal and the vertical synchronizing signal after the vertical frequency conversion are reset by the reset pulse. Therefore, when a video signal conversion device is created by an integrated circuit and vertical frequency conversion is performed by using a plurality of integrated circuits, the plurality of integrated circuits can be accurately set without passing a synchronization signal between the plurality of integrated circuits. Can operate in synchronization.

  According to the present invention, the connection order of the vertical frequency conversion means, interlace / progressive conversion means, horizontal pixel conversion means, and vertical pixel number conversion means is adaptively switched, and the storage capacity of the storage means according to the conversion content of the video signal Since each means can be arranged so that the most effective use can be made, the storage capacity of the storage means can be minimized without degrading the image quality.

  According to the present invention, in the case where the scanning line conversion means is arranged after the vertical frequency conversion means, the first horizontal synchronizing signal generation means and the output side of the vertical frequency conversion means A horizontal synchronizing signal serving as a reference on the input side of the scanning line converting means is generated, and a second horizontal synchronizing signal generating means different from the first horizontal synchronizing signal generating means serves as a reference on the output side of the scanning line converting means. Since the horizontal synchronizing signal is generated and the first and second horizontal synchronizing signal generating means are reset by the vertical synchronizing signal after the output side of the vertical frequency converting means, regardless of the enlargement / reduction by the scanning line conversion, The synchronization signal on the output side can be kept almost constant.

  Further, according to the present invention, when the vertical frequency conversion means is arranged after the scanning line conversion means, the first horizontal synchronizing signal generating means responds to the conversion rate of the scanning line conversion regardless of the presence or absence of the vertical frequency conversion. A horizontal synchronizing signal serving as a reference on the output side of the scanning line converting means and the input side of the vertical frequency converting means is generated at the selected frequency, and the second horizontal synchronizing signal generating means uses the reference pulse generated from the pulse generating means. A horizontal synchronizing signal serving as a reference on the output side of the vertical frequency converting means is generated, the first horizontal synchronizing signal generating means is reset by the vertical synchronizing signal of the video signal input to the scanning line converting means, and is output from the selecting means. Since the pulse generation means is reset by the vertical synchronization signal, vertical frequency conversion can be performed after scanning line conversion, and enlargement / reduction by scanning line conversion can be performed. Warazu, it is possible to keep the output side of the synchronizing signal of the device substantially constant.

  Further, according to the present invention, the horizontal synchronization signal reset by the vertical synchronization signal is generated, and the last pulse immediately before the horizontal synchronization signal is reset by the vertical synchronization signal is extracted from the horizontal synchronization signal. The width of the last horizontal period can be sufficiently widened, and the vertical synchronization signal can be generated at an accurate timing to always operate stably.

  Further, according to the present invention, the control signal for setting the operation of the video signal converter is decoded, and the reset pulse is output at the timing when the vertical frequency conversion is turned on from the off state by the decoded control signal, Since the horizontal sync signal and vertical sync signal after vertical frequency conversion are reset by the reset pulse, a video signal conversion device is created by an integrated circuit, and when performing vertical frequency conversion using multiple integrated circuits, multiple integrated A plurality of integrated circuits can be operated in synchronization with each other without passing a synchronization signal between the circuits.

The block diagram which shows the structure of the video signal converter by the 1st Embodiment of this invention The block diagram which shows the 1st example of the connection order of each block when performing IP conversion which does not require a field memory, or when not performing IP conversion The block diagram which shows the 2nd example of the connection order of each block when performing IP conversion which does not require a field memory, or when not performing IP conversion The block diagram which shows the 3rd example of the connection order of each block when IP conversion which does not require a field memory is performed, or when IP conversion is not performed The block diagram which shows the 4th example of the connection order of each block when performing IP conversion which does not require a field memory, or when not performing IP conversion The block diagram which shows the 1st example of the connection order of each block in the case of performing IP conversion which requires a field memory The block diagram which shows the 2nd example of the connection order of each block in the case of performing IP conversion which requires a field memory The block diagram which shows the structure of the video signal converter by the 2nd Embodiment of this invention Timing chart of each horizontal synchronizing signal at the time of enlargement processing by the scanning line conversion processing unit shown in FIG. Schematic diagram showing a display image for explaining the enlargement process by the scanning line conversion processing unit shown in FIG. Timing chart of each horizontal synchronization signal at the time of reduction processing by the scanning line conversion processing unit shown in FIG. FIG. 8 is a schematic diagram showing a display image for explaining reduction processing by the scanning line conversion processing unit shown in FIG. The block diagram which shows the structure of the video signal converter by the 3rd Embodiment of this invention The block diagram which shows the structure of the video signal converter by the 4th Embodiment of this invention FIG. 14 is a block diagram showing a configuration of an example of a counter with an extraction function used as the H counter with an extraction function and the division ratio counter with an extraction function shown in FIG. 14. FIG. 15 is a timing chart for explaining the operation of the counter with a sampling function shown in FIG. The block diagram which shows the structure of the synchronizing signal generation circuit used for the video signal converter by the 5th Embodiment of this invention Block diagram showing the configuration of a conventional video signal conversion apparatus that performs scanning line conversion without performing vertical frequency conversion The block diagram which shows the structure of the conventional video signal converter which performs a scanning line conversion while performing vertical frequency conversion FIG. 19 is a block diagram showing a configuration of a conventional video signal conversion apparatus in which a video signal conversion apparatus as shown in FIG. 19 is created by LSI, and the created two LSIs are operated in synchronization to perform vertical frequency conversion and scanning line conversion.

  Embodiments of the video signal conversion apparatus according to the present invention will be described below. The video signal converter according to the present invention outputs a video signal that is preferably used for a display device that performs dot matrix display such as a plasma display panel (PDP), a liquid crystal panel, and the like. , CRT (cathode ray tube) and the like.

(First embodiment)
First, the video signal converter according to the first embodiment of the present invention will be described. FIG. 1 is a block diagram showing a configuration of a video signal conversion apparatus according to the first embodiment of the present invention.

  1 includes a field memory 1, a memory control processing unit 2, an IP (interlace / progressive) conversion processing unit 3, a scanning line conversion processing unit 4, a horizontal pixel conversion processing unit 5, a selector control unit 6, and Selectors S1 to S4 are provided.

  The selection operation of the selector S1 is controlled by the selector control unit 6, and the video signal DV digitized by an AD (analog / digital) converter (not shown) outside the apparatus, the output of the scanning line conversion processing unit 4, and the horizontal The output of the pixel conversion processing unit 5 is received, and one of these three inputs is output to the memory control processing unit 2.

  The memory control processing unit 2 receives the output of the selector S1, generates control signals such as write and read addresses, and outputs them to the field memory 1, and writes the output of the selector S1 into the field memory 1 or writes into the field memory 1. The read data is read out, a video signal is transferred to and from the field memory 1, and vertical frequency conversion is performed as necessary.

  The selector S2 is controlled in its selection operation by the selector control unit 6, receives the video signal DV, the output of the memory control processing unit 2 and the output of the horizontal pixel conversion processing unit 5, and receives one of these three inputs. The data is output to the IP conversion processing unit 3.

  The IP conversion processing unit 3 receives the output of the selector S2, converts it to a progressive signal when the input video signal is an interlaced signal, and conversely passes it through in the case of the progressive signal, and scan line conversion processing unit 4 Output to.

  The scanning line conversion processing unit 4 performs vertical enlargement processing and reduction processing by increasing or decreasing the number of scanning lines of the video signal output from the IP conversion processing unit 3.

  The selector S3 is controlled in its selection operation by the selector control unit 6, receives the video signal DV, the output of the scanning line conversion processing unit 4, and the output of the horizontal pixel conversion processing unit 5, and receives one of these three inputs. Is output to the horizontal pixel conversion processing unit 5.

  The horizontal pixel conversion processing unit 5 receives the output of the selector S3, and performs horizontal enlargement processing and reduction processing by increasing or decreasing the number of horizontal pixels of the input video signal.

  The selector S4 has its selection operation controlled by the selector control unit 6, receives the output of the scanning line conversion processing unit 4, the output of the horizontal pixel conversion processing unit 5, and the output of the memory control processing unit 2, and receives these three inputs. One of them is output as a converted video signal TV to a display device (not shown).

  The selector control unit 6 receives the scanning line conversion coefficient signal K1, the horizontal pixel conversion coefficient signal K2, and the IP conversion mode signal K3, and changes each according to the scanning line conversion ratio, the horizontal pixel number conversion ratio, and the IP conversion mode. The selection operation of the selectors S1 to S4 is controlled so that the blocks are connected in the order described later.

  Although not shown, the video signal conversion apparatus shown in FIG. 1 further includes a synchronization processing unit, which receives a synchronization signal input from the outside, and based on this synchronization signal, a memory In order to properly control the operations of the control processing unit 2, the IP conversion processing unit 3, the scanning line conversion processing unit 4 and the horizontal pixel conversion processing unit 5, a predetermined clock, horizontal synchronizing signal and vertical synchronizing signal are given to each block. Yes.

  In the present embodiment, the field memory 1 corresponds to a storage unit, the memory control processing unit 2 corresponds to a vertical frequency conversion unit, the IP conversion processing unit 3 corresponds to an interlace / progressive conversion unit, and a scanning line conversion processing unit 4 corresponds to the scanning line conversion means, the horizontal pixel conversion processing section 5 corresponds to the horizontal pixel conversion means, and the selector control section 6 and the selectors S1 to S4 correspond to the connection switching means.

  Next, the scanning line conversion coefficient signal K1, the horizontal pixel conversion coefficient signal K2, and the IP conversion mode signal K3 will be described.

  In the scanning line conversion and horizontal pixel conversion, if the number of pixels in the vertical direction or the horizontal direction before conversion is k and the number of pixels in the vertical direction or the horizontal direction after conversion is 1, and k is larger than 1, the reduction process is performed. , K is smaller than 1, enlargement processing is performed. For example, when the scanning line conversion coefficient signal K1 is larger than 1, the selector control unit 6 is notified that the reduction processing is performed as scanning line conversion. When the scanning line conversion coefficient signal K1 is smaller than 1, the scanning line conversion coefficient signal K1 is expanded as scanning line conversion. The selector control unit 6 is notified that the process is to be performed.

  Similarly, when the horizontal pixel conversion coefficient signal K2 is larger than 1, the selector control unit 6 is notified that the reduction process is performed as horizontal pixel conversion. When the horizontal pixel conversion coefficient signal K2 is smaller than 1, horizontal pixel conversion is performed. The selector control unit 6 is notified that the enlargement process is performed.

  The IP conversion method includes, for example, a motion adaptive type in which motion is detected between frames, and line interpolation is performed by changing the synthesis ratio of the information of the own field and the information of the previous field according to the degree of the motion. There are IP conversion and intra-field interpolation in which interpolation is performed using only the information of the own field. Since the former requires information on the previous field and previous frame, a field memory is required before IP conversion, and cannot be compatible with vertical frequency conversion. On the other hand, since the latter does not require a field memory, it can be compatible with vertical frequency conversion. When performing IP conversion, scanning line conversion must be performed after IP conversion.

  As described above, the IP conversion mode includes a mode that does not perform IP conversion, an IP conversion mode that does not require a field memory, and an IP conversion mode that requires a field memory. Therefore, the IP conversion mode signal K3 notifies the selector control unit 6 of one of the above three modes.

  Next, the order in which the blocks are connected according to the above three criteria will be described.

  2 to 5 show respective blocks when an input video signal does not require IP conversion including processing in the time axis direction, that is, when IP conversion that does not require a field memory is performed or when IP conversion is not performed. It is a block diagram which shows the 1st thru | or 4th example of a connection order.

  First, when the number of horizontal pixels of the video signal is larger than the number of horizontal pixels of the display panel and the number of vertical pixels of the video signal is larger than the number of vertical pixels of the display panel, both horizontal pixel conversion and scanning line conversion are reduced processing. . In this case, in order to minimize the storage capacity of the field memory 1, the horizontal pixel conversion processing unit 5 and the scanning line conversion processing unit 4 need to be arranged before the memory control processing unit 2.

  Therefore, the scanning line conversion coefficient signal K1 notifies that the reduction process is performed as the scanning line conversion, the horizontal pixel conversion coefficient signal K2 notifies that the reduction process is performed as the horizontal pixel conversion, and the IP conversion mode signal K3 When notified of a mode in which IP conversion is not performed or an IP conversion mode that does not require a field memory, the selector control unit 6 selects (SEL1, SEL2, SEL3, SEL4) as selection signals SEL1-SEL4 of the selectors S1-S4. ) = (1, 2, 0, 2) is output. As a result, as shown in FIG. 2, the blocks are connected in the order of the horizontal pixel conversion processing unit 5, the IP conversion processing unit 3, the scanning line conversion processing unit 4, and the memory control processing unit 2.

  For example, when 1: 3 reduction processing is performed as horizontal pixel conversion and 1: 2 reduction processing is performed as scanning line conversion, the total amount of information is reduced by performing horizontal pixel conversion before scanning line conversion. , Can improve the operation speed. As described above, when both are reduction processing, it is preferable to perform conversion with a large reduction ratio first, and processing for performing processing with a large reduction ratio among the horizontal pixel conversion processing unit 5 and the scanning line conversion processing unit 4. It is preferable that the parts are connected so as to be arranged first.

  Next, when the number of horizontal pixels of the video signal is smaller than the number of horizontal pixels of the display panel and the number of vertical pixels of the video signal is larger than the number of vertical pixels of the display panel, the horizontal pixel conversion is an enlargement process, and the scanning line conversion is performed. Reduction processing is performed. In this case, in order to minimize the storage capacity of the field memory 1, the scanning line conversion processing unit 4 is arranged before the memory control processing unit 2, and the horizontal pixel conversion processing unit 5 is arranged after the memory control processing unit 2. Need to be placed.

  Therefore, the scanning line conversion coefficient signal K1 notifies that the reduction process is performed as the scanning line conversion, the horizontal pixel conversion coefficient signal K2 notifies that the expansion process is performed as the horizontal pixel conversion, and the IP conversion mode signal K3 When notified of a mode in which IP conversion is not performed or an IP conversion mode that does not require a field memory, the selector control unit 6 selects (SEL1, SEL2, SEL3, SEL4) as selection signals SEL1-SEL4 of the selectors S1-S4. ) = (1, 0, 2, 1) is output. As a result, as shown in FIG. 3, the blocks are connected in the order of the IP conversion processing unit 3, the scanning line conversion processing unit 4, the memory control processing unit 2, and the horizontal pixel conversion processing unit 5.

  Next, when the number of horizontal pixels of the video signal is larger than the number of horizontal pixels of the display panel and the number of vertical pixels of the video signal is smaller than the number of vertical pixels of the display panel, the horizontal pixel conversion is a reduction process, and the scanning line conversion is performed. Enlargement processing. In this case, in order to minimize the storage capacity of the field memory 1, the horizontal pixel conversion processing unit 5 is arranged before the memory control processing unit 2 and the scanning line conversion processing unit 4 is arranged after the memory control processing unit 2. Need to be placed.

  Therefore, the scanning line conversion coefficient signal K1 notifies that the enlargement process is performed as the scanning line conversion, the horizontal pixel conversion coefficient signal K2 notifies that the reduction process is performed as the horizontal pixel conversion, and the IP conversion mode signal K3 When notified of a mode in which IP conversion is not performed or an IP conversion mode that does not require a field memory, the selector control unit 6 selects (SEL1, SEL2, SEL3, SEL4) as selection signals SEL1-SEL4 of the selectors S1-S4. ) = (2, 1, 0, 0) is output. As a result, as shown in FIG. 4, the blocks are connected in the order of the horizontal pixel conversion processing unit 5, the IP conversion processing unit 3, the scanning line conversion processing unit 4, and the memory control processing unit 2.

  Next, when the number of horizontal pixels of the video signal is smaller than the number of horizontal pixels of the display panel and the number of vertical pixels of the video signal is smaller than the number of vertical pixels of the display panel, both horizontal pixel conversion and scanning line conversion are Become. In this case, it is necessary to arrange the scanning line conversion processing unit 4 and the horizontal pixel conversion processing unit 5 in the subsequent stage of the memory control processing unit 2 in order to minimize the storage capacity of the field memory 1.

  Further, when the scanning line conversion processing unit 4 is arranged at the subsequent stage of the memory control processing unit 2, the frequency of the horizontal synchronization signal on the output side of the scanning line conversion processing unit 4 is always kept constant, and the scanning line conversion processing unit 4 If the enlargement processing is performed by the horizontal pixel conversion processing unit 5 arranged in the preceding stage, the information amount of the processed video signal is increased by the enlargement processing, and the storage capacity of the line memory of the scanning line conversion processing unit 4 is increased. Or the operating frequency of the line memory must be increased. For this reason, it is necessary to arrange the horizontal pixel conversion processing unit 5 in the subsequent stage of the scanning line conversion processing unit 4.

  Therefore, the scanning line conversion coefficient signal K1 notifies that the enlargement process is performed as the scanning line conversion, the horizontal pixel conversion coefficient signal K2 notifies that the enlargement process is performed as the horizontal pixel conversion, and the IP conversion mode signal K3 When notified of a mode in which IP conversion is not performed or an IP conversion mode that does not require a field memory, the selector control unit 6 selects (SEL1, SEL2, SEL3, SEL4) as selection signals SEL1-SEL4 of the selectors S1-S4. ) = (0, 1, 1, 1) is output. As a result, as shown in FIG. 5, the blocks are connected in the order of the memory control processing unit 2, the IP conversion processing unit 3, the scanning line conversion processing unit 4, and the horizontal pixel conversion processing unit 5.

  6 and 7 show the connection order of each block when the input video signal requires interlace / progressive conversion including processing in the time axis direction, that is, when IP conversion that requires field memory is performed. It is a block diagram which shows the 1st and 2nd example. In this case, since the IP conversion processing unit 3 must be disposed at the subsequent stage of the memory control processing unit 2 and the scanning line conversion processing unit 4 must be disposed at the subsequent stage of the IP conversion processing unit 3, the horizontal pixel conversion processing unit 5 is stored in the memory. Which side of the control processing unit 2 is to be arranged is selected.

  First, when the number of horizontal pixels of the video signal is larger than the number of horizontal pixels of the display panel, the horizontal pixel conversion is a reduction process. In this case, in order to minimize the storage capacity of the field memory 1, it is necessary to arrange the horizontal pixel conversion processing unit 5 before the memory control processing unit 2.

  Therefore, when the horizontal pixel conversion coefficient signal K2 notifies that the reduction process is performed as the horizontal pixel conversion, and the IP conversion mode signal K3 notifies the IP conversion mode that requires the field memory, the selector control unit 6 As the selection signals SEL1 to SEL4 of the selectors S1 to S4, signals that are (SEL1, SEL2, SEL3, SEL4) = (2, 1, 0, 0) are output. As a result, as shown in FIG. 6, the blocks are connected in the order of the horizontal pixel conversion processing unit 5, the memory control processing unit 2, the IP conversion processing unit 3, and the scanning line conversion processing unit 4.

  Next, when the number of horizontal pixels of the video signal is smaller than the number of horizontal pixels of the display panel, the horizontal pixel conversion is an enlargement process. In this case, in order to minimize the storage capacity of the field memory 1, it is necessary to arrange the horizontal pixel conversion processing unit 5 after the memory control processing unit 2.

  Accordingly, when the horizontal pixel conversion coefficient signal K2 notifies that the enlargement process is performed as the horizontal pixel conversion, and the IP conversion mode signal K3 notifies the IP conversion mode that requires the field memory, the selector control unit 6 As the selection signals SEL1 to SEL4 of the selectors S1 to S4, signals that are (SEL1, SEL2, SEL3, SEL4) = (0, 1, 1, 1) are output. As a result, as shown in FIG. 7, the blocks are connected in the order of the memory control processing unit 2, the IP conversion processing unit 3, the scanning line conversion processing unit 4, and the horizontal pixel conversion processing unit 5.

  As described above, in this embodiment, the connection order of the memory control processing unit 2, the IP conversion processing unit 3, the scanning line conversion processing unit 4, and the horizontal pixel conversion processing unit 5 can be switched adaptively, so that the video Each block can be arranged so as to make the most effective use of the storage capacity of the field memory 1 in accordance with the signal conversion contents. Accordingly, the storage capacity of the field memory 1 can be suppressed to the necessary minimum without degrading the image quality, and the operation speed of the apparatus can be improved. Can be increased. Further, when performing the same processing as in the prior art, the operation clock can be set low, so that power consumption can also be reduced.

  When the enlargement process and the reduction process are not performed, the blocks may be connected in any order, and the blocks may be connected according to the specifications of the entire display system including the video signal converter.

(Second Embodiment)
Next, a video signal conversion apparatus according to the second embodiment of the present invention will be described. FIG. 8 is a block diagram showing a configuration of a video signal conversion apparatus according to the second embodiment of the present invention.

  The video signal conversion apparatus shown in FIG. 8 includes a field memory 1, a memory control processing unit 2, a scanning line conversion processing unit 4, and a synchronization processing unit 7. The synchronization processing unit 7 includes PLL circuits 71 and 72, frequency division ratio counters 73 and 74, a crystal oscillator 75, H counters 76 and 77, a V counter 78, and a selector 79.

  The memory control processing unit 2 receives a video signal DV digitized by an AD converter (not shown) outside the apparatus, generates control signals such as write and read addresses, and outputs the control signals to the field memory 1 for input. The video signal is written to the field memory 1 and the data written to the field memory 1 is read to exchange the video signal with the field memory 1 and perform vertical frequency conversion as necessary. In addition, the memory control processing unit 2 inputs a vertical synchronization signal VS of the digital video signal DV from the outside as a vertical synchronization signal V1 that becomes a reference pulse on the input side of the memory control processing unit 2 (reference pulse on the input side of the entire apparatus). Is done.

  The scanning line conversion processing unit 4 receives the output of the memory control processing unit 2, performs an enlargement process and a reduction process in the vertical direction by increasing or decreasing the number of scanning lines of the input video signal, and outputs the converted video signal LV To do.

  The PLL circuit 71 receives a horizontal synchronization signal HS of the digital video signal DV from the outside and generates a first clock CK1. The frequency division ratio counter 73 determines the frequency division ratio of the PLL circuit 71, that is, divides the first clock CK1, generates a feedback pulse to the PLL circuit 71, and inputs the pulse to the memory control processing unit 2 Is output to the memory control processing unit 2 as a horizontal synchronization signal H1 serving as a reference pulse on the side (a reference pulse on the input side of the entire apparatus).

  The crystal oscillator 75 generates the second clock CK2. The H counter 76 divides the second clock CK2, and the horizontal synchronization signal H2 that becomes the reference pulse before the scanning line conversion, that is, the output side reference pulse of the memory control processing unit 2 and the input side reference pulse of the scanning line conversion processing unit 4 is used. Is output to the memory control processing unit 2 and the scanning line conversion processing unit 4. The V counter 78 divides the horizontal synchronizing signal H2 output from the H counter 76 and outputs a vertical synchronizing signal V2 'to the selector 79.

  The selector 79 is a vertical synchronization signal VS and a V counter 78 of the digital video signal DV inputted from the outside as a vertical synchronization signal V1 which becomes a reference pulse on the input side of the memory control processing unit 2 (reference pulse on the input side of the entire apparatus). When the vertical frequency conversion is performed by the memory control processing unit 2, the vertical synchronization signal V2 ′ is selected. When the vertical frequency conversion is not performed, the vertical synchronization signal V1 is selected. Before the scanning line conversion, that is, the reference pulse on the output side of the memory control processing unit 2 and the vertical synchronization signal V2 that becomes the reference pulse on the input side of the scanning line conversion processing unit 4 and after the scanning line conversion, that is, on the output side of the scanning line conversion processing unit 4 Is output to the memory control processing unit 2 and the scanning line conversion processing unit 4 as a vertical synchronization signal V3 serving as a reference pulse.

  The H counter 77 divides the second clock CK2 and outputs a reference pulse. The PLL circuit 72 receives the reference pulse output from the H counter 77 and generates a third clock CK3. The division ratio counter 74 determines the division ratio of the PLL circuit 72, that is, divides the third clock CK3, generates a feedback pulse to the PLL circuit 72, and outputs the pulse to the scanning line conversion processing unit 4 The signal is output to the scanning line conversion processing unit 4 as a horizontal synchronizing signal H3 that becomes an output side reference pulse (an output side reference pulse of the entire apparatus).

  Further, both the H counters 76 and 77 and the frequency division ratio counter 74 are reset by the vertical synchronization signal V2 (reset pulse RST) selected by the selector 79. Here, since the selector 79 selects the output V2 ′ of the V counter 78 during the vertical frequency conversion, the H counter 76 is reset by the vertical synchronization signal V2 created based on the horizontal synchronization signal H2 created by itself, At first glance it seems meaningless.

  However, for example, when the video signal conversion apparatus shown in FIG. 8 is created by LSI and a plurality of LSIs are operated synchronously, a case where a vertical synchronization signal after vertical frequency conversion is input from another LSI is considered as H. The reset function of the counter 76 is important. In this case, it goes without saying that the V counter 78 also needs a reset function. When the video signal conversion apparatus shown in FIG. 8 is produced by LSI, the PLL circuits 71 and 72 and the crystal oscillator 75 are not integrated due to restrictions due to the manufacturing process. . The other embodiments are the same in this respect.

  In the present embodiment, the field memory 1 corresponds to a storage unit, the memory control processing unit 2 corresponds to a vertical frequency conversion unit, the scanning line conversion processing unit 4 corresponds to a scanning line conversion unit, and the synchronization processing unit 7 The H counter 76 corresponds to the first horizontal synchronizing signal generating means, the V counter 78 corresponds to the vertical synchronizing signal generating means, and the H counter 77 and the frequency division ratio counter 74 correspond to the second horizontal synchronizing signal generating means. The selector 79 corresponds to the synchronizing signal generating means, and the selector 79 corresponds to the selecting means. The H counter 76 corresponds to the first counter, the V counter 78 corresponds to the second counter, the H counter 77 corresponds to the third counter, and the frequency division ratio counter 74 corresponds to the fourth counter. To do.

  Next, the operation of the video signal converter configured as described above will be described. FIG. 9 is a timing chart of each horizontal synchronization signal at the time of enlargement processing by the scanning line conversion processing unit 4 shown in FIG. 8, and FIG. 10 is for explaining the enlargement processing by the scanning line conversion processing unit 4 shown in FIG. It is a schematic diagram which shows a display image.

  In the case of enlargement processing by 2 → 3 conversion (1.5 times) shown in FIG. 9, as shown in FIG. 10, at the output time of the memory control processing unit 2, the center in which the upper and lower portions that are unnecessary by the enlargement processing are cut off Only the portion is cut out, and only the central portion is enlarged by the scanning line conversion processing unit 4 and converted into the number of lines required by the display panel. At this time, as shown in FIG. 9, the frequency of the horizontal synchronizing signal H2 before the scanning line conversion is lowered so that the frequency of the horizontal synchronizing signal H3 after the scanning line conversion becomes equal to the frequency of the horizontal synchronizing signal H1 at the time of input. To operate.

  In order to perform the above conversion processing, another horizontal synchronization signal having a cycle independent of the input horizontal synchronization signal H1 is required, and the horizontal synchronization signal H2 is generated by the H counter 76 independently of the horizontal synchronization signal H1. ing.

  Further, the set value of the H counter 77 after the scanning line conversion is closely related to the set value of the H counter 76. For example, as shown in FIG. 9, when 1.5 times enlargement processing is performed, two cycles of the horizontal synchronizing signal H2 before the scanning line conversion must be three cycles of the horizontal synchronizing signal H3 after the scanning line conversion. That is, the set value of the H counters 76 and 77 must be set to 3: 2, which is the reciprocal ratio of the number of lines included within a certain period. Therefore, when the scanning line conversion processing unit 4 performs m: n enlargement processing, the ratio between the setting value of the H counter 76 and the setting value of the H counter 77 needs to be the ratio of n: m.

  In this way, the reading speed of the video data from the field memory 1 can be slowed and unnecessary portions of the video data are not stored, so that the storage capacity of the field memory 1 can be reduced.

  FIG. 11 is a timing chart of each horizontal synchronizing signal at the time of reduction processing by the scanning line conversion processing unit 4 shown in FIG. 8, and FIG. 12 is for explaining the reduction processing by the scanning line conversion processing unit 4 shown in FIG. It is a schematic diagram which shows a display image.

  In the case of reduction processing by 4 → 3 conversion (0.75 times) shown in FIG. 11, dummy black data is inserted vertically at the output time of the memory control processing unit 2 as shown in FIG. After increasing the number, the scanning line conversion processing unit 4 performs a reduction process. At this time, as shown in FIG. 12, the period of the horizontal synchronizing signal H2 before the scanning line conversion is multiplied by 0.75 in advance, and the frequency of the horizontal synchronizing signal H3 after the scanning line conversion is the horizontal synchronizing signal H1 at the time of input. Operate so that it is equal to the frequency of.

  In general, the first clock CK1 output from the PLL circuit 71 is used as a sampling clock in the AD converter circuit, and the frequency division ratio counter 73 is basically a dot of the input video signal. The clock and the first clock CK1 are set to have the same oscillation frequency. The frequency division ratio counter 74 is set so that all the horizontal pixels of the output video signal sufficiently enter within one horizontal period and the number of clocks within one horizontal period required by the subsequent circuit. . The V counter 78 is set so that the frequency of the vertical synchronizing signal V2 'becomes the vertical frequency required by the subsequent circuit or the like.

  As described above, the frequency of each synchronization signal after the output side of the memory control processing unit 2 is determined by calculating backward from the number of lines, the number of clocks, and the conversion ratio of the scanning line conversion required by the circuit in the subsequent stage. It is possible to keep the frequency of the horizontal sync signal and clock on the output side constant. This is always determined only by the conversion ratio in scanning line conversion, regardless of the frequency of the input video signal and the number of pixels. It becomes easy to set.

  As described above, in the present embodiment, when the scanning line conversion processing unit 4 is arranged after the memory control processing unit 2, the reference pulse on the output side of the memory control processing unit 2 regardless of the presence or absence of vertical frequency conversion. The horizontal synchronizing signal H2 is regenerated by the H counter 76, and a reference pulse of the PLL circuit 72 for generating the third clock CK3 is generated by the H counter 77 different from the H counter 76, and the H counters 76 and 77 and the PLL circuit are generated. The frequency division ratio counter 74 that determines the frequency division ratio of 72 is reset by a vertical synchronization signal V2 serving as a reference pulse after the output side of the memory control processing unit 2. Therefore, the horizontal synchronizing signal and the clock on the output side of the apparatus can be kept constant regardless of the enlargement and reduction processing by the scanning line conversion processing unit 4.

  Even if the frequency division ratio counter 74 does not have a reset function, a clock is generated within the tracking range of the PLL circuit 72. However, if the phase relationship between the reference pulse and the feedback pulse of the PLL circuit 72 is greatly deviated, the video is disturbed or top curl occurs until the PLL circuit 72 is locked. Therefore, a reset function is also provided in the frequency division ratio counter 74, and the oscillation operation of the PLL circuit 72 is stabilized by simultaneously resetting the reference pulse and the feedback pulse.

  In the example shown in FIG. 8, the crystal oscillator 75 is used to generate the second clock CK2, but this is fast as the internal operation of the apparatus, for example, by the interface of the field memory 1 or IP conversion. When a clock is required, the second clock CK2 inside the device is used which is faster than the first clock CK1 on the input side of the device and the third clock CK3 on the output side of the device. Therefore, if there is no problem in terms of the operation speed of the device, the first clock CK1 on the input side may be used instead of the second clock CK2 without using a crystal oscillator.

  On the other hand, the advantage of using the crystal oscillator 75 is not only advantageous when a fast operation is required as described above, but also an asynchronous clock, which causes a clock disturbance output on the display panel. For example, the output side can guarantee stable synchronization and clock even if the input side synchronization and clock are disturbed.

(Third embodiment)
Next, a video signal conversion apparatus according to a third embodiment of the present invention will be described. FIG. 13 is a block diagram showing a configuration of a video signal conversion apparatus according to the third embodiment of the present invention.

  The video signal conversion apparatus shown in FIG. 13 includes a field memory 1, a memory control processing unit 2, a scanning line conversion processing unit 4, and a synchronization processing unit 7a. The synchronization processing unit 7 a includes PLL circuits 71 and 72, frequency division ratio counters 73 and 74, a crystal oscillator 75, H counters 76 and 80, a V counter 78, and a selector 79.

  The scanning line conversion processing unit 4 receives the video signal DV digitized by an AD converter (not shown) outside the apparatus, and increases or decreases the number of scanning lines of the input video signal to increase or decrease the vertical direction. I do. The scanning line conversion processing unit 4 also includes a vertical synchronization signal V1 that serves as a reference pulse on the input side of the scanning line conversion processing unit 4 (a reference pulse on the input side of the entire apparatus) and after scanning line conversion, that is, the scanning line conversion processing unit 4. The vertical synchronizing signal VS of the digital video signal DV is input from the outside as the vertical synchronizing signal V2 serving as a reference pulse on the output side.

  The memory control processing unit 2 receives the output of the scanning line conversion processing unit 4, generates control signals such as writing and reading addresses, and outputs them to the field memory 1, and outputs the scanning line conversion processing unit 4 to the field memory 1. Write or read data written to the field memory 1 to transfer video signals to and from the field memory 1 and perform vertical frequency conversion as necessary to output the converted video signal LV To do. The memory control processing unit 2 receives the vertical synchronization signal VS of the digital video signal DV from the outside as the vertical synchronization signal V2 that becomes the reference pulse on the input side of the memory control processing unit 2 after scanning line conversion.

  The PLL circuit 71 receives a horizontal synchronization signal HS of the digital video signal DV from the outside and generates a first clock CK1. The frequency division ratio counter 73 determines the frequency division ratio of the PLL circuit 71, that is, divides the first clock CK 1, generates a feedback pulse to the PLL circuit 71, and outputs the pulse to the scanning line conversion processing unit 4. The signal is output to the scanning line conversion processing unit 4 as a horizontal synchronization signal H1 that becomes a reference pulse on the input side (reference pulse on the input side of the entire apparatus).

  The H counter 80 divides the first clock CK1, and after the scanning line conversion, that is, the horizontal synchronization signal H2 that becomes the reference pulse on the output side of the scanning line conversion processing unit 4 and the reference pulse on the input side of the memory control processing unit 2 Is output. The crystal oscillator 75 generates the second clock CK2. The H counter 76 divides the second clock CK2, generates a reference pulse of the PLL circuit 72 having the same frequency as the horizontal synchronization signal H2, and outputs the pulse to the V counter 78. The V counter 78 divides the reference pulse output from the H counter 76 and outputs a vertical synchronization signal V3 '.

  The selector 79 is a vertical synchronizing signal VS and a V counter of the digital video signal DV inputted from the outside as a vertical synchronizing signal V1 which becomes a reference pulse on the input side of the scanning line conversion processing unit 4 (reference pulse on the input side of the entire apparatus). In response to the vertical synchronization signal V3 ′ output from 78, the vertical synchronization signal V3 ′ is selected when vertical frequency conversion is performed by the memory control processing unit 2, and the vertical synchronization signal V1 is selected when vertical frequency conversion is not performed. Then, it outputs to the memory control processing unit 2 as a vertical synchronization signal V that becomes a reference pulse on the output side of the memory control processing unit 2 (reference pulse on the output side of the entire apparatus).

  The PLL circuit 72 receives the reference pulse output from the H counter 76 and generates a third clock CK3. The division ratio counter 74 determines the division ratio of the PLL circuit 72, that is, divides the third clock CK3, generates a feedback pulse to the PLL circuit 72, and outputs the pulse to the output of the memory control processing unit 2. Is output to the memory control processing unit 2 as a horizontal synchronization signal H3 that becomes a reference pulse on the side (a reference pulse on the output side of the entire apparatus).

  The H counter 80 is reset by a vertical synchronization signal VS (reset pulse RST) input from the outside, and the H counter 76 and the division ratio counter 74 are reset by a vertical synchronization signal V3 (reset pulse RST) selected by the selector 79. Reset. Here, since the selector 79 selects the output V3 ′ of the V counter 78 during the vertical frequency conversion, the H counter 76 generates the vertical synchronization signal V3 ′ created based on the horizontal synchronization signal generated by itself during the vertical frequency conversion. Seems to be meaningless at first glance.

  However, for example, when the video signal conversion apparatus shown in FIG. 13 is created by LSI and a plurality of LSIs are operated synchronously, a case where a vertical synchronization signal after vertical frequency conversion is input from another LSI is considered as H. The reset function of the counter 76 is important. In this case, it goes without saying that the V counter 78 also needs a reset function.

  In the present embodiment, the field memory 1 corresponds to storage means, the memory control processing section 2 corresponds to vertical frequency conversion means, the scanning line conversion processing section 4 corresponds to scanning line conversion means, and the synchronization processing section 7a The H counter 80 corresponds to the first horizontal synchronization signal generation means, the H counter 76 corresponds to the pulse generation means, the V counter 78 corresponds to the vertical synchronization signal generation means, and the frequency dividing ratio corresponds to the synchronization control means. The counter 74 corresponds to second horizontal synchronization signal generation means, and the selector 79 corresponds to selection means. The H counter 80 corresponds to the first counter, the H counter 76 corresponds to the second counter, the V counter 78 corresponds to the third counter, and the frequency division ratio counter 74 corresponds to the fourth counter. To do.

  Next, the operation of the video signal converter configured as described above will be described. Between the frequency division ratio counter 73 that generates the horizontal synchronizing signal H1 before the scanning line conversion and the H counter 80 that generates the horizontal synchronizing signal H2 after the scanning line conversion, the H counters 76 and 77 of the second embodiment. The same relationship as In other words, when m: n conversion is performed in the scanning line conversion, the set values of the frequency division ratio counter 73 and the H counter 80 must be n: m. At this time, since the frequency of the horizontal synchronizing signal H1 before the scanning line conversion is determined by the input video signal, the frequency and the number of lines of the horizontal synchronizing signal H2 after the scanning line conversion vary greatly according to the conversion rate of the scanning line conversion. . Therefore, by changing the horizontal synchronization signal and the clock by the memory control processing unit 2, it is possible to keep the frequency of the horizontal synchronization signal and the clock on the output side of the apparatus constant.

  In general, the first clock CK1 output from the PLL circuit 71 is used as a sampling clock in the AD converter circuit, and the frequency division ratio counter 73 is basically a dot of the input video signal. The clock and the first clock CK1 are set to have the same oscillation frequency. The frequency division ratio counter 74 is set so that all the horizontal pixels of the output video signal sufficiently enter within one horizontal period and the number of clocks within one horizontal period required by the subsequent circuit. . The V counter 78 is set so that the frequency of the vertical synchronization signal V3 'becomes the vertical frequency required by the subsequent circuit or the like.

  As described above, in the present embodiment, when the memory control processing unit 2 is disposed after the scanning line conversion processing unit 4, the frequency according to the conversion rate of the scanning line conversion is used regardless of the presence or absence of vertical frequency conversion. An H counter 80 for generating a horizontal synchronization signal H2 and an H counter 76 for generating a reference pulse serving as a reference on the output side of the memory control processing unit 2 are provided, and an output of the H counter 76 is generated by a third clock CK3. As a reference pulse for the PLL circuit 72, the H counter 80 is reset by the vertical synchronizing signal VS of the input video signal DV, and a frequency dividing ratio counter 74 for determining a frequency dividing ratio between the H counter 76 and the PLL circuit 72 Is reset by the vertical synchronization signal V3 after the output of the memory control processing unit 2. Therefore, the vertical frequency conversion can be performed after the scanning line conversion, and the horizontal synchronization signal and the clock on the output side of the apparatus can be kept constant regardless of the enlargement and reduction processing by the scanning line conversion processing unit 4. .

  Even if the frequency division ratio counter 74 does not have a reset function, a clock is generated within the tracking range of the PLL circuit 72. However, if the phase relationship between the reference pulse and the feedback pulse of the PLL circuit 72 is greatly deviated, the video is disturbed or top curl occurs until the PLL circuit 72 is locked. Therefore, a reset function is also provided in the frequency division ratio counter 74, and the oscillation operation of the PLL circuit 72 is stabilized by simultaneously resetting the reference pulse and the feedback pulse.

  In the example shown in FIG. 13, the crystal oscillator 75 is used to generate the second clock CK2, but this is fast as the internal operation of the apparatus, for example, by the interface of the field memory 1 or IP conversion. When a clock is required, the second clock CK2 inside the device is used which is faster than the first clock CK1 on the input side of the device and the third clock CK3 on the output side of the device. For example, when the enlargement process is performed by the scanning line conversion processing unit 4, a synchronization signal faster than the input is required on the output side of the scanning line conversion processing unit 4. Therefore, the conversion process is performed on the first clock CK on the input side. Can no longer do. For this reason, the synchronization signal is once again beaten with the faster second clock CK2 and supplied to the scanning line conversion processing unit 4 and the memory control processing unit 2 to perform conversion processing. If there is no problem in the operation speed of the apparatus, the first clock CK1 on the input side may be used in place of the second clock CK2 without using a crystal oscillator.

  On the other hand, the advantage of using the crystal oscillator 75 is not only advantageous when a fast operation is required as described above, but also an asynchronous clock, which causes a clock disturbance output on the display panel. For example, the output side can guarantee stable synchronization and clock even if the input side synchronization and clock are disturbed.

(Fourth embodiment)
Next explained is a video signal converter according to the fourth embodiment of the invention.

  In the counter having a reset function such as the H counter 76 used in the second and third embodiments, the horizontal period immediately before the reset is performed is shorter than the normal horizontal period. Therefore, in each block to which a synchronization signal is supplied, when processing that cannot be completed unless a sufficient number of clocks are secured, for example, when writing to or reading from a line memory, the operation is not stable with the same synchronization signal, and the worst In this case, the normal video area is affected. In addition, when the last horizontal period becomes extremely short, the last horizontal sync signal and the first horizontal sync signal are connected, or the vertical sync signal is recreated from the horizontal sync signal. The operation cannot be guaranteed, for example, the vertical synchronization signal is generated with reference to the horizontal synchronization signal.

  The video signal conversion apparatus according to the fourth embodiment solves the above problems and improves the stability of circuit operation. FIG. 14 is a block diagram showing a configuration of a video signal conversion apparatus according to the fourth embodiment of the present invention.

  The difference between the video signal converter shown in FIG. 14 and the video signal converter shown in FIG. 8 is that the synchronization processing unit 7a is changed to the synchronization processing unit 7b, and the H counters 76 and 77 and the division ratio counter 74 are sampling functions. The H counters 81 and 82 and the division ratio counter 83 with a sampling function are respectively changed, and the other points are the same as those of the video signal converter shown in FIG. Detailed description will be omitted below.

  The H counters 81 and 82 with the extraction function and the frequency division ratio counter 83 with the extraction function shown in FIG. 14 are counters that have the function of extracting the last horizontal pulse in the vertical period as well as being reset.

  FIG. 15 is a block diagram showing a configuration of an example of a counter with an extraction function used as the H counters 81 and 82 with an extraction function and the frequency division ratio counter 83 with an extraction function shown in FIG.

  15 includes a pulse generation circuit 91, a delay circuit 92, an extraction circuit 93, and a maximum value detection circuit 94.

  The pulse generation circuit 91 receives the clock CLK, generates a pulse PG, and is reset by a reset signal RST, and corresponds to the H counter 76 shown in FIG. The delay circuit 92 delays the pulse PG output from the pulse generation circuit 91 in accordance with the delay of the maximum value pulse MS of the maximum value detection circuit 94 and outputs a delay pulse DS.

  The maximum value detection circuit 94 counts the pulse PG output from the pulse generation circuit 91, and is actually the last horizontal pulse of the delay pulse DS during the period from the last horizontal pulse where the count value is maximized to the reset. The maximum value pulse MS that is at a high level (ON state) is output only during the period from the rising edge to the rising edge of the first horizontal pulse, that is, the last horizontal period.

  The extraction circuit 93 extracts the delay pulse DS output from the delay circuit 93 during the period when the maximum value detection circuit 94 is on, that is, the period when the maximum value pulse MS is high level, and outputs it as the output pulse OS. The period in which the delay pulse DS is extracted is until immediately before the first horizontal synchronization signal in the vertical period is output, and the delay circuit 92 is adjusted so as to be at that timing.

  In the present embodiment, the field memory 1 corresponds to a storage unit, the memory control processing unit 2 corresponds to a vertical frequency conversion unit, the scanning line conversion processing unit 4 corresponds to a scanning line conversion unit, and the synchronization processing unit 7b The H counters 81 and 82 with extraction function and the frequency division ratio counter 83 with extraction function correspond to horizontal synchronization signal generation means, the pulse generation circuit 91 corresponds to pulse generation means, and the delay circuit 92 corresponds to synchronization control means. The extraction circuit 93 corresponds to the delay means, the extraction circuit 93 corresponds to the extraction means, and the maximum value detection circuit 94 corresponds to the maximum value detection means.

  FIG. 16 is a timing chart for explaining the operation of the counter with an extraction function shown in FIG.

  As shown in FIG. 16, the pulse PG generated from the pulse generation circuit 91 is delayed by the delay circuit 92, and the delay pulse DS is output from the delay circuit 92. At this time, if the maximum value pulse MS is output from the maximum value detection circuit 94, the delay pulse DS during the period when the maximum value pulse MS is at the high level is extracted by the extraction circuit 93. An output pulse OS from which the pulse has been extracted is output.

  With the above configuration, in the present embodiment, the pulse of the last horizontal synchronization signal immediately before resetting is extracted, so that the horizontal period immediately before resetting can be made longer than the normal horizontal period. Therefore, in each block to which a synchronization signal is supplied, stable operation can be performed even when processing that cannot be completed unless a sufficient number of clocks are secured, for example, writing to or reading from a line memory, is always good. An image can be displayed on a display panel or the like.

  In the above description, the case where the counter with an extraction function of the present invention is applied to the video signal conversion apparatus shown in FIG. 8 has been described. However, the present invention is not particularly limited to this example, and the video signal conversion apparatus shown in FIG. The counter with the sampling function of the present invention can be similarly applied to the H counters 76 and 80 and the frequency division ratio counter 74, and the same effect can be obtained.

(Fifth embodiment)
Next explained is a video signal converter according to the fifth embodiment of the invention. FIG. 17 is a block diagram showing a configuration of a synchronization signal generating circuit used in the video signal conversion apparatus according to the fifth embodiment of the present invention.

  The synchronization signal generating circuit shown in FIG. 17 includes a serial bus decoding circuit 101, an edge detection circuit 102, an H counter 103, and a V counter 104.

  The serial bus decoding circuit 101 decodes a serial bus control signal SC such as an IIC bus. A bus terminal such as an IIC bus is generally controlled by a microcomputer and is normally provided in any LSI. The edge detection circuit 102 detects ON / OFF switching of vertical frequency conversion, which is one of the outputs of the serial bus decoding circuit 101, and generates a reset pulse RST when the ON state is changed from the OFF state.

  The H counter 103 receives a predetermined clock CLK and generates a horizontal synchronizing signal VH after vertical frequency conversion. The V counter 104 further divides the horizontal synchronizing signal VH output from the H counter 103 to generate a vertical synchronizing signal VH after vertical frequency conversion. The H counter 103 and the V counter 104 correspond to the H counter 76 and the V counter 78 shown in FIGS. 8 and 13, respectively. The other blocks not shown are the blocks shown in FIGS. Can be used.

  In the present embodiment, the serial bus decoding circuit 101 corresponds to the decoding means, the edge detection circuit 102 corresponds to the resetting means, the H counter 103 corresponds to the first counter, and the V counter 104 corresponds to the second counter. Equivalent to.

  Next, an operation when the video signal conversion apparatus having the synchronization signal generation circuit shown in FIG. 17 is created by one LSI and a plurality of the same LSIs are operated synchronously will be described.

  The serial bus decoding circuit 101 of each LSI uses a vertical synchronization signal VS of a video signal input to the device as a data load pulse. Therefore, by transmitting a control signal SC for turning on vertical frequency conversion simultaneously to the serial bus decoding circuits 101 of a plurality of LSIs within the same vertical period, the edge detection circuit 102 of each LSI operates at the same timing, and the reset pulse H counter 103 and V counter 104 are simultaneously reset by RST. As a result, if no measures are taken, the horizontal synchronization signal and the vertical synchronization signal after the vertical frequency conversion, which is essentially free, can be moved between the plurality of LSIs with the same phase.

  As described above, in this embodiment, when performing vertical frequency conversion, synchronization is performed between a plurality of LSIs by taking timing according to the change point of the control signal of the serial bus that is indispensable for setting the LSIs. A plurality of LSIs can be operated synchronously without passing signals, and delays due to the printed circuit board, pin capacitance, etc., and complexity of the printed circuit board wiring itself can be avoided.

  The present invention can be used in a video signal conversion device that converts a video signal into a video signal suitable for a display device.

DESCRIPTION OF SYMBOLS 1 Field memory 2 Memory control processing part 3 IP conversion processing part 4 Scan line conversion processing part 5 Horizontal pixel conversion processing part 6 Selector control part 7, 7a, 7b Synchronization processing part S1-S4 Selector 71, 72 PLL circuit 73, 74 minutes Frequency Counter 75 Crystal Oscillator 76, 77, 80 H Counter 78 V Counter 79 Selector 81, 82 H Counter with Extraction Function 83 Divider Ratio Counter with Extraction Function 91 Pulse Generation Circuit 92 Delay Circuit 93 Extraction Circuit 94 Maximum Value Detection Circuit 101 Serial bus decoding circuit 102 Edge detection circuit 103 H counter 104 V counter

Claims (9)

A video signal converter for converting an input video signal into a video signal suitable for a display device,
Storage means for storing video signals;
Vertical frequency conversion means for storing an input video signal in the storage means and converting a vertical frequency of the video signal stored in the storage means;
Scanning line conversion means for converting the number of scanning lines of the video signal output from the vertical frequency conversion means;
Synchronization control means for outputting a synchronization control signal for controlling operations of the vertical frequency conversion means and the scanning line conversion means to the vertical frequency conversion means and the scanning line conversion means,
The synchronization control means includes
First horizontal synchronizing signal generating means for generating a horizontal synchronizing signal that serves as a reference for the output side of the vertical frequency converting means and the input side of the scanning line converting means;
Vertical synchronizing signal generating means for generating a vertical synchronizing signal using a horizontal synchronizing signal generated from the first horizontal synchronizing signal generating means;
Second horizontal synchronizing signal generating means for generating a horizontal synchronizing signal which is a reference on the output side of the scanning line converting means;
The vertical synchronization signal of the video signal input to the vertical frequency conversion means and the vertical synchronization signal output from the vertical synchronization signal generation means are received, and the output side of the vertical frequency conversion means and the input side of the scanning line conversion means As a reference vertical synchronization signal, when the vertical frequency conversion means performs vertical frequency conversion, the vertical synchronization signal of the vertical synchronization signal generation means is selected and output, and the vertical frequency conversion means does not perform vertical frequency conversion. Selecting means for selecting and outputting a vertical synchronizing signal of the video signal input to the vertical frequency converting means in the case,
The video signal converter according to claim 1, wherein the first and second horizontal synchronizing signal generating means are reset by a vertical synchronizing signal output from the selecting means. The first horizontal synchronizing signal generating means includes a first counter for generating a horizontal synchronizing signal which serves as a reference on the output side of the vertical frequency converting means and on the input side of the scanning line converting means,
The vertical synchronization signal generating means includes a second counter for generating a vertical synchronization signal by dividing the horizontal synchronization signal generated from the first counter,
The second horizontal synchronizing signal generating means is
A third counter for generating a reference pulse of a PLL circuit for generating a predetermined clock;
A fourth counter that determines a frequency division ratio of the PLL circuit, divides a clock output from the PLL circuit, and generates a horizontal synchronization signal serving as a reference on the output side of the scanning line converter;
2. The video signal conversion apparatus according to claim 1, wherein the first and third counters are reset by a vertical synchronization signal output from the selection unit. 3. The video signal converter according to claim 2, wherein the fourth counter is reset by a vertical synchronization signal output from the selection unit. A video signal converter for converting an input video signal into a video signal suitable for a display device,
Scanning line conversion means for converting the number of scanning lines of an input video signal;
Storage means for storing video signals;
Vertical frequency conversion means for storing the video signal output from the scanning line conversion means in the storage means, and converting the vertical frequency of the video signal stored in the storage means;
Synchronization control means for outputting a synchronization control signal for controlling operations of the scanning line conversion means and the vertical frequency conversion means to the scanning line conversion means and the vertical frequency conversion means,
The synchronization control means includes
First horizontal synchronizing signal generating means for generating a horizontal synchronizing signal which serves as a reference for the output side of the scanning line converting means and the input side of the vertical frequency converting means;
Pulse generating means for generating a predetermined reference pulse;
Vertical synchronizing signal generating means for generating a vertical synchronizing signal using a reference pulse generated from the pulse generating means;
Second horizontal synchronizing signal generating means for generating a horizontal synchronizing signal which becomes a reference on the output side of the vertical frequency converting means using a reference pulse generated from the pulse generating means;
The vertical synchronization signal of the video signal input to the scanning line conversion unit and the vertical synchronization signal output from the vertical synchronization signal generation unit are received, and as the vertical synchronization signal serving as a reference on the output side of the vertical frequency conversion unit, When the vertical frequency converting means performs vertical frequency conversion, the vertical synchronizing signal of the vertical synchronizing signal generating means is selected and output, and when the vertical frequency converting means does not perform vertical frequency conversion, it is input to the scanning line converting means. Selecting means for selecting and outputting a vertical synchronization signal of the video signal to be output,
The first horizontal synchronizing signal generating means is reset by a vertical synchronizing signal of a video signal input to the scanning line converting means, and the pulse generating means is reset by a vertical synchronizing signal output from the selecting means. A video signal converter characterized by the above. The first horizontal synchronizing signal generating means includes a first counter for generating a horizontal synchronizing signal that serves as a reference on the output side of the scanning line converting means and on the input side of the vertical frequency converting means,
The pulse generating means includes a second counter that generates a horizontal synchronizing signal that serves as a reference pulse of a PLL circuit that generates a predetermined clock,
The vertical synchronization signal generating means includes a third counter for generating a vertical synchronization signal by dividing the horizontal synchronization signal generated from the second counter,
The second horizontal synchronization signal generating means determines a frequency division ratio of the PLL circuit, divides a clock output from the PLL circuit, and serves as a reference for the output side of the vertical frequency conversion means. Including a fourth counter for generating
The first counter is reset by a vertical synchronization signal of a video signal input to the scanning line conversion unit, and the second counter is reset by a vertical synchronization signal output from the selection unit. The video signal converter according to claim 4. 6. The video signal converter according to claim 5, wherein the fourth counter is reset by a vertical synchronization signal output from the selection unit. A video signal converter for converting an input video signal into a video signal suitable for a display device,
Storage means for storing video signals;
Vertical frequency conversion means for converting the vertical frequency of the video signal stored in the storage means;
Scanning line conversion means for converting the number of scanning lines of the video signal;
Synchronization control means for outputting a synchronization control signal for controlling operations of the vertical frequency conversion means and the scanning line conversion means to the vertical frequency conversion means and the scanning line conversion means,
The synchronization control means generates a horizontal synchronization signal that is reset by a vertical synchronization signal, and generates a horizontal synchronization signal that extracts the last pulse immediately before the horizontal synchronization signal is reset by the vertical synchronization signal from the horizontal synchronization signal. A video signal conversion apparatus comprising: means. The horizontal synchronizing signal generating means includes
Pulse generating means for counting input pulses and generating pulses at a predetermined timing;
A maximum value detecting means for counting the pulses output from the pulse generating means and detecting the last pulse having a maximum counter value;
Delay means for delaying a pulse output from the pulse generating means to generate a delayed pulse;
8. The video signal converter according to claim 7, further comprising: a sampling unit that extracts a delay pulse obtained by delaying the last pulse detected by the maximum value detection unit from the delay pulse output from the delay unit. A video signal converter for converting an input video signal into a video signal suitable for a display device,
Decoding means for decoding a control signal for setting the operation of the video signal converter;
A reset means for detecting a timing at which vertical frequency conversion is switched from an off state to an on state from a decoding result of the decoding means and outputting a reset pulse;
A first counter that generates a horizontal synchronization signal after vertical frequency conversion that is reset by a reset pulse output from the reset means;
A video signal converter comprising: a second counter that generates a vertical synchronization signal after vertical frequency conversion that is reset by a reset pulse output from the reset means.

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