JP2011081786A5 - - Google Patents

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Publication number
JP2011081786A5
JP2011081786A5 JP2010205642A JP2010205642A JP2011081786A5 JP 2011081786 A5 JP2011081786 A5 JP 2011081786A5 JP 2010205642 A JP2010205642 A JP 2010205642A JP 2010205642 A JP2010205642 A JP 2010205642A JP 2011081786 A5 JP2011081786 A5 JP 2011081786A5
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Japan
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layout
devices
matching
computer
selecting
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JP2010205642A
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English (en)
Japanese (ja)
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JP2011081786A (ja
JP5491333B2 (ja
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Priority claimed from US12/561,801 external-priority patent/US8176463B2/en
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Publication of JP5491333B2 publication Critical patent/JP5491333B2/ja
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JP2010205642A 2009-09-17 2010-09-14 集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング Expired - Fee Related JP5491333B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/561,801 US8176463B2 (en) 2009-09-17 2009-09-17 Modeling and simulating device mismatch for designing integrated circuits
US12/561,801 2009-09-17

Publications (3)

Publication Number Publication Date
JP2011081786A JP2011081786A (ja) 2011-04-21
JP2011081786A5 true JP2011081786A5 (https=) 2013-10-24
JP5491333B2 JP5491333B2 (ja) 2014-05-14

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JP2010205642A Expired - Fee Related JP5491333B2 (ja) 2009-09-17 2010-09-14 集積回路の設計のためのデバイスミスマッチのモデリングおよびシミュレーティング

Country Status (3)

Country Link
US (1) US8176463B2 (https=)
EP (1) EP2306348A1 (https=)
JP (1) JP5491333B2 (https=)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8645901B2 (en) * 2009-12-01 2014-02-04 Cadence Design Systems, Inc. Visualization and information display for shapes in displayed graphical images based on a cursor
TWI476619B (zh) * 2011-12-01 2015-03-11 Ncku Res & Dev Foundation 類比積體電路布局的電阻匹配方法
EP2762910A1 (en) 2013-01-30 2014-08-06 Samsung Electronics Co., Ltd Susceptibility-weighted magnetic resonance imaging
KR101502103B1 (ko) * 2013-01-30 2015-03-12 삼성전자 주식회사 자기공명영상장치 및 자화강조영상법
US9922146B2 (en) 2013-03-21 2018-03-20 Nxp Usa, Inc. Tool apparatus, method and computer program for designing an integrated circuit
US9255962B2 (en) 2013-08-15 2016-02-09 GlobalFoundries, Inc. Determining intra-die variation of an integrated circuit
CN104715094A (zh) * 2013-12-17 2015-06-17 北京华大九天软件有限公司 一种自动生成匹配器件方法
US9679094B2 (en) 2015-04-29 2017-06-13 International Business Machines Corporation Determining correlation coefficient(s) among different field effect transistor types and/or among different electrical parameter types
US20170046470A1 (en) * 2015-08-14 2017-02-16 Globalfoundries Inc. Process design kit for efficient and accurate mismatch simulation of analog circuits
US10216887B1 (en) 2015-12-18 2019-02-26 Cadence Design Systems, Inc. Methods, systems, and computer program products for implementing an electronic design with time varying resistors in power gating analysis
US10162931B2 (en) * 2017-03-28 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming serpentine resistor
US10262092B1 (en) * 2017-05-08 2019-04-16 Cadence Design Systems, Inc. Interactive platform to predict mismatch variation and contribution when adjusting component parameters
DE102017213583A1 (de) * 2017-08-04 2019-02-07 Siemens Aktiengesellschaft Verfahren zur Produktionsplanung
US10558780B1 (en) 2017-09-30 2020-02-11 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing schematic driven extracted views for an electronic design
US10678978B1 (en) * 2017-09-30 2020-06-09 Cadence Design Systems, Inc. Methods, systems, and computer program product for binding and back annotating an electronic design with a schematic driven extracted view
US10467370B1 (en) 2017-09-30 2019-11-05 Cadence Design Systems, Inc. Methods, systems, and computer program product for implementing a net as a transmission line model in a schematic driven extracted view for an electronic design
CN108256219B (zh) * 2018-01-18 2021-08-06 上海华虹宏力半导体制造有限公司 一种mos晶体管的器件失配模型的修正方法及系统
US10916042B2 (en) * 2019-03-12 2021-02-09 DecisionNext, Inc. Methods and devices for capturing heuristic information via a relationship tool
CN109933946B (zh) * 2019-03-29 2023-08-18 上海华力集成电路制造有限公司 一种半导体器件的分析方法
US10997333B1 (en) 2019-12-05 2021-05-04 Cadence Design Systems, Inc. Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view
TWI717302B (zh) * 2020-07-30 2021-01-21 頂極科技股份有限公司 半導體製程零配件的質變檢測系統及方法
US11361142B2 (en) * 2020-08-31 2022-06-14 Siemens Industry Software Inc. Estimating integrated circuit yield from modeled response to scaling of distribution samples
US20230195984A1 (en) * 2021-12-22 2023-06-22 Texas Instruments Incorporated Method for timing signoff in mixed-transistor designs
GB2620947B (en) * 2022-07-26 2025-02-19 Agile Analog Ltd Analogue circuit design

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7418683B1 (en) * 2005-09-21 2008-08-26 Cadence Design Systems, Inc Constraint assistant for circuit design

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