JP2011077225A5

JP2011077225A5 -

Info

Publication number: JP2011077225A5
Application number: JP2009225906A
Authority: JP
Filing date: 2009-09-30
Publication date: 2012-05-31
Anticipated expiration: 2029-09-30

Claims

A semiconductor chip having metal electrode films formed on both sides of the semiconductor substrate;
A first low thermal expansion plate bonded via a first bonding layer under the semiconductor chip;
A base electrode joined via a second joining layer under the first low thermal expansion plate;
A second low thermal expansion plate bonded via a third bonding layer on the semiconductor chip;
A lead electrode bonded on the second low thermal expansion plate via a fourth bonding layer;
A part of the base electrode and the lead electrode, a semiconductor chip, a low thermal expansion plate, and an insulating resin formed so as to cover each bonding layer,
The first and third bonding layers are made of a lead-free solder material having a liquidus temperature of 300 to 500 ° C., and the second and third bonding layers are porous with a porosity of 20 to 70%. wherein a that consists quality of Ag layer.

A semiconductor chip having metal electrode films formed on both sides of the semiconductor substrate;
A low thermal expansion plate bonded via a first bonding layer under the semiconductor chip;
A base electrode joined via a second joining layer under the low thermal expansion plate;
A lead electrode joined via a third joining layer on the semiconductor chip;
A portion of the lead electrode and base electrode, a semiconductor chip, a low thermal expansion plate, and an insulating resin formed to cover each bonding layer;
The first bonding layer is composed of a solder material containing no lead having a liquidus temperature of 300 to 500 ° C., and the second and third bonding layers are porous Ag layers having a porosity of 20 to 70%. A semiconductor device having a structured structure.

In claim 1 or 2,
Liquid phase temperature: 300-500 ° C. lead-free solder material is composed of multi-component high-temperature solder whose main constituent elements are Sn, Sb, Ag, Cu,
A semiconductor device characterized in that the coefficient of thermal expansion in the surface direction of the low thermal expansion plate is 8 ppm or less.

In claim 1 or 2,
The base electrode, the lead electrode, the low thermal expansion plate and the semiconductor chip are Ni-plated parts,
The structure is such that a porous Ag film having a smaller porosity and smaller pore size than the joining layer is formed on the connection surface of the Ni-plated component that is metal-joined with a porous Ag layer. A semiconductor device characterized by the above.

In claim 1 or 2,
Any one of Cu, Ni, Al, Mg, Mo, and W plated with a noble metal having a maximum particle size of 1/2 or more of the Ag bonding layer in the bonding layer composed of a porous Ag layer A semiconductor device characterized in that the above highly conductive metal particles are dispersedly arranged.

In a semiconductor device comprising a semiconductor chip, a lead electrode, a base electrode, a low thermal expansion plate, and an insulating resin,
A porous Ag metallized film having a porosity of 1 to 30%, a closed pore ratio of 50% or more, and a thickness of 1 to 30 μm is formed on the Ni plating surface of the member. A porous Ag bonding layer having a porosity of 20 to 70%, an open system porosity ratio of 50% or more, and a thickness of 70 to 500 μm is formed on the porous layer. Having a connection structure in which at least a part of the open cavity in the Ag bonding layer is filled with a thermosetting resin;
A semiconductor device characterized in that the entire structure is covered with an insulating resin except for part of a lead electrode and a base electrode.

In Claim 6, the lead electrode and the base electrode are members plated with Ni on Cu,
An Ag metallized film is formed only in a limited region around a connection surface.

7. The semiconductor device according to claim 6, wherein the porous Ag metallized film has a structure in which Ag particles equal to or larger than the film thickness are embedded.

8. The semiconductor device according to claim 7, wherein the Ag metallized film is an Ag film formed by a method of applying a solution of an organic Ag complex on a Ni surface and heating and baking in the air.

A highly conductive lead electrode and base electrode with Ni plating on the surface;
A low thermal expansion plate with Ni plating on the surface;
A semiconductor chip in which a metal electrode film containing Ni is formed on both sides of a semiconductor substrate;
In the manufacturing method of a semiconductor device made of an insulating resin formed so as to cover the whole except for a part of the lead electrode and the base electrode,
An organic Ag complex solution or an organic solution in which nano-Ag particles are dispersed is applied to the joint surface of the lead electrode and the base electrode and one surface of the low thermal expansion plate, and is heat-baked at 200 to 350 ° C. in the atmosphere to be Ag metallized. Process,
A step of producing a joining component by joining the Ni plating side of the low thermal expansion plate to both surfaces of a semiconductor chip with a high-temperature lead-free solder by heat treatment in a reducing atmosphere;
A sintered type Ag paste is applied to the Ag metallized region of the base electrode, and the joining component of the semiconductor chip and the low thermal expansion plate is mounted thereon. Further, the sintered type Ag paste is applied to the Ag metallized region on the upper side of the joining component. A mounting step of applying an Ag paste and mounting a lead electrode thereon;
Heating and mounting the mounted assembly to a temperature of 200 to 350 ° C. at a moderate temperature increase of 20 ° C./min or less in the atmosphere;
A method of manufacturing a semiconductor device, comprising: supplying an insulating resin so as to cover the entire surface except for a part of the lead electrode and the base electrode, and performing a heating and curing process.

In claim 10,
A method for manufacturing a semiconductor device, comprising adding a step of impregnating a porous sintered Ag bonding layer with a liquid thermosetting resin after the assembly is sintered and bonded, followed by heating and curing.

In claim 11,
Before impregnating the porous sintered Ag bonding layer with the liquid thermosetting resin, a step of applying an organic Zn complex solution to the assembly bonded body and performing a baking treatment in the atmosphere at a temperature of 250 to 350 ° C. was added. A method for manufacturing a semiconductor device.

Ag particles having an average particle size of 0.1 to 3 μm formed with an organic protective film that decomposes at 200 ° C. or less on the surface, an organic solvent for pasting, Ag particles having a particle size of 3 to 30 μm, A paste-like connecting material composed of spherical noble metal particles having a diameter of 50 to 500 μm or highly conductive particles such as noble metal plated spherical Cu, Ni, Al, Mg, Mo and W.

The connecting part has a structure in which the difference in the thermal expansion coefficient of the connecting member is 5 ppm or more and the length of the connecting surface in the longitudinal direction is 3 mm or more and is metal-bonded through a porous Ag layer. It has a structure where the connection points of less than 5ppm are joined with lead-free high-temperature solder,
A semiconductor device comprising a semiconductor chip, one or more low thermal expansion members, and a plurality of highly conductive electrode members.

A semiconductor chip in which a metal electrode film having a noble metal on the outermost surface is formed on both sides of the semiconductor substrate;
A base electrode in which a noble metal film having pores is formed on the outermost surface bonded via a first bonding layer under the semiconductor chip;
A lead electrode formed with a noble metal film having a hole on the outermost surface bonded to the semiconductor chip via a second bonding layer;
Insulating resin formed so as to cover a part of the lead electrode and the base electrode, the semiconductor chip and each bonding layer,
The semiconductor device according to claim 1, wherein the first and second bonding layers have a structure composed of a porous Ag layer having a porosity of 20 to 70%.