JP2011066251A - Method of manufacturing semiconductor substrate - Google Patents

Method of manufacturing semiconductor substrate Download PDF

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JP2011066251A
JP2011066251A JP2009216306A JP2009216306A JP2011066251A JP 2011066251 A JP2011066251 A JP 2011066251A JP 2009216306 A JP2009216306 A JP 2009216306A JP 2009216306 A JP2009216306 A JP 2009216306A JP 2011066251 A JP2011066251 A JP 2011066251A
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semiconductor substrate
opening
hole
electrode pad
active surface
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Kazuji Azuma
和司 東
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Panasonic Corp
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Panasonic Corp
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<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor substrate, capable of achieving a high quality through type electrode in higher productivity at lower cost, even when the semiconductor substrate is thick. <P>SOLUTION: An electrode pad (102) having an opening (104) including an exposed active surface is formed to a semiconductor substrate (101). A recess (105a) is formed toward the surface in the opposite side of the active surface from the opening (104). An insulating film (106) is formed at the internal side of the recess (105a). A conductive path (107) is formed on the surface of the insulating film (106) and the electrode pad (102). Thereafter, the semiconductor substrate (101) is formed thinner from the surface in the opposite side of the active surface and is then provided through the bottom of the recess (105a). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、貫通電極を有する半導体基板の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor substrate having a through electrode.

半導体を半導体基板に実装してパッケージングする際には、前記半導体基板に貫通電極を形成することによって、小型、低背パッケージングを実現している。従来の貫通電極の形成方法としては、特許文献1などに記載されたものがある。   When a semiconductor is mounted on a semiconductor substrate and packaged, a small and low-profile packaging is realized by forming a through electrode in the semiconductor substrate. As a conventional method for forming a through electrode, there is one described in Patent Document 1 or the like.

図7は特許文献1の貫通電極形成方法を示す。
これは、半導体基板の素子が作り込まれるアクティブ面の反対側からアクティブ面に向けて貫通孔と導通経路を形成するものがある。11は半導体基板、12は第1のシリコン酸化膜、13は細孔、14は採壁に第2のシリコン酸化膜、15は金属薄膜、16は第2の金属薄膜、17は貫通電極である。
FIG. 7 shows the through electrode forming method of Patent Document 1.
In some cases, a through-hole and a conduction path are formed from the side opposite to the active surface on which elements of the semiconductor substrate are formed toward the active surface. 11 is a semiconductor substrate, 12 is a first silicon oxide film, 13 is a pore, 14 is a second silicon oxide film on the wall, 15 is a metal thin film, 16 is a second metal thin film, and 17 is a through electrode. .

図7(a)では、半導体基板11のアクティブ面に第1のシリコン酸化膜12aを形成し、アクティブ面の反対側に第1のシリコン酸化膜12bを形成する。
図7(b)では、第1のシリコン酸化膜12bの一部にフォトリソグラフでパターンを形成した後にドライエッチングで除去する。
In FIG. 7A, a first silicon oxide film 12a is formed on the active surface of the semiconductor substrate 11, and a first silicon oxide film 12b is formed on the opposite side of the active surface.
In FIG. 7B, a pattern is formed on a part of the first silicon oxide film 12b by photolithography, and then removed by dry etching.

図7(c)では、フォトリソグラフでパターンを形成した後にドライエッチングで半導体基板11に細孔13を形成する。
図7(d)では、細孔13の側面を第2のシリコン酸化膜14で絶縁処理する。
In FIG. 7C, after forming a pattern by photolithography, the pores 13 are formed in the semiconductor substrate 11 by dry etching.
In FIG. 7D, the side surfaces of the pores 13 are insulated with the second silicon oxide film 14.

図7(e)では、半導体基板11のアクティブ面に金属薄膜15と第2の金属薄膜16を重ねて形成する。
図7(f)では、細孔13を通してアクティブ面側の第1のシリコン酸化膜12aをドライエッチングにより除去する。
In FIG. 7E, the metal thin film 15 and the second metal thin film 16 are formed on the active surface of the semiconductor substrate 11 so as to overlap each other.
In FIG. 7F, the first silicon oxide film 12a on the active surface side is removed by dry etching through the pores 13.

図7(g)では、金属薄膜15に導通するように細孔13に導電性材料を充填して貫通電極17を形成する。   In FIG. 7G, the through electrode 17 is formed by filling the pores 13 with a conductive material so as to be electrically connected to the metal thin film 15.

特開2004−94859号公報JP 2004-94859 A

しかしながら、前記従来の構成では、半導体基板11のアクティブ面とは反対側の面から貫通孔を形成するため、図7(c)においてアクティブ面の薄膜12aがプロセス処理によりオーバーエッチングが発生したり、熱応力により破壊される可能性があるという課題を有している。   However, in the conventional configuration, since the through-hole is formed from the surface opposite to the active surface of the semiconductor substrate 11, the thin film 12a on the active surface in FIG. There is a problem that it may be broken by thermal stress.

また、半導体基板11が厚い場合、貫通孔形成においては代表的な加工速度が15μm/minであるため、たとえば半導体基板が300μmの場合、20minの時間を要し、生産性が低いという課題を有している。   Further, when the semiconductor substrate 11 is thick, a typical processing speed is 15 μm / min in the formation of the through hole. For example, when the semiconductor substrate is 300 μm, it takes 20 min, and the productivity is low. is doing.

本発明は、半導体基板が厚い場合においても貫通電極を高生産性、高品質で低コストで実現できる半導体基板の製造方法を提供することを目的とする。   An object of the present invention is to provide a method of manufacturing a semiconductor substrate that can realize a through electrode with high productivity, high quality, and low cost even when the semiconductor substrate is thick.

本発明の半導体基板の製造方法は、半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドを形成し、前記開口部から半導体基板に前記アクティブ面から反対側の面に向かって前記反対側の面に達しない凹部を形成し、前記凹部の内側に絶縁膜を形成し、前記絶縁膜と電極パッドの表面に導電経路を形成し、前記半導体基板を前記反対側の面から前記半導体基板を薄型化して前記凹部の底部を前記反対側の面に貫通させることを特徴とする。前記凹部をドライエッチ、ブラスト、レーザー加工方法の何れかによって形成する。また、前記凹部の深さ方向の形状をテーパー状に形成することが好ましい。   According to the method of manufacturing a semiconductor substrate of the present invention, an electrode pad having an opening through which an active surface of the semiconductor substrate is exposed is formed on the semiconductor substrate, and the semiconductor substrate is directed from the opening to the opposite surface from the active surface. Forming a recess that does not reach the opposite surface, forming an insulating film inside the recess, forming a conductive path on the surface of the insulating film and the electrode pad, and removing the semiconductor substrate from the opposite surface The semiconductor substrate is thinned so that the bottom of the recess penetrates the opposite surface. The concave portion is formed by any of dry etching, blasting, and laser processing. Moreover, it is preferable to form the shape of the said recessed part in the depth direction in a taper shape.

また本発明の半導体基板の製造方法は、半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドを形成し、前記アクティブ面とは反対側の面から前記半導体基板を薄型化し、前記開口部から半導体基板に前記アクティブ面から反対側の面に向かって前記反対側の面に貫通した孔を形成し、前記孔の内側に絶縁膜を形成し、前記絶縁膜と前記電極パッドの表面に導電膜を形成することを特徴とする。前記孔をドライエッチ、ブラスト、レーザー加工方法の何れかによって前記半導体基板に形成する。前記孔の形状をテーパー状に形成することが好ましい。   The method of manufacturing a semiconductor substrate according to the present invention includes forming an electrode pad having an opening through which an active surface of the semiconductor substrate is exposed on the semiconductor substrate, thinning the semiconductor substrate from a surface opposite to the active surface, A hole penetrating the opposite surface from the active surface to the opposite surface is formed in the semiconductor substrate from the opening, an insulating film is formed inside the hole, and the insulating film and the electrode pad A conductive film is formed on the surface. The holes are formed in the semiconductor substrate by any of dry etching, blasting, and laser processing methods. It is preferable to form the hole in a tapered shape.

本発明の半導体基板は、半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドと、前記開口部によって露出した前記半導体基板の前記アクティブ面から反対側の面に貫通して形成された貫通孔と、前記貫通孔の内側と前記開口部によって露出した半導体基板の前記アクティブ面に形成された絶縁膜と、電極パッドの表面と前記絶縁膜の表面に形成され端部が前記半導体基板の前記反対側の面に露出した導電経路とを設けたことを特徴とする。   The semiconductor substrate of the present invention is formed by penetrating an electrode pad having an opening through which an active surface of the semiconductor substrate is exposed in the semiconductor substrate and a surface opposite to the active surface of the semiconductor substrate exposed by the opening. An insulating film formed on the active surface of the semiconductor substrate exposed by the inside of the through hole and the opening, an electrode pad surface, and an end formed on the surface of the insulating film. A conductive path exposed on the opposite surface of the substrate is provided.

また本発明の半導体基板は、半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドと、前記開口部によって露出した前記半導体基板の前記アクティブ面から反対側の面に貫通して形成され前記半導体基板の前記アクティブ面の開口が前記反対側の面の開口よりも大きい貫通孔と、前記貫通孔の内側と前記開口部によって露出した半導体基板の前記アクティブ面に形成された絶縁膜と、電極パッドの表面と前記絶縁膜の表面に形成され端部が前記半導体基板の前記反対側の面に露出した導電経路とを設けたことを特徴とする。前記貫通孔の内側の水平断面に凹凸を有することが好ましい。前記貫通孔の断面が円形であり、前記貫通孔の前記アクティブ面での開口と前記反対側の面での開口との直径の比が、0.5以上0.8以下であることが好ましい。   According to another aspect of the present invention, there is provided a semiconductor substrate including an electrode pad having an opening through which an active surface of the semiconductor substrate is exposed, and a surface opposite to the active surface of the semiconductor substrate exposed through the opening. A through hole formed on the active surface of the semiconductor substrate that is exposed by the opening and the inside of the through hole and the opening, the opening of the active surface of the semiconductor substrate being larger than the opening of the opposite surface; And a conductive path formed on the surface of the electrode pad and the surface of the insulating film and having an end exposed on the opposite surface of the semiconductor substrate. It is preferable that the horizontal cross section inside the through hole has irregularities. It is preferable that a cross section of the through hole is circular, and a ratio of a diameter of an opening on the active surface of the through hole and an opening on the opposite surface is 0.5 or more and 0.8 or less.

この構成によると、半導体基板のアクティブ面からの貫通電極形成が可能となり、アクティブ面の薄膜がプロセス処理によりオーバーエッチングが発生したり、熱応力により破壊される従来の問題を回避できるとともに、レーザー加工プロセスの使用が可能となり貫通電極形成の低コスト化を実現できる。   According to this configuration, it is possible to form a through electrode from the active surface of the semiconductor substrate, and it is possible to avoid the conventional problems that the thin film on the active surface is over-etched due to process processing or is destroyed by thermal stress, and laser processing The process can be used, and the cost for forming the through electrode can be reduced.

また、半導体基板をアクティブ面とは反対側の面から薄型化することによって、従来よりも生産性を向上する効果がある。   Further, by reducing the thickness of the semiconductor substrate from the surface opposite to the active surface, there is an effect of improving productivity as compared with the conventional case.

本発明の実施の形態1の半導体基板の拡大平面図とそのA−A断面図The enlarged plan view of the semiconductor substrate of Embodiment 1 of this invention, and its AA sectional drawing 同実施の形態の製造工程の説明図で、左側が各工程での半導体基板の平面図、その右側が拡大断面図It is explanatory drawing of the manufacturing process of the embodiment, The left side is a top view of the semiconductor substrate in each process, The right side is an expanded sectional view 本発明の実施の形態2の半導体基板の製造工程の説明図で、左側が各工程での半導体基板の平面図、その右側が拡大断面図FIG. 8 is an explanatory diagram of the manufacturing process of the semiconductor substrate according to the second embodiment of the present invention, the left side is a plan view of the semiconductor substrate in each step, and the right side is an enlarged cross-sectional view. 本発明の実施の形態3の半導体基板の拡大平面図とそのA−A断面図The enlarged plan view of the semiconductor substrate of Embodiment 3 of this invention, and its AA sectional drawing 同実施の形態の半導体基板の製造工程の説明図で、左側が各工程での半導体基板の平面図、その右側が拡大断面図In the explanatory view of the manufacturing process of the semiconductor substrate of the embodiment, the left side is a plan view of the semiconductor substrate in each step, the right side is an enlarged sectional view 本発明の実施の形態4の半導体基板の拡大平面図とそのA−A断面図The enlarged plan view of the semiconductor substrate of Embodiment 4 of this invention, and its AA sectional drawing 特許文献1に記載された従来の貫通電極形成方法のプロセスフロー図Process flow diagram of conventional through electrode forming method described in Patent Document 1

以下、本発明の各実施の形態を図1〜図6に基づいて説明する。
(実施の形態1)
図1と図2は本発明の実施の形態1を示す。
Hereinafter, each embodiment of the present invention will be described with reference to FIGS.
(Embodiment 1)
1 and 2 show Embodiment 1 of the present invention.

図1は貫通電極が形成された半導体基板の拡大平面図とそのA−A断面図である。この半導体基板は、図2に示す工程で作成されている。図2(a)〜図2(e)では左側に平面図、その右側に拡大断面図を示す。   FIG. 1 is an enlarged plan view of a semiconductor substrate on which a through electrode is formed, and an AA cross-sectional view thereof. This semiconductor substrate is produced by the process shown in FIG. 2A to 2E show a plan view on the left side and an enlarged cross-sectional view on the right side.

図2(a)では、Si、SiC、GaAsなどの素材で形成された半導体基板101に開口部104を有する電極を形成する。半導体基板101はサイズがφ3インチ〜φ12インチ、厚みが0.2mm〜0.7mm程度である。具体的には、半導体基板101の上に形成されている酸化膜103とこの酸化膜103の上に形成されている電極パッド102に対して、半導体基板101を露出させる開口部104を形成する。酸化膜103は素材がSiOなどでその厚みは0.1μm〜1μm程度である。電極パッド102は素材がAl、Al−Cuなどでそのサイズが50角〜100角、厚みが0.3mm〜1mmである。 In FIG. 2A, an electrode having an opening 104 is formed on a semiconductor substrate 101 formed of a material such as Si, SiC, or GaAs. The semiconductor substrate 101 has a size of φ3 inch to φ12 inch and a thickness of about 0.2 mm to 0.7 mm. Specifically, an opening 104 for exposing the semiconductor substrate 101 is formed in the oxide film 103 formed on the semiconductor substrate 101 and the electrode pad 102 formed on the oxide film 103. The oxide film 103 is made of SiO 2 or the like and has a thickness of about 0.1 μm to 1 μm. The electrode pad 102 is made of Al, Al-Cu, etc., and has a size of 50 to 100 squares and a thickness of 0.3 mm to 1 mm.

酸化膜103上の電極パッド102の部分的に存在しない構造は半導体IC加工プロセスにおいて、フォトリソグラフを活用した酸化膜のパターニングによって形成することができる。また、開口部104は電極パッド102のパターニング形成時にマスクをデザインすることによって、追加のプロセス無しに実現できる。開口部104は円形で、その大きさは電極パッド102のサイズよりも10〜20%程度小さくした。たとえば電極パッド102が100μmの場合、中心部に80μm〜90μm径にするのがよい。   A structure in which the electrode pad 102 on the oxide film 103 does not exist partially can be formed by patterning the oxide film using photolithography in a semiconductor IC processing process. Further, the opening 104 can be realized without an additional process by designing a mask when the electrode pad 102 is patterned. The opening 104 is circular and its size is about 10 to 20% smaller than the size of the electrode pad 102. For example, when the electrode pad 102 is 100 μm, the diameter may be 80 μm to 90 μm at the center.

図2(b)では、開口部104の内側で半導体基板101の上にφ50μm〜φ100μmの凹部105aを形成する。
凹部105aの加工は、加工するデザインをフォトリソグラフプロセスを用いて20μm〜30μm厚のレジストによりマスクし、ドライエッチング、ブラスト、レーザーにより開口された部分を加工する。ここでは半導体基板101の厚みに対して貫通しないように途中まで凹部105aを形成した。
In FIG. 2B, a recess 105 a having a diameter of 50 μm to 100 μm is formed on the semiconductor substrate 101 inside the opening 104.
The recess 105a is processed by masking a design to be processed with a resist having a thickness of 20 μm to 30 μm using a photolithographic process, and processing a portion opened by dry etching, blasting, or laser. Here, the recess 105 a is formed partway so as not to penetrate the thickness of the semiconductor substrate 101.

図2(c)では、凹部105aの内周面と開口部104の内側で半導体基板101の表面に1μm〜5μm程度のSiOなどの絶縁膜106を形成する。この絶縁膜106は、後に形成する導電経路107と半導体基板101とが電気的にショートしてリークさせないためである。電極パッド102の表面に絶縁膜106が形成されないように、電極パッド102の表面をフォトリソグラフプロセスでマスクをした状態でCVDプロセスを用いた酸化膜形成や絶縁材料をインクジエット、スプレなどの印刷方法で形成する。 In FIG. 2C, an insulating film 106 such as SiO 2 having a thickness of about 1 μm to 5 μm is formed on the surface of the semiconductor substrate 101 inside the inner peripheral surface of the recess 105 a and the opening 104. This insulating film 106 is for preventing a leakage due to an electrical short circuit between a conductive path 107 and a semiconductor substrate 101 to be formed later. Oxide film formation using a CVD process in a state where the surface of the electrode pad 102 is masked by a photolithographic process so that the insulating film 106 is not formed on the surface of the electrode pad 102, or a printing method such as ink jet or spraying an insulating material Form with.

図2(d)では、絶縁膜106と電極パッド102の上に導電材料によって導電経路107を形成する。具体的には、絶縁膜106の上に0.1μm〜0.3μm程度のTi/Cuスパッタ、蒸着膜を形成し、その後、電解、または無電解Cuメッキで5μm〜10μm程度の厚みを確保する。導電経路107の形成は導電ペーストをインクジエット、印刷方法などで充填することによっても形成できる。   In FIG. 2D, a conductive path 107 is formed of a conductive material on the insulating film 106 and the electrode pad 102. Specifically, a Ti / Cu sputtering or vapor deposition film of about 0.1 μm to 0.3 μm is formed on the insulating film 106, and then a thickness of about 5 μm to 10 μm is secured by electrolysis or electroless Cu plating. . The conductive path 107 can also be formed by filling a conductive paste with an ink jet or printing method.

図2(e)では、半導体基板101の裏面の表面粗さを制御するためにアクティブ面の裏面側から研磨を施す。これにより、半導体基板101の表から半導体基板101の裏に貫通する導電経路を有した貫通電極を形成できる。その後は半導体基板101の裏面側に絶縁膜と配線パターンを形成し、基板に実装できるようにBGA電極を形成するなどの処理を実施する。なお、凹部105aによって形成された貫通孔を、図1では105aaとして図示した。   In FIG. 2E, polishing is performed from the back surface side of the active surface in order to control the surface roughness of the back surface of the semiconductor substrate 101. Thereby, a through electrode having a conductive path penetrating from the front of the semiconductor substrate 101 to the back of the semiconductor substrate 101 can be formed. Thereafter, an insulating film and a wiring pattern are formed on the back surface side of the semiconductor substrate 101, and a process such as forming a BGA electrode so as to be mounted on the substrate is performed. In addition, the through-hole formed by the recessed part 105a was illustrated as 105aa in FIG.

かかる構成によれば、ウエハの設計を変更するのみでプロセスを変更することなく、アクティブ面からの貫通電極の形成が可能となり、コストを上昇させることなく実施できるものである。   According to such a configuration, the through electrode can be formed from the active surface without changing the process only by changing the design of the wafer, and can be carried out without increasing the cost.

そして、半導体基板101のアクティブ面とは反対側の面から形成した場合のように、アクティブ面の薄膜がプロセス処理によりオーバーエッチングが発生して不良や熱応力により破壊されることもない。   Then, as in the case where the semiconductor substrate 101 is formed from the surface opposite to the active surface, the thin film on the active surface is not over-etched by the process process and is not destroyed by defects or thermal stress.

また、半導体基板101が厚い場合、貫通孔形成においては代表的な加工速度が15μm/minであるため、たとえば半導体基板101が300μmの場合、20minの時間を要し、生産性が低いという課題に対し、アクティブ面からの貫通電極形成により貫通電極形成後に半導体基板101を裏面側から研磨して薄くするプロセスの実施により、生産性を向上する効果がある。   Further, when the semiconductor substrate 101 is thick, a typical processing speed is 15 μm / min in the formation of the through hole. For example, when the semiconductor substrate 101 is 300 μm, it takes 20 minutes and the productivity is low. On the other hand, by forming a through electrode from the active surface and performing a process of polishing and thinning the semiconductor substrate 101 from the back side after forming the through electrode, there is an effect of improving productivity.

また、レーザ加工のように電極パッド102の部分に熱変化が生じるというプロセス上の問題が生じないため、レーザ加工プロセスの使用が可能となり貫通電極形成の低コスト化を実現することができる。   In addition, since there is no problem in the process of causing a thermal change in the electrode pad 102 as in laser processing, the laser processing process can be used, and the cost for forming the through electrode can be reduced.

また、半導体基板101のアクティブ面とは反対側の面からの孔加工の場合、Siを孔加工した後に酸化膜の加工を施す必要がある。本構造を活用した方法によれば孔加工部に酸化膜が存在していないため、酸化膜加工プロセスが削除でき、プロセス歩留りによる品質低下を防ぐと共に、加工コストを下げることができる。   In the case of drilling from the surface opposite to the active surface of the semiconductor substrate 101, it is necessary to process the oxide film after drilling Si. According to the method utilizing this structure, since the oxide film is not present in the hole processing portion, the oxide film processing process can be eliminated, quality deterioration due to process yield can be prevented, and processing cost can be reduced.

(実施の形態2)
図3は本発明の実施の形態2を示す。
実施の形態1では最終の図2(e)で半導体基板101を研磨して薄くしたが、図3に示す工程では図2(a)から図2(b)に至る間で半導体基板101を研磨して薄くしている点が異なっている。
(Embodiment 2)
FIG. 3 shows a second embodiment of the present invention.
In the first embodiment, the semiconductor substrate 101 is polished and thinned in the final FIG. 2E, but in the process shown in FIG. 3, the semiconductor substrate 101 is polished between FIG. 2A and FIG. The difference is that it is thinned.

図3(a)では、Si、SiC、GaAsなどの素材で形成された半導体基板101に開口部104を有する電極を形成する。半導体基板101の上に形成されている酸化膜103とこの酸化膜103の上に形成されている電極パッド102に対して、半導体基板101を露出させる開口部104を形成する。   In FIG. 3A, an electrode having an opening 104 is formed on a semiconductor substrate 101 formed of a material such as Si, SiC, or GaAs. An opening 104 for exposing the semiconductor substrate 101 is formed in the oxide film 103 formed on the semiconductor substrate 101 and the electrode pad 102 formed on the oxide film 103.

図3(b)では、半導体基板101の裏面側からグラインダなどを用いて任意の厚みに削る。
図3(c)では、開口部104の内側で半導体基板101の上に半導体基板101の裏面側に貫通したφ50μm〜φ100μmの孔105bを形成する。
In FIG. 3B, the semiconductor substrate 101 is cut to an arbitrary thickness using a grinder or the like from the back surface side.
In FIG. 3C, a hole 105 b having a diameter of 50 μm to φ100 μm penetrating on the back surface side of the semiconductor substrate 101 is formed on the semiconductor substrate 101 inside the opening 104.

図3(d)では、孔105bの内周面と開口部104の内側で半導体基板101の表面に1μm〜5μm程度のSiOなどの絶縁膜106を形成する。電極パッド102の表面に絶縁膜106が形成されないように、電極パッド102の表面をフォトリソグラフプロセスでマスクをした状態でCVDプロセスを用いた酸化膜形成や絶縁材料をインクジエット、スプレなどの印刷方法で形成する。 In FIG. 3D, an insulating film 106 such as SiO 2 having a thickness of about 1 μm to 5 μm is formed on the surface of the semiconductor substrate 101 inside the hole 105 b and inside the opening 104. Oxide film formation using a CVD process in a state where the surface of the electrode pad 102 is masked by a photolithographic process so that the insulating film 106 is not formed on the surface of the electrode pad 102, or a printing method such as ink jet or spraying an insulating material Form with.

図3(e)では、絶縁膜106と電極パッド102の上に導電材料によって導電経路107を形成する。これにより、半導体基板101の表から半導体基板101の裏面に貫通する導電経路を有した貫通電極を形成できる。その後は半導体基板101の裏面側に絶縁膜と配線パターンを形成し、基板に実装できるようにBGA電極を形成するなどの処理を実施する。   In FIG. 3E, a conductive path 107 is formed of a conductive material on the insulating film 106 and the electrode pad 102. Thereby, a through electrode having a conductive path penetrating from the front surface of the semiconductor substrate 101 to the back surface of the semiconductor substrate 101 can be formed. Thereafter, an insulating film and a wiring pattern are formed on the back surface side of the semiconductor substrate 101, and a process such as forming a BGA electrode so as to be mounted on the substrate is performed.

この構成によれば、孔105bを加工前に半導体基板101の厚みを薄く制御することにより、孔加工に必要な工数を最低必要条件にのみ実施することができるため無駄がなく、余分なコスト上昇がなくなる。   According to this configuration, by controlling the thickness of the semiconductor substrate 101 to be thin before the hole 105b is processed, the man-hours required for the hole processing can be performed only to the minimum necessary conditions, so there is no waste and an extra cost increases. Disappears.

(実施の形態3)
図4と図5は本発明の実施の形態3を示す。
実施の形態1では図2(b)で半導体基板101に形成した凹部105aの形状が、半導体基板101のアクティブ側の開口から底部に向かって単一の円形であったが、実施の形態3では、凹部105aの形状が図4(a)と図4(b)に示すように、半導体基板101のアクティブ側の開口から底部に向かって次第に径が小さくなる形状である点が異なっている。
(Embodiment 3)
4 and 5 show Embodiment 3 of the present invention.
In the first embodiment, the shape of the recess 105a formed in the semiconductor substrate 101 in FIG. 2B is a single circle from the opening on the active side of the semiconductor substrate 101 toward the bottom, but in the third embodiment, As shown in FIGS. 4A and 4B, the shape of the recess 105a is different in that the diameter gradually decreases from the opening on the active side of the semiconductor substrate 101 toward the bottom.

図5(a)では、Si、SiC、GaAsなどの素材で形成された半導体基板101に開口部104を有する電極を形成する。具体的には、半導体基板101の上に形成されている酸化膜103とこの酸化膜103の上に形成されている電極パッド102に対して、半導体基板101を露出させる開口部104を形成する。酸化膜103は素材がSiOなどでその厚みは0.1μm〜1μm程度である。電極パッド102は素材がAl、Al−Cuなどでそのサイズが50角〜100角、厚みが0.3mm〜1mmである。 In FIG. 5A, an electrode having an opening 104 is formed on a semiconductor substrate 101 formed of a material such as Si, SiC, or GaAs. Specifically, an opening 104 for exposing the semiconductor substrate 101 is formed in the oxide film 103 formed on the semiconductor substrate 101 and the electrode pad 102 formed on the oxide film 103. The oxide film 103 is made of SiO 2 or the like and has a thickness of about 0.1 μm to 1 μm. The electrode pad 102 is made of Al, Al-Cu, etc., and has a size of 50 to 100 squares and a thickness of 0.3 mm to 1 mm.

酸化膜103上の電極パッド102の部分的に存在しない構造は半導体IC加工プロセスにおいて、フォトリソグラフを活用した酸化膜のパターニングによって形成することができる。また、開口部104は電極パッド102のパターニング形成時にマスクをデザインすることによって、追加のプロセス無しに実現できる。開口部104は円形で、その大きさは電極パッド102のサイズよりも10〜20%程度小さくした。たとえば電極パッド102が100μmの場合、中心部に80μm〜90μm径にするのがよい。   A structure in which the electrode pad 102 on the oxide film 103 does not exist partially can be formed by patterning the oxide film using photolithography in a semiconductor IC processing process. Further, the opening 104 can be realized without an additional process by designing a mask when the electrode pad 102 is patterned. The opening 104 is circular and its size is about 10 to 20% smaller than the size of the electrode pad 102. For example, when the electrode pad 102 is 100 μm, the diameter may be 80 μm to 90 μm at the center.

図5(b)では、開口部104の内側で半導体基板101の上にドライエッチ、レーザ、ブラストなどの方法により角度が60°〜85°のテーパー形状の凹部105cを形成する。ここでは半導体基板101の厚みに対して貫通しないように途中まで凹部105cを形成した。   In FIG. 5B, a tapered recess 105c having an angle of 60 ° to 85 ° is formed on the semiconductor substrate 101 inside the opening 104 by a method such as dry etching, laser, or blasting. Here, the recess 105 c is formed partway so as not to penetrate the thickness of the semiconductor substrate 101.

図5(c)では、凹部105cの内周面と開口部104の内側で半導体基板101の表面に1μm〜5μm程度のSiOなどの絶縁膜106を形成する。この絶縁膜106は、後に形成する導電経路107と半導体基板101とが電気的にショートしてリークさせないためである。電極パッド102の表面に絶縁膜106が形成されないように、電極パッド102の表面をフォトリソグラフプロセスでマスクをした状態でCVDプロセスを用いた酸化膜形成や絶縁材料をインクジエット、スプレなどの印刷方法で形成する。 In FIG. 5C, an insulating film 106 such as SiO 2 having a thickness of about 1 μm to 5 μm is formed on the surface of the semiconductor substrate 101 inside the inner peripheral surface of the recess 105 c and the opening 104. This insulating film 106 is for preventing a leakage due to an electrical short circuit between a conductive path 107 and a semiconductor substrate 101 to be formed later. Oxide film formation using a CVD process in a state where the surface of the electrode pad 102 is masked by a photolithographic process so that the insulating film 106 is not formed on the surface of the electrode pad 102, or a printing method such as ink jet or spraying an insulating material Form with.

図5(d)では、絶縁膜106と電極パッド102の上に導電材料によって導電経路107を形成する。
図5(e)では、半導体基板101の裏面の表面粗さを制御するためにアクティブ面の裏面側から研磨を施す。これにより、半導体基板101の表から半導体基板101の裏に貫通する導電経路を有した貫通電極を形成できる。その後は半導体基板101の裏面側に絶縁膜と配線パターンを形成し、基板に実装できるようにBGA電極を形成するなどの処理を実施する。なお、凹部105cによって形成されたテーパー状の貫通孔を、図4では105ccとして図示した。
In FIG. 5D, a conductive path 107 is formed of a conductive material on the insulating film 106 and the electrode pad 102.
In FIG. 5E, polishing is performed from the back surface side of the active surface in order to control the surface roughness of the back surface of the semiconductor substrate 101. Thereby, a through electrode having a conductive path penetrating from the front of the semiconductor substrate 101 to the back of the semiconductor substrate 101 can be formed. Thereafter, an insulating film and a wiring pattern are formed on the back surface side of the semiconductor substrate 101, and a process such as forming a BGA electrode so as to be mounted on the substrate is performed. The tapered through hole formed by the recess 105c is shown as 105cc in FIG.

この構成によれば、貫通孔をテーパー形状にすることにより、スパッタ、メッキが容易となり、歩留りロスによる品質低下を低減しコストを抑えることができる。テーパー形状の貫通孔の上面の開口の直径と下面の開口の直径の比は0.8〜0.5がよい。0.5では、下面の直径が上面の直径の半分となる。それ以下ならば、接続の場合の位置ズレのため導通がとれなくなる。0.8以上の場合は膜を形成しにくい、特に、エッジ部分での膜形成がしにくい。   According to this configuration, by forming the through hole in a tapered shape, sputtering and plating can be facilitated, quality deterioration due to yield loss can be reduced, and cost can be suppressed. The ratio of the diameter of the opening on the upper surface of the tapered through hole to the diameter of the opening on the lower surface is preferably 0.8 to 0.5. At 0.5, the lower surface diameter is half of the upper surface diameter. If it is less than that, continuity cannot be obtained due to misalignment in the case of connection. When the ratio is 0.8 or more, it is difficult to form a film, and in particular, it is difficult to form a film at an edge portion.

(実施の形態4)
図6は本発明の実施の形態4を示す。
上記の各実施の形態では半導体基板101に形成した貫通電極の水平の断面形状が円形であったが、この実施の形態4では図6(a)と図6(b)に示すように、貫通電極の水平の断面形状が星形である点が異なっている。
(Embodiment 4)
FIG. 6 shows a fourth embodiment of the present invention.
In each of the above embodiments, the horizontal cross-sectional shape of the through electrode formed on the semiconductor substrate 101 is circular. However, in this fourth embodiment, as shown in FIGS. The difference is that the horizontal cross-sectional shape of the electrode is a star.

この水平の断面形状が星形の貫通電極は、電極パッド102に対して、半導体基板101を露出させた開口部104の領域に、レジストなどによりマスクを形成し、ドライエッチ、レーザ、ブラストなどの方法により半導体基板101に水平の断面形状が星形の凹部105aを形成し、星形の凹部105aの表面にSiOなどの酸化膜103を形成した後、その上にTiスパッタ、蒸着、Cuメッキなどで導電経路107を形成する。なお、凹部105aによって形成されたテーパー状の貫通孔を、図6では105abとして図示した。 This through-hole electrode having a star-shaped horizontal cross section is formed by forming a mask with a resist or the like in the region of the opening 104 where the semiconductor substrate 101 is exposed with respect to the electrode pad 102, and performing dry etching, laser, blasting, etc. After forming a star-shaped recess 105a having a horizontal cross-sectional shape on the semiconductor substrate 101 by the method, and forming an oxide film 103 such as SiO 2 on the surface of the star-shaped recess 105a, Ti sputtering, vapor deposition, Cu plating is formed thereon. The conductive path 107 is formed by, for example. Note that the tapered through hole formed by the recess 105a is illustrated as 105ab in FIG.

かかる構成によれば、貫通孔形状を星型にすることにより、側面の表面積が増加し、ビア抵抗の低下と放熱性が向上する。
この実施の形態では星形の凹部105aを形成する場合を例に挙げて説明したが、図3に示した孔105bの平面形状を星形にした場合も同様に実施できる。
According to such a configuration, by making the through-hole shape into a star shape, the surface area of the side surface is increased, and the via resistance is reduced and the heat dissipation is improved.
In this embodiment, the case where the star-shaped concave portion 105a is formed has been described as an example. However, the present invention can be similarly implemented when the planar shape of the hole 105b shown in FIG.

なお、貫通電極の水平の断面形状が星形の場合を例に挙げて説明したが、凹凸のある丸、ギア型、凹凸のある四角などその他の多角形でも同様の効果を得ることができる。さらに、これらを実施の形態3のようにテーパー形状に形成することもできる。   In addition, although the case where the horizontal cross-sectional shape of the through electrode is a star has been described as an example, the same effect can be obtained with other polygons such as an uneven circle, a gear shape, and an uneven square. Further, they can be formed in a tapered shape as in the third embodiment.

上記の各実施の形態では、一つの電極パッドに対して一つの貫通電極を形成した場合を例に挙げて説明したが、一つの電極パッドに対して複数の貫通電極を形成する場合も同様である。   In each of the above embodiments, the case where one through electrode is formed for one electrode pad has been described as an example, but the same applies to the case where a plurality of through electrodes are formed for one electrode pad. is there.

本発明は半導体パッケージングの小型化、薄型化、低コスト化、信号伝送の高速化などが実現でき、電子機器の発展に広く貢献できる。   The present invention can realize downsizing, thinning, cost reduction, and high-speed signal transmission of semiconductor packaging, and can contribute widely to the development of electronic devices.

101 半導体基板
104 開口部
103 酸化膜
102 電極パッド
105a 凹部
106 絶縁膜
107 導電経路
105aa 貫通孔
105b 孔
105c テーパー形状の凹部
105cc 貫通孔
105ab 貫通孔
101 Semiconductor substrate 104 Opening 103 Oxide film 102 Electrode pad 105a Recess 106 Insulating film 107 Conductive path 105aa Through hole 105b Hole 105c Tapered recess 105cc Through hole 105ab Through hole

Claims (10)

半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドを形成し、
前記開口部から半導体基板に前記アクティブ面から反対側の面に向かって前記反対側の面に達しない凹部を形成し、
前記凹部の内側に絶縁膜を形成し、
前記絶縁膜と電極パッドの表面に導電経路を形成し、
前記半導体基板を前記反対側の面から前記半導体基板を薄型化して前記凹部の底部を前記反対側の面に貫通させる
半導体基板の製造方法。
Forming an electrode pad on the semiconductor substrate having an opening through which the active surface of the semiconductor substrate is exposed;
Forming a recess that does not reach the opposite surface from the active surface to the opposite surface from the opening to the semiconductor substrate;
Forming an insulating film inside the recess,
Forming a conductive path on the surface of the insulating film and the electrode pad;
A method of manufacturing a semiconductor substrate, wherein the semiconductor substrate is thinned from the opposite surface and the bottom of the concave portion is penetrated through the opposite surface.
前記凹部をドライエッチ、ブラスト、レーザー加工方法の何れかによって形成する
請求項1記載の半導体基板の製造方法。
The method of manufacturing a semiconductor substrate according to claim 1, wherein the recess is formed by any one of dry etching, blasting, and laser processing.
前記凹部の深さ方向の形状をテーパー状に形成する
請求項1記載の半導体基板の製造方法。
The method of manufacturing a semiconductor substrate according to claim 1, wherein a shape of the concave portion in a depth direction is formed in a tapered shape.
半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドを形成し、
前記アクティブ面とは反対側の面から前記半導体基板を薄型化し、
前記開口部から半導体基板に前記アクティブ面から反対側の面に向かって前記反対側の面に貫通した孔を形成し、
前記孔の内側に絶縁膜を形成し、
前記絶縁膜と前記電極パッドの表面に導電経路を形成する
半導体基板の製造方法。
Forming an electrode pad on the semiconductor substrate having an opening through which the active surface of the semiconductor substrate is exposed;
Thinning the semiconductor substrate from the surface opposite to the active surface,
Forming a hole penetrating from the opening to the opposite surface toward the opposite surface from the active surface to the semiconductor substrate;
Forming an insulating film inside the hole;
A method of manufacturing a semiconductor substrate, wherein a conductive path is formed on surfaces of the insulating film and the electrode pad.
前記孔をドライエッチ、ブラスト、レーザー加工方法の何れかによって前記半導体基板に形成する
請求項1記載の半導体基板の製造方法。
The method of manufacturing a semiconductor substrate according to claim 1, wherein the hole is formed in the semiconductor substrate by any one of dry etching, blasting, and laser processing.
前記孔の形状をテーパー状に形成する請求項4記載の半導体基板の製造方法。   The method for manufacturing a semiconductor substrate according to claim 4, wherein the hole is formed in a tapered shape. 半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドと、
前記開口部によって露出した前記半導体基板の前記アクティブ面から反対側の面に貫通して形成された貫通孔と、
前記貫通孔の内側と前記開口部によって露出した半導体基板の前記アクティブ面に形成された絶縁膜と、
電極パッドの表面と前記絶縁膜の表面に形成され端部が前記半導体基板の前記反対側の面に露出した導電経路と
を設けた半導体基板。
An electrode pad having an opening exposing an active surface of the semiconductor substrate on the semiconductor substrate;
A through-hole formed through the surface opposite to the active surface of the semiconductor substrate exposed by the opening;
An insulating film formed on the active surface of the semiconductor substrate exposed by the inside of the through hole and the opening;
A semiconductor substrate provided with a surface of an electrode pad and a conductive path formed on the surface of the insulating film and having an end exposed on the opposite surface of the semiconductor substrate.
半導体基板に前記半導体基板のアクティブ面が露出する開口部を有する電極パッドと、
前記開口部によって露出した前記半導体基板の前記アクティブ面から反対側の面に貫通して形成され前記半導体基板の前記アクティブ面の開口が前記反対側の面の開口よりも大きい貫通孔と、
前記貫通孔の内側と前記開口部によって露出した半導体基板の前記アクティブ面に形成された絶縁膜と、
電極パッドの表面と前記絶縁膜の表面に形成され端部が前記半導体基板の前記反対側の面に露出した導電経路と
を設けた半導体基板。
An electrode pad having an opening exposing an active surface of the semiconductor substrate on the semiconductor substrate;
A through hole formed by penetrating from the active surface of the semiconductor substrate exposed by the opening to the opposite surface, the opening of the active surface of the semiconductor substrate being larger than the opening of the opposite surface;
An insulating film formed on the active surface of the semiconductor substrate exposed by the inside of the through hole and the opening;
A semiconductor substrate provided with a surface of an electrode pad and a conductive path formed on the surface of the insulating film and having an end exposed on the opposite surface of the semiconductor substrate.
前記貫通孔の内側の水平断面に凹凸を有する請求項7記載の半導体基板。   The semiconductor substrate according to claim 7, wherein the horizontal cross section inside the through hole has irregularities. 前記貫通孔の断面が円形であり、前記貫通孔の前記アクティブ面での開口と前記反対側の面での開口との直径の比が、0.5以上0.8以下である請求項8記載の半導体基板。   The cross section of the through hole is circular, and a ratio of a diameter of the opening on the active surface of the through hole and the opening on the opposite surface is 0.5 or more and 0.8 or less. Semiconductor substrate.
JP2009216306A 2009-09-18 2009-09-18 Method of manufacturing semiconductor substrate Pending JP2011066251A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018088468A1 (en) * 2016-11-14 2018-05-17 旭硝子株式会社 Substrate having non-through hole

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018088468A1 (en) * 2016-11-14 2018-05-17 旭硝子株式会社 Substrate having non-through hole
JPWO2018088468A1 (en) * 2016-11-14 2019-10-03 Agc株式会社 Substrate with non-through holes
TWI759353B (en) * 2016-11-14 2022-04-01 日商Agc股份有限公司 Substrate with non-through holes

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