JP2011064618A5 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2011064618A5
JP2011064618A5 JP2009216571A JP2009216571A JP2011064618A5 JP 2011064618 A5 JP2011064618 A5 JP 2011064618A5 JP 2009216571 A JP2009216571 A JP 2009216571A JP 2009216571 A JP2009216571 A JP 2009216571A JP 2011064618 A5 JP2011064618 A5 JP 2011064618A5
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Japan
Prior art keywords
clock
semiconductor device
unit
test
count data
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JP2009216571A
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JP2011064618A (ja
JP5266173B2 (ja
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Priority to JP2009216571A priority Critical patent/JP5266173B2/ja
Priority claimed from JP2009216571A external-priority patent/JP5266173B2/ja
Priority to US12/883,825 priority patent/US8346499B2/en
Publication of JP2011064618A publication Critical patent/JP2011064618A/ja
Publication of JP2011064618A5 publication Critical patent/JP2011064618A5/ja
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Publication of JP5266173B2 publication Critical patent/JP5266173B2/ja
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Claims (1)

  1. 入力パタンに基づいて動作する演算回路部を備える半導体装置であって、
    バーンイン試験用クロックに基づいて内部クロックを生成する内部クロック生成部と、
    前記バーンイン試験用クロックを計数してクロックカウントデータを生成するクロック計数部と、
    ＩＤＤＱ試験で用いられるＩＤＤＱ試験用クロックカウントデータを記憶する記憶部と、
    前記クロックカウントデータと前記ＩＤＤＱ試験用クロックカウントデータとが一致した場合に、前記内部クロック生成部による前記内部クロックの生成を停止させるクロック生成停止制御部と、
    前記内部クロックに同期して、ＩＤＤＱ試験用パタンを前記演算回路部に入力する試験用パタン生成部と、
    を備える半導体装置。
JP2009216571A 2009-09-18 2009-09-18 半導体装置 Expired - Fee Related JP5266173B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009216571A JP5266173B2 (ja) 2009-09-18 2009-09-18 半導体装置
US12/883,825 US8346499B2 (en) 2009-09-18 2010-09-16 Semiconductor device and its testing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009216571A JP5266173B2 (ja) 2009-09-18 2009-09-18 半導体装置

Publications (3)

Publication Number Publication Date
JP2011064618A JP2011064618A (ja) 2011-03-31
JP2011064618A5 true JP2011064618A5 (ja) 2012-04-05
JP5266173B2 JP5266173B2 (ja) 2013-08-21

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JP2009216571A Expired - Fee Related JP5266173B2 (ja) 2009-09-18 2009-09-18 半導体装置

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US (1) US8346499B2 (ja)
JP (1) JP5266173B2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112130053B (zh) * 2020-08-11 2024-05-14 上海华虹集成电路有限责任公司 一种在ate上进行芯片功能同步测试的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62204171A (ja) 1986-03-05 1987-09-08 Hitachi Ltd 集積回路のモニタ−ドエ−ジング方法
JPH05251534A (ja) 1991-11-20 1993-09-28 Nec Corp 半導体集積回路装置
JPH11142471A (ja) * 1997-11-07 1999-05-28 Nec Corp バーンイン試験方法及びバーンイン試験装置
JP2003156534A (ja) * 2001-11-21 2003-05-30 Hitachi Ltd 半導体集積回路
US20040025123A1 (en) * 2002-08-01 2004-02-05 Angilivelil Josey G. System and method to facilitate evaluation of integrated circuits through delay testing
US7486098B2 (en) * 2005-06-16 2009-02-03 International Business Machines Corporation Integrated circuit testing method using well bias modification
JP4708269B2 (ja) * 2006-06-22 2011-06-22 シャープ株式会社 半導体装置、及び半導体装置の検査方法

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