GB2468094A - DMA data transfer - Google Patents
DMA data transfer Download PDFInfo
- Publication number
- GB2468094A GB2468094A GB1011025A GB201011025A GB2468094A GB 2468094 A GB2468094 A GB 2468094A GB 1011025 A GB1011025 A GB 1011025A GB 201011025 A GB201011025 A GB 201011025A GB 2468094 A GB2468094 A GB 2468094A
- Authority
- GB
- United Kingdom
- Prior art keywords
- transfer
- trigger
- amount
- data
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
An integrated circuit comprising: a plurality of on-chip devices; a DMA engine; and a CPU for executing code to set up the data transfer engine to perform a transfer, the set-up comprising indicating the address of a source and destination device. The integrated circuit also comprises timing means arranged to generate a trigger at a time after the execution of the set-up code; and transfer control means arranged to determine, at that time, an amount of data to be transferred. The DMA engine is arranged to receive the trigger from the timing means and an indication of the amount from the transfer control means, and to transfer that amount of data to the destination peripheral interface in response to the trigger.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0724439A GB0724439D0 (en) | 2007-12-14 | 2007-12-14 | Data transfer |
| PCT/EP2008/066781 WO2009077341A1 (en) | 2007-12-14 | 2008-12-04 | Dma data transfer |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB201011025D0 GB201011025D0 (en) | 2010-08-18 |
| GB2468094A true GB2468094A (en) | 2010-08-25 |
| GB2468094B GB2468094B (en) | 2012-09-26 |
Family
ID=39048127
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0724439A Ceased GB0724439D0 (en) | 2007-12-14 | 2007-12-14 | Data transfer |
| GB1011025.2A Active GB2468094B (en) | 2007-12-14 | 2008-12-04 | DMA data transfer |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0724439A Ceased GB0724439D0 (en) | 2007-12-14 | 2007-12-14 | Data transfer |
Country Status (3)
| Country | Link |
|---|---|
| GB (2) | GB0724439D0 (en) |
| TW (1) | TW200937199A (en) |
| WO (1) | WO2009077341A1 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2953308B1 (en) | 2009-12-01 | 2011-12-09 | Bull Sas | SYSTEM FOR AUTHORIZING DIRECT TRANSFERS OF DATA BETWEEN MEMORIES OF SEVERAL ELEMENTS OF THIS SYSTEM |
| FR2953307B1 (en) | 2009-12-01 | 2011-12-16 | Bull Sas | MEMORY DIRECT ACCESS CONTROLLER FOR DIRECT TRANSFER OF DATA BETWEEN MEMORIES OF MULTIPLE PERIPHERAL DEVICES |
| GB2497528B (en) | 2011-12-12 | 2020-04-22 | Nordic Semiconductor Asa | Peripheral communication |
| US9875202B2 (en) | 2015-03-09 | 2018-01-23 | Nordic Semiconductor Asa | Peripheral communication system with shortcut path |
| GB2539455A (en) | 2015-06-16 | 2016-12-21 | Nordic Semiconductor Asa | Memory watch unit |
| GB2540341B (en) | 2015-06-16 | 2019-06-26 | Nordic Semiconductor Asa | Event generating unit |
| WO2017052659A1 (en) | 2015-09-25 | 2017-03-30 | Intel Corporation | Microelectronic package communication using radio interfaces connected through wiring |
| CN110069432B (en) * | 2018-01-22 | 2023-03-24 | 小华半导体有限公司 | Peripheral circuit interconnection system with data processing function and linkage method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905911A (en) * | 1990-06-29 | 1999-05-18 | Fujitsu Limited | Data transfer system which determines a size of data being transferred between a memory and an input/output device |
| EP0997822A2 (en) * | 1998-10-28 | 2000-05-03 | Nec Corporation | DMA control method and apparatus |
| US20060010264A1 (en) * | 2000-06-09 | 2006-01-12 | Rader Sheila M | Integrated processor platform supporting wireless handheld multi-media devices |
-
2007
- 2007-12-14 GB GB0724439A patent/GB0724439D0/en not_active Ceased
-
2008
- 2008-12-04 GB GB1011025.2A patent/GB2468094B/en active Active
- 2008-12-04 WO PCT/EP2008/066781 patent/WO2009077341A1/en active Application Filing
- 2008-12-08 TW TW97147627A patent/TW200937199A/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5905911A (en) * | 1990-06-29 | 1999-05-18 | Fujitsu Limited | Data transfer system which determines a size of data being transferred between a memory and an input/output device |
| EP0997822A2 (en) * | 1998-10-28 | 2000-05-03 | Nec Corporation | DMA control method and apparatus |
| US20060010264A1 (en) * | 2000-06-09 | 2006-01-12 | Rader Sheila M | Integrated processor platform supporting wireless handheld multi-media devices |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0724439D0 (en) | 2008-01-30 |
| GB201011025D0 (en) | 2010-08-18 |
| GB2468094B (en) | 2012-09-26 |
| TW200937199A (en) | 2009-09-01 |
| WO2009077341A1 (en) | 2009-06-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) |
Free format text: REGISTERED BETWEEN 20130516 AND 20130522 |