JP2011062565A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent mismatching of the control states of a game-control microcomputer and a put-out control microcomputer when performing initialization processing according to an operation of an operation means, and which enables development of random numbers of a high random property. <P>SOLUTION: When power supply is started, following determination whether a clear signal is in an ON state, processing for controlling progress of a game is performed after waiting for a delay time to pass over. Moreover, when the power supply is started, after performing setting for developing the random numbers in a random number circuit, the game-control microcomputer is set in an interrupt-authorized state. In the setting of the random number circuit, a start value of a first round for generating the random numbers is set at a value based on a proper ID number given for each game-control microcomputer (a step S126). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified When a variable display device that variably displays is provided, and a prize game medium is paid out as a prize based on the winning of a game medium in a prize area in the game area, and the display result of the variable display becomes a predetermined specific display result The present invention relates to a gaming machine that controls a specific gaming state advantageous to a player.

  As a gaming machine such as a pachinko gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and a predetermined number of prize balls are awarded when the game medium wins a prize area such as a prize opening provided in the game area. There are many things that can be paid out to players. Further, variable display is performed by updating or scrolling display of predetermined identification information (hereinafter referred to as display symbol) on a display device such as a liquid crystal display (hereinafter referred to as LCD: Liquid Crystal Display), and a predetermined game based on the display result. There is a game that enhances the game interest by a so-called variable display game that determines whether or not to add value.

  A special figure game that is performed as one of the variable display games is a variable display of a display symbol based on the detection of a game ball that passes through the start winning opening (that the variable display start condition is satisfied). In the game, the “hit” is defined as a case where the stop symbol form when the display is completely stopped is a predetermined specific display form. In this special figure game, when a “hit” is made, a special electric accessory called a big prize opening or an attacker is opened, and a state in which a game ball can be won extremely easily is provided to a player for a certain period of time. . Such a state is referred to as a “specific game state” or a “hit game state”.

  The progress of the game in such a gaming machine is controlled by game control means such as a microcomputer. Here, when the payout control means for controlling the prize ball payout is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board. It is controlled by the game control microcomputer. Therefore, the number of winning balls based on winning is determined by the game control means, and a control command indicating the number of winning balls is transmitted to the payout control microcomputer. Then, the payout control microcomputer executes a process of paying out the number of prize balls corresponding to the winning based on the control command from the game control microcomputer.

  In addition, in order to save the gaming state when power supply is stopped, such as a power failure, a detection signal from a power supply monitoring means for detecting a decrease in power supply voltage is input to the main board and the payout control board, and the game control microcomputer and payout control Each of the microcomputers has been proposed to execute a process of saving data for restoring a state when power supply is stopped (for example, Patent Document 1). According to the technique described in Patent Document 1, when power supply to a gaming machine is started, the gaming control microcomputer is activated against the rise of the payout control microcomputer (the control operation can be executed). By configuring so that the rise is delayed, it becomes possible for the payout control means to reliably receive a command transmitted from the game control microcomputer to the payout control microcomputer. Furthermore, according to the technology described in Patent Document 1, if a clear switch is provided and the clear switch is pressed when power supply to the gaming machine is started, the game control microcomputer and the payout Each of the control microcomputers executes the initialization process, whereby the data for restoring the state when the power supply is stopped can be cleared.

  Furthermore, when the power supply to the gaming machine is started, it is generated periodically after setting to update the random number value used to determine whether or not the random number circuit is set to “big hit” Has been proposed that permits execution of timer interrupt processing (for example, Patent Document 2).

JP 2003-103025 A Japanese Patent Laying-Open No. 2005-103166

  According to the technique described in Patent Document 1, when the power supply to the gaming machine is started, the rise of the game control microcomputer is delayed with respect to the rise of the payout control microcomputer. The point in time when the signal indicating that the game is present is shifted between the payout control microcomputer and the game control microcomputer. Therefore, even when the payout control microcomputer detects that the clear switch is pressed, there is a possibility that the game control microcomputer cannot detect the press of the clear switch. In this case, since only the payout control microcomputer executes the initialization process, there arises a problem that the control state cannot be matched with the game control microcomputer.

  Further, according to the technique described in Patent Document 2, the initial value of the random number (start value of the first round) set when power supply to the gaming machine is started is different even in different game control microcomputers. I can not let you. Therefore, there is a problem in that a “big hit” may be illegally generated by generating a signal for taking in a random number value at a timing when a predetermined time has elapsed from the start of power supply.

  The present invention has been made in view of the above circumstances, and when executing initialization processing in response to an operation of an operation means such as a clear switch, the control states of the game control microcomputer and the payout control microcomputer are controlled. It is an object of the present invention to prevent the occurrence of inconsistency and enable generation of random numbers with high randomness.

  (1) In order to solve the above-described problem, the gaming machine according to the present application is variable after a variable display execution condition (for example, a game ball wins a start winning opening provided in the normal variable winning ball apparatus 6) is established. A plurality of types of identification information (for example, special symbols and decorations) that can be identified based on the establishment of a display start condition (for example, completion of the previous special symbol game or jackpot gaming state by the special symbol display device 4). A variable display device (for example, a special symbol display device 4 or an image display device 5) is variably displayed, and a winning area in the game area (for example, a start winning opening provided in the normal variable winning ball apparatus 6, special variable) The prize game medium is paid out as a prize based on the fact that a game medium (for example, a game ball or the like) has won a prize at the big prize opening provided in the winning ball apparatus 7 or the prize winning openings 42A to 42D. When the display result of the odd display becomes a predetermined specific display result (for example, a jackpot symbol or a finalized combination symbol of the jackpot combination), control is performed to a specific gaming state (for example, a jackpot gaming state) advantageous to the player A game machine (for example, a pachinko game machine 1) that detects that a game ball has won the winning area and outputs a winning detection signal (for example, a start port switch 22, a count switch 24, a winning port) Switches 25A to 25D, etc.), an initialization operation means (for example, clear switch 304) that outputs an initialization request signal (for example, a clear signal) in response to an operation, and a payout means (for example, a payout game medium). A payout motor 51) and a random number circuit (for example, a random number circuit 103) for generating random numbers, and a winning test from the winning detection means. A game control process (for example, the processes of S71 to S84 by a timer interrupt) that controls the progress of the game when the output signal is input is executed, and a payout control signal for controlling the payout means is provided in the gaming machine. A game control board (for example, a game control microcomputer 100 or the like) on which a game control microcomputer (for example, the game control microcomputer 100 or the like) for transmitting an effect control signal for controlling an electrical component for performance (for example, the image display device 5 or the like) is mounted. For the payout control for executing the payout control processing (for example, the processing of S551 to S558 by timer interruption) in accordance with the payout control signal transmitted by the microcomputer for game control and the main board 11) Dispensing with a microcomputer (for example, dispensation control microcomputer 150) An effect control microcomputer (for example, an effect control microcomputer 120) that controls the control electric parts (for example, the payout control board 15 and the like) and the effect electric components according to the effect control signal transmitted by the game control microcomputer. Etc.) and when the state of power used in the gaming machine becomes a predetermined state (for example, the period when VLP is +20 V or less is 56 milliseconds or more) Power monitoring means (for example, a power monitoring circuit 303) that outputs a power failure signal (for example, a power interruption signal) when the power is continued, and the random number circuit receives numerical data based on a predetermined signal input. In a predetermined range that can be updated, from a predetermined initial value to a predetermined final value, it is updated cyclically according to a predetermined order. Value update means (for example, random number generation circuits 173A and 173B and random number sequence change circuits 176A and 176B) and random value storage means (for example, random value register 181A, 181B etc.), the game control microcomputer stores data indicating the progress of the game, and retains the stored contents for at least a predetermined period even when the power supply to the gaming machine is stopped In response to input of the means (for example, the power-backed RAM 106) and the winning detection signal, a payout number signal (for example, first to third payout number designation commands) indicating the number of prize game media to be paid out The number-of-payout signal transmission means (for example, the CPU 104) transmits to the microcomputer for payout control as the payout control signal. After executing any one of the processes of steps S307, S310, and S311 and the like, the portion for executing the payout command control process of step S81) and the fact that the power monitoring means outputs the power failure signal, Game control-side power supply stop time processing means (for example, a portion where the CPU 104 executes the main-side power-off processing in step S30) for executing a game control-side power supply stop time process for storing data indicating the progress state; Initialization operation determination means for determining whether or not an initialization request signal is output from the initialization operation means when power supply to the gaming machine is started (for example, a portion where the CPU 104 executes the process of step S7) And the like, and after the determination by the initialization operation determination means, at least the payout control process is started to execute the game control process. A delay processing unit that executes a delay process that delays until the execution of (for example, a portion in which the CPU 104 executes the processes of steps S9 to S11), and after the delay process by the delay processing unit is executed, On the condition that the initialization operation determination means determines that the initialization request signal has not been output, the game progress state is determined based on the data indicating the game progress state stored in the game control storage means. The game control side recovery process is executed by the game control side recovery process means (for example, the part where the CPU 104 executes the process of step S17) and the game control side recovery process means for executing the game control side recovery process to be restored. The restoration notification signal for notifying that the game control side restoration process has been executed is used as the production control signal. A recovery notification signal transmission means (for example, a portion where the CPU 104 executes the process of step S18) to be transmitted to the control microcomputer and the random number circuit for generating the random number after power supply to the gaming machine is started. Random circuit setting means for setting (for example, a portion that executes 12-bit random number initial setting process or 16-bit random number initial setting process in step S25 after the CPU 104 executes the process of step S24), and the random circuit setting means After the setting is performed, the timer interrupt process execution permitting means (for example, the part where the CPU 104 executes the process of step S28) that permits the execution of the timer interrupt process that occurs periodically, and the timer interrupt process are being executed. , Execution condition determination means for determining whether or not the variable display execution condition is satisfied (for example, CPU 104 is a part for executing the processing of step S421), and the execution condition determination means determines that the variable display execution condition is satisfied, the random number value stored by the random value storage means is Random value reading means for reading (for example, the part where the CPU 104 executes the winning process in step S422) and determining whether the random number value read by the random value reading means matches predetermined determination value data And a display result determining means for determining whether or not the display result in the variable display is a specific display result (for example, a portion in which the CPU 104 executes the variable display start process in step S431). The microcomputer has a payout number signal receiving means (for example, receiving the payout number signal transmitted by the payout number signal transmitting means). After the CPU 214 executes the processing corresponding to steps S51 to S55, the payout of the prize game medium indicated by the payout number signal received by the payout number signal receiving means, etc. Stores unpaid-out number data (for example, data set in a prize ball unpaid counter) indicating the number of unpaid prize game media that have not been paid out of the number, and power supply to the gaming machine is stopped. Even at least for a predetermined period, the payout control storage means (for example, the RAM 216 backed up by a power source) that retains the stored contents and the payout means are driven to control the number of unpaid premiums as indicated by the unpaid-out number data. Premium game medium payout control means for executing payout control for paying out game media (for example, the CPU 214 executes a prize ball payout operation process in step S663). A payout control side power supply stop process for executing a payout control side power supply stop process for storing the unpaid number data in response to the power supply monitoring means outputting the power failure signal. When the power supply to the means (for example, the part where the CPU 214 executes the payout-side power cut-off process in step S522) and the power supply to the gaming machine is started, the initialization request signal is not output from the initialization operation means. On the condition, the payout control side recovery processing means for executing the payout control side recovery processing (for example, the CPU 214 performs a step of recovering the payout to the state where the payout is possible based on the unpaid number data stored in the payout control storage means) Etc.), and the production control microcomputer transmits the recovery information transmitted by the recovery notification signal transmitting means. When an intelligence signal is received, recovery notification means (for example, the CPU 123 executes the process of step S942 to notify that the game control side recovery process has been executed by controlling the electrical parts for the effect, 76 (A), a portion for displaying a recovery screen on the image display device 5), and at least one of the game control microcomputer and the payout control microcomputer is between the other. A serial communication circuit (for example, serial communication circuits 108 and 218) that performs serial communication in the communication control means for controlling the serial communication operation by the serial communication circuit (for example, the CPU 104 performs the serial communication initial setting process and step in step S26) The part for executing the interrupt initial setting process of S27, The serial communication initial setting process of 518 and the part for executing the interrupt initial setting process of step S519, etc.), and the serial communication circuit, when any of a plurality of interrupt request conditions is satisfied, Including an interrupt request notification means (for example, SIST1 of the serial status register 204) for notifying the communication control means of an interrupt request according to an interrupt request condition established, and the interrupt request notified by the interrupt request notification means is a serial communication When an error occurs in, an interrupt request condition is satisfied, and an error interrupt request (for example, an interrupt request at the time of a parity error, an interrupt request at the time of an overrun error, for causing the communication control means to execute processing corresponding to the occurrence of the error) , Interrupt request at framing error, noise error Including an interrupt request, etc.) at the time over. Note that the gaming control microcomputer, when the power supply to the gaming machine is started, determines that the initialization request signal is output by the initialization operation determining means, and stores the gaming control storage means. Game control side initialization processing means for executing initialization processing for initializing stored contents may be included. Further, the data indicating the progress of the game includes premium game medium number data (for example, the total number of prize balls) that can specify the number of premium game media to be paid out in response to the input of a winning detection signal to the game control microcomputer. Data set in the counter, data set in the first to third payout number instruction counters, and the like) may be included.

According to such a configuration, after the game control microcomputer determines whether or not the initialization request signal is output from the initialization operation means, at least the payout control process starts executing the game control process. It is configured to execute a delay process that delays until it is done.
Thus, it is possible to prevent the control state from being unmatched between the game control microcomputer and the payout control microcomputer in accordance with the operation on the initialization operation means. Further, the payout control microcomputer can reliably receive the payout control signal from the game control microcomputer.

The communication control unit is configured to perform an interrupt process based on the error interrupt request based on a different type of interrupt request from the error interrupt request when a plurality of types of interrupt requests are simultaneously notified by the interrupt request notification unit. When the read value in step S141 by the interrupt processing order control means (for example, the reset / interrupt controllers 102 and 212, the CPU 104 or the CPU 214, etc.) executed in preference to the processing is other than 06h and 07h, the processing in step S142 Etc.), and when the error interrupt request is notified by the interrupt request notification means, execution of processing for controlling serial communication operation by the serial communication circuit is performed as interrupt processing based on the error interrupt request. Error interrupt processing means to stop (eg CP 104 or portions for performing the process of step S41, S42, etc. portion CPU214 is executing the processing in steps S541, S542) and may contain.
As a result, when an error interrupt request is notified by the interrupt request notification means, the serial communication operation by the serial communication circuit can be stopped immediately, and erroneous information is prevented from being transmitted due to the occurrence of an abnormality in serial communication. it can.
Further, the random number circuit setting means sets initial value setting means (for example, the CPU 104 in steps S104 and S126) that sets a value based on a unique identification number assigned to each game control microcomputer to the predetermined initial value. A portion for executing processing).
Thereby, the initial value of the random number that starts updating after the power supply is started can be made different for each gaming machine, and is used for determining whether or not the display result in the variable display is the specific display result. It is possible to increase the randomness of the generated random number and prevent the specific display result from being illegally generated.

  (2) In the gaming machine of the above (1), the game control microcomputer includes a random number circuit (for example, an initial value setting circuit 172A, a random number generator) in which the predetermined update range of numerical data that can be updated by the numerical value updating means is different. A 12-bit random number generation component including a circuit 173A, a selector 174A, an ARSC 175A, a random number sequence change circuit 176A, a maximum value comparison circuit 177A, a random value register 181A, a clock signal output circuit 171, an initial value setting circuit 172A, and a random number generation A circuit 173B, a selector 174B, a BRSC 175B, a random number sequence change circuit 176B, a maximum value comparison circuit 177B, an inversion circuit 178, a timer circuit 179, a latch signal generation circuit 180, a component for 16-bit random number generation including a random number value register 181B) A number of built-in Is used random number circuit setting means for setting a random number circuit to be used from among the plurality of random number circuits (for example, when bits 4 and 3 of KRSS1 and the read value in step S24 by the CPU 104 are other than “00”, A part for executing at least one of a 12-bit random number initial setting process and a 16-bit random number initial setting process in step S25), and a function of a random number circuit other than the random number circuit set by the use random number circuit setting means Random number circuit stopping means (for example, when bits 4 and 3 of KRSS1 and the read value in step S24 by the CPU 104 are other than "11", 12-bit random number initial setting processing and 16 random number initial setting in step S25) A portion that does not execute at least one of the processes).

In such a configuration, the game control microcomputer is configured to include a plurality of random number circuits having different predetermined update ranges of numerical data that can be updated by the numerical value updating means. The random number circuit setting means includes: a random number setting means for setting a random number circuit to be used among a plurality of random number circuits; and a random number circuit stopping means for stopping a function of a random number circuit other than the set random number circuit when used. It is configured to include.
This makes it possible to set the random number circuit corresponding to the random number used according to various determinations, such as determining whether or not the display result of variable display is the specific display result, and reduce the processing load required for the determination. can do.

  (3) In the gaming machine of the above (1) or (2), the random number circuit setting means sets a predetermined maximum value within a numerical data update range by the numerical value updating means (for example, KRMS). , KRXS, the part where the CPU 104 executes the processing of steps S107 and S129, and the like, and whether or not the predetermined maximum value set by the random number maximum value setting means is within the usable range of the random number value Use range determination means (for example, the part where the CPU 104 executes the processes of steps S108 and S130) and the use range determination means determine that the random number value is not within the usable range of the random value. Reset means for resetting a predetermined value within the usable range of numerical values as the predetermined maximum value (for example, the CPU 104 executes step S110, Such portions for performing the process of 132) and may contain.

In such a configuration, the random number circuit setting means includes a random number maximum value setting means for setting a predetermined maximum value within the numerical data update range, and the set predetermined maximum value is within the usable range of the random number value. Use range determining means for determining whether or not there is, and resetting means for resetting a predetermined value within the usable range as a predetermined maximum value when it is determined that the range is not within the usable range It is configured as follows.
Thereby, it is possible to reduce the processing load required for the determination by setting the use range of the random number value in detail, and it is possible to prevent the random number from being updated in an extremely narrow range due to malfunction or fraud.

  (4) In any one of the above gaming machines (1) to (3), the numerical value updating means includes a plurality of update methods (for example, updating at a cycle of the internal system clock or a cycle of 16 times the internal system clock). And the random number circuit setting means updates one of the plurality of update methods for the numerical data. An update method setting means (for example, bit 2 of KRSS1 or a portion in which the CPU 104 executes the processes of steps S121 and S122) that is set as the update method may be included.

In such a configuration, the numerical value updating means is configured to update numerical data by any one of a plurality of update methods. Further, the random number circuit setting means is configured to include an update method setting means for setting any one of a plurality of update methods as a numerical data update method.
As a result, the randomness update method can be made different to improve the randomness of the random numbers.

  (5) In the gaming machine of any one of (1) to (4), the initial value setting means executes a predetermined calculation using a unique identification number assigned to each gaming control microcomputer. The value calculated by this may be set as the predetermined initial value.

In such a configuration, the initial value setting means sets a value calculated by executing a predetermined operation using a unique identification number assigned to each game control microcomputer as a predetermined initial value. It is configured as follows.
This makes it possible to increase the randomness of the random number by making the initial value different for each gaming machine, and to make it difficult to specify the initial value from the identification number, resulting in an illegal specific display result. Can be prevented.

  (6) In the gaming machine according to any one of (1) to (5), the random number circuit setting unit requests change of a permutation that is a renewal order of numerical data updated by the numerical value updating unit. Permutation change setting means for setting numerical permutation change data in the register (for example, when the CPU 104 performs the process of step S106 when the read value in step S105 is “10”, When the read value in step S127 is “10”, the process of step S128 is executed, and then the process of step S239 is executed. When the numerical data is updated from the initial value to the predetermined final value, a notification signal indicating that the numerical data has been updated to the predetermined final value. Notification signal output means (for example, a portion where the random number generation circuit 173A outputs the random number round-trip signal RIJ1 or a portion where the random number generation circuit 173B outputs the random number round-trip signal RIJ2) and the numerical permutation change register Numerical value permutation changing means (for example, random number sequence changing circuits 176A, 176B) that changes the permutation in response to the notification signal being output by the notification signal output means when change data is set. Good. The random number circuit includes permutation change method selection means for selecting one of the first and second permutation change methods, which are methods for changing the permutation, and the numerical permutation change means is the first by the permutation change method selection means. When the permutation changing method is selected, the permutation is changed according to the numerical data being updated from the predetermined initial value to the predetermined final value by the numerical value updating means, while the permutation changing method selecting means When the permutation change method 2 is selected, the numerical data updating means updates the numerical data from a predetermined initial value to a predetermined final value, and the numerical permutation change data is set in the numerical permutation change register The permutation may be changed according to the above. Further, the game control microcomputer may include numerical permutation change data writing means for writing the numerical permutation change data to the numerical permutation change register during execution of the timer interrupt process.

In such a configuration, the random number circuit setting means includes permutation change setting means for setting the numerical permutation change data in the numerical permutation change register that requests the change of the permutation, which is the update order of the numerical data. . When the numerical value data is updated from a predetermined initial value to a predetermined final value by the numerical value updating means, the random number circuit outputs a notification signal indicating that the numerical data has been updated to the predetermined final value. And output means and numerical permutation changing means for changing the permutation in response to the notification signal being output by the notification signal output means when the numerical permutation change data is set in the numerical permutation change register. It is configured.
Thereby, when the numerical data is updated from the predetermined initial value to the predetermined final value, the permutation can be changed variously to increase the randomness of the random numbers.

  (7) In any one of the above gaming machines (1) to (6), when the random number circuit setting means updates the numerical data from the predetermined initial value to the predetermined final value by the numerical value updating means. Includes initial value change setting means for setting whether or not to change the predetermined initial value (for example, bits 1 and 0 of KRSS1, bits 3 and 2 of KRSS2, initial value setting circuits 172A and 172B, etc.) The random number circuit outputs a notification signal indicating that the numerical data is updated to the predetermined final value when the numerical data is updated from the predetermined initial value to the predetermined final value by the numerical value updating means. Signal output means (for example, a portion where the random number generation circuit 173A outputs the random number round-trip signal RIJ1, a portion where the random number generation circuit 173B outputs the random number round-trip signal RIJ2, etc.) and the initial stage When the initial value is set to be changed by the change setting means, the initial value changing means for changing the predetermined initial value in response to the notification signal being output by the notification signal output means (for example, step S74 by the CPU 104). The initial value setting circuits 172A and 172B may include initial value setting signals SK1 and SK2 based on the random number start value change setting process.

In such a configuration, the random number circuit setting means is an initial stage for setting whether or not to change the predetermined initial value when the numerical data is updated from the predetermined initial value to the predetermined final value by the numerical value updating means. A value change setting unit is included. Further, the random number circuit outputs a notification signal indicating that the numerical data is updated to the predetermined final value when the numerical data is updated from the predetermined initial value to the final value by the numerical value updating means. And an initial value changing means for changing a predetermined initial value in response to the output of the notification signal by the notification signal output means when the initial value change setting means is set to change the initial value. It is configured.
Thereby, when the numerical data is updated from the predetermined initial value to the predetermined final value, the initial value can be changed to increase the randomness of the random number.

  (8) In any of the above gaming machines (1) to (7), a start signal output means (for example, a start port switch 22 or the like) that detects that the variable display execution condition is satisfied and outputs a start signal And the random number circuit outputs a latch signal for causing the random number value storage means to store numerical data updated by the numerical value updating means in response to the start signal output means outputting a start signal. Including a signal output means (for example, a latch signal generation circuit 180). The latch signal output means outputs a latch signal on condition that a start signal is continuously input from the start signal output means for a predetermined period. Also good.

In such a configuration, the start signal output means is configured to detect that the variable display execution condition is satisfied and output the start signal. The random number circuit is configured to include a latch signal output means for outputting a latch signal in response to the start signal being output by the start signal output means. The latch signal output means is configured to output a latch signal on condition that the start signal is continuously input from the start signal output means for a predetermined period.
Thereby, it is possible to prevent the latch signal output means from erroneously outputting the latch signal due to the influence of noise or the like.

  (9) In the gaming machine of (8), the random number reading means outputs the start signal until the number of executions of the timer interrupt process reaches a predetermined number (for example, 2 times) (for example, 4 milliseconds). Based on the continuous input of the start signal from the means, the random number value stored in the random value storage means is read (for example, the CPU 104 determines Yes when the timer value is “2” or more in step S421). The latch signal output means may set a time shorter than the time until the timer interrupt process is executed to the predetermined time as the predetermined period. (For example, a part in which the timer circuit 179 sets 3 milliseconds as a time shorter than 4 milliseconds, which is the execution time of two game control timer interruption processes).

In such a configuration, the game control microcomputer obtains the random number value from the random value storage means based on the fact that the start signal is continuously input until the number of executions of the timer interrupt process reaches a predetermined number. Random value reading means for reading is included. Further, the latch signal output is configured to set a time shorter than the time until the number of executions of the timer interrupt process reaches a predetermined time as the predetermined period.
Thereby, it is possible to prevent the random value read this time from becoming the same value as the random value read previously.

  (10) In the gaming machine according to any one of (1) to (9), when the payout number signal receiving unit receives the payout number signal, a reception confirmation signal indicating that the payout number signal has been received ( Including a reception confirmation signal transmission means (for example, a part that executes the payout side transmission process of step S557 after the CPU 214 executes the process of step S634), which transmits a prize ball ACK command or the like to the microcomputer for game control. When the game control microcomputer confirms that the reception confirmation signal is not received after the payout number signal is transmitted by the payout number signal transmission means, the game control microcomputer sends a payout number signal to the payout number signal transmission means. Re-transmission control means for re-transmission (for example, the CPU 104 executes the process of step S336, so that the Y in step S302 and a payout abnormality notification signal (for example, main notification) for notifying that a payout abnormality has occurred when the retransmission control means causes the payout number signal transmitting means to retransmit the payout number signal. A payout abnormality notification signal transmitting means (for example, the CPU 104 determines Yes in step S275) that transmits a side payout abnormality notification start command or the like as the effect control signal to the effect control microcomputer. And the production control microcomputer receives the payout abnormality notification signal transmitted by the payout abnormality notification signal transmission means, and the like. A payout abnormality notifying means (for example, notifying that a payout abnormality has occurred by controlling the electrical parts for the production) The CPU 123 may include a portion that causes the image display device 5 to display a main-side payout abnormality notification screen as shown in FIG. 76D by executing the process of step S954. The game control microcomputer and the payout control microcomputer may perform serial communication in both directions.

In such a configuration, when the game control microcomputer transmits the payout number signal and then confirms that it will not receive the reception confirmation signal, the payout number signal transmission means retransmits the payout number signal. When the control means and the retransmission control means retransmit the payout number signal, the payout abnormality is transmitted to the effect control microcomputer as an effect control signal to notify that a payout abnormality has occurred. And a notification signal transmitting means.
As a result, when it is determined that the payout control microcomputer has not received the payout number signal, it is possible to prevent the disadvantage of the player so as not to hinder the payout control by retransmitting the payout number signal. Thus, communication abnormality related to payout control can be easily recognized outside the gaming machine.

  (11) In the gaming machine according to any one of (1) to (10), when the payout number signal receiving unit receives the payout number signal, a reception confirmation signal indicating that the payout number signal has been received ( Including a reception confirmation signal transmission means (for example, a part that executes the payout side transmission process of step S557 after the CPU 214 executes the process of step S634), which transmits a prize ball ACK command or the like to the microcomputer for game control. The game control microcomputer receives a reception confirmation reception signal (for example, an ACK feedback command) to the payout control microcomputer when receiving the reception confirmation signal transmitted by the reception confirmation signal transmission means. Confirmation signal transmission means (for example, the CPU 104 executes the process of step S331). The payout control microcomputer receives the reception confirmation acceptance signal after the reception confirmation signal is transmitted by the reception confirmation signal transmission means. The reception confirmation acceptance signal determination means (for example, the part where the CPU 214 executes steps S616, S638 and S643) and the reception confirmation acceptance signal determination means receive the reception confirmation acceptance signal. When it is determined that there is no payout (for example, Yes in step S643), the payout control is stopped even if the payout control prohibition state indicates that there is an unpaid out prize game medium. (E.g., in response to the main board communication error flag being set in step S644) The payout control prohibition state control means (for example, the part where the CPU 214 executes the process of step S721) may be included. The game control microcomputer and the payout control microcomputer may perform serial communication in both directions.

In such a configuration, the payout control microcomputer receives the reception confirmation acceptance signal determination means for determining whether or not the reception confirmation acceptance signal from the game control microcomputer has been received, and the reception confirmation acceptance signal determination means. When it is determined that the confirmation acceptance signal has not been received, the payout control prohibition state is controlled so that the payout control is stopped even if the unpaid number data indicates that there is an unpaid premium game medium. And a payout control prohibition state control means.
Accordingly, it is possible to prevent the payout game medium from being paid out excessively when a certain payout control is executed and, for example, an abnormality due to a communication error or an illegal act on the communication line occurs.

  (12) In the gaming machine according to any one of (1) to (11), when the payout number signal receiving unit receives the payout number signal, a reception confirmation signal indicating that the payout number signal has been received ( Including a reception confirmation signal transmission means (for example, a part that executes the payout side transmission process of step S557 after the CPU 214 executes the process of step S634), which transmits a prize ball ACK command or the like to the microcomputer for game control. The game control microcomputer receives a reception confirmation reception signal (for example, an ACK feedback command) to the payout control microcomputer when receiving the reception confirmation signal transmitted by the reception confirmation signal transmission means. Confirmation signal transmission means (for example, the CPU 104 executes the process of step S331). The payout control microcomputer receives the reception confirmation acceptance signal after the reception confirmation signal is transmitted by the reception confirmation signal transmission means. The reception confirmation acceptance signal determination means (for example, the part where the CPU 214 executes steps S616, S638 and S643) and the reception confirmation acceptance signal determination means receive the reception confirmation acceptance signal. When it is determined that the payout number is not present (for example, “Yes” in step S643), the payout number signal receiving unit stops receiving the payout number signal as the payout control prohibited state (eg, the main board in step S644). In response to the communication error flag being set, the processing after step S602 is performed. The payout control prohibition state control means (for example, the part where the CPU 214 executes the process of step S601) may be included. The game control microcomputer and the payout control microcomputer may perform serial communication in both directions.

In such a configuration, the payout control microcomputer receives the reception confirmation acceptance signal determination means for determining whether or not the reception confirmation acceptance signal from the game control microcomputer has been received, and the reception confirmation acceptance signal determination means. When it is determined that the confirmation acceptance signal has not been received, the payout control prohibiting state includes payout control prohibiting state control means for controlling the payout number signal receiving means to stop receiving the payout number signal. It is configured as follows.
Accordingly, it is possible to prevent the payout game medium from being paid out excessively when a certain payout control is executed and, for example, an abnormality due to a communication error or an illegal act on the communication line occurs.

  (13) In the gaming machine according to (11) or (12), the gaming machine includes error cancellation operation means (for example, an error cancellation switch 73) that outputs an error cancellation signal according to an operation, and the payout control microcomputer includes When the error canceling signal is output from the error canceling operation means, the prohibition state canceling means for canceling the payout control prohibiting state by the payout control prohibiting state control means (for example, the CPU 214 executes the payout side error canceling process in step S558). Part, etc.).

In such a configuration, the payout control microcomputer is configured to include prohibition state canceling means for canceling the payout control prohibition state when an error canceling signal is output from the error canceling operation means.
Thereby, for example, after a game store clerk inspects for an abnormality, the game can be continued while maintaining the control state before the inspection.

  (14) In any one of the above gaming machines (1) to (13), the interrupt request notified by the interrupt request notifying unit satisfies an interrupt request condition when a signal is received, and reads the received signal Including a reception interrupt request for causing the communication control means to execute an interrupt process (for example, an interrupt request at the time of receiving data transfer or an interrupt request at the time of detecting an idle line), and the communication control means is notified by the interrupt request notification means Prior to the execution of the interrupt processing based on the interrupt request to be executed, including priority changing means for changing the priority of the interrupt processing (for example, the portion where the CPU 104 or the CPU 214 executes the processing such as steps S141 and S142), The interrupt processing order control means is more preferable than the interrupt processing based on the error interrupt request by the priority changing means. When it is modified to run with priority interrupt processing based on the signal interrupt request may be executed with priority interrupt processing based on the received interrupt request to the interrupt process based on the error interrupt request.

In such a configuration, the interrupt request notified by the interrupt request notification unit includes a reception interrupt request for causing the communication control unit to execute an interrupt process for reading the received signal, and the communication control unit includes the interrupt request notification unit. Including priority changing means for changing the priority of interrupt processing before the execution of the interrupt processing based on the interrupt request notified by is interrupted, and the interrupt processing order control means is more effective than the interrupt processing based on the error interrupt request. When the interrupt process based on the received interrupt request is changed so as to be executed with priority, the interrupt process based on the received interrupt request is executed with priority over the interrupt process based on the error interrupt request.
Thereby, after the execution of the interrupt process is permitted, the interrupt process can be surely executed according to the changed priority order. Further, the degree of freedom in design can be increased by changing the priority order of the interrupt processing so that the interrupt processing based on the reception interrupt request is executed with priority over the interrupt processing based on the error interrupt request.

  (15) In the gaming machine according to any one of (1) to (14), the specific microcomputer executes timer interrupt processing execution means for executing interrupt processing based on a timer interrupt request that is generated every time a predetermined time elapses ( For example, a portion where the CPU 104 executes the processing of steps S71 to S84, a portion where the CPU 214 executes the processing of steps S551 to S558, etc.), the execution of the interrupt processing based on the timer interrupt request, and the interrupt request notification means Prior to the execution of the interrupt processing based on the interrupt request, the priority between the interrupt processing executed by the timer interrupt processing execution means and the interrupt processing based on the interrupt request notified by the interrupt request notification means is determined. Priority order initial setting means for setting (for example, the CPU 104 performs step S 7 for executing the interrupt initial setting process, and the CPU 214 executing the interrupt initial setting process in step S519). The interrupt processing order control means is based on the timer interrupt request by the priority order initial setting means. When the interrupt process based on the interrupt request notified by the interrupt request notifying unit is set to be executed with priority over the interrupt process, the timer interrupt process executing unit executes the interrupt process before the interrupt process is executed. Interrupt processing based on the interrupt request notified by the interrupt request notification means may be executed.

In such a configuration, before the specific microcomputer is permitted to execute the interrupt processing based on the timer interrupt request and the interrupt processing based on the interrupt request notified by the interrupt request notification means, the timer interrupt processing is executed. Priority priority setting means for setting the priority between the interrupt processing executed by the means and the interrupt processing based on the interrupt request notified by the interrupt request notifying means, and the interrupt processing order control means includes an interrupt based on the timer interrupt request. When it is set to execute the interrupt processing based on the interrupt request notified by the interrupt request notification means prior to the processing, the interrupt request notification means before the timer interrupt processing execution means executes the interrupt processing. Configured to execute interrupt processing based on the interrupt request notified by It has been.
Thereby, after the execution of the interrupt process is permitted, the interrupt process can be surely executed according to the set priority order. In addition, the interrupt processing priority can be arbitrarily set so that the interrupt processing based on the interrupt request notified by the interrupt request notifying means is given priority over the interrupt processing based on the timer interrupt request. The degree of freedom can be increased.

  (16) In the gaming machine according to any one of (1) to (15), the gaming control microcomputer determines whether or not the power supply voltage is stable before the determination by the initialization operation determination unit. A power supply confirmation unit for confirming (for example, a portion where the CPU 104 executes the processes of steps S5 and S6) may be included.

In such a configuration, before the determination by the initialization operation determination means is made, it is configured to check whether or not the power supply voltage is stable.
As a result, it can be detected that the initialization request signal is output even though it has not been output, or it can be detected that the initialization request signal has not been output despite being output. It is possible to prevent the game control microcomputer from being erroneously detected.

  (17) In the gaming machine according to any one of (1) to (16), the payout control board transmits the power failure signal output from the power supply monitoring means to the game control microcomputer. Means (for example, as shown in FIG. 6, a portion where a power-off signal is transmitted from the dispensing control board 15 to the main board 11) may be included.

  In such a configuration, the power failure signal from the power monitoring means is transmitted from the power failure signal transmission means provided on the payout control board to the game control microcomputer. It is possible to simplify and reduce the cost of the gaming machine.

It is a front view of the pachinko gaming machine in the present embodiment. It is explanatory drawing which shows the relationship of each switch for detecting a game ball. It is a block diagram which shows the various control boards etc. which were mounted in the pachinko game machine. It is a figure which shows the structural example of a power supply board. It is a timing diagram which shows typically the state of a reset signal and a power-off signal. It is a block diagram which shows the example of installation of a main board | substrate, a payout control board, and a power supply board. It is explanatory drawing which shows an example of the content of a display control command. It is explanatory drawing which shows the structural example of the command transmitted / received between the main board | substrate and the payout control board. It is a disassembled perspective view which shows the structural example of the payout apparatus in which the payout motor is installed. It is a block diagram which shows the structural example of the microcomputer for game control. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example of ARSC and BRSC. It is explanatory drawing which shows the change operation | movement of the permutation by a random number sequence change circuit. It is explanatory drawing which shows the change operation | movement of the permutation by a random number sequence change circuit. It is explanatory drawing which shows the reset operation | movement of the random value by a maximum value comparison circuit. It is a figure which shows the structural example of a random value register or a maximum value read register. It is a figure which shows an example of the address map in the microcomputer for game control. It is a figure which shows an example of the address map in ROM. It is explanatory drawing which shows the example of a setting of the highest priority interrupt. It is explanatory drawing which shows the content of random number initialization data. It is explanatory drawing which shows the content of serial communication initial setting data. It is a block diagram which shows the structural example of the data holding area for game control. It is a figure which shows the structural example of the reception command buffer for a payout. It is a figure which shows the structural example of the transmission command buffer for payment. It is a block diagram which shows the structural example of a serial communication circuit. It is a figure which shows the structural example of a serial status register and a serial control register. It is a block diagram which shows the structural example of the microcomputer for payout control. It is a block diagram which shows the structural example of the data holding area for payout control. It is a flowchart which shows an example of a game control main process. It is a flowchart which shows an example of a game control main process. It is a figure which shows an example of the specific process performed within the game control main process. It is a flowchart which shows an example of a 12-bit random number initial setting process. It is a flowchart which shows an example of a 16-bit random number initial setting process. It is explanatory drawing which shows the content of the process performed as a serial communication initial setting process. It is a flowchart which shows an example of an interruption initial setting process. It is a flowchart which shows an example of the main side power-off process. It is a flowchart which shows an example of a serial communication error interruption process. It is a flowchart which shows an example of a serial reception interruption process. It is a flowchart which shows an example of a serial transmission interruption process. It is a flowchart which shows an example of the timer interruption process for game control. It is a flowchart which shows an example of a random number start value change setting process. It is a flowchart which shows an example of a random number start value change setting process. It is a flowchart which shows an example of a random number permutation change setting process. FIG. 6 is a flowchart illustrating an example of a prize ball process, and an explanatory diagram illustrating an example of a specific process executed in the prize ball process. It is a flowchart which shows an example of a prize ball transmission process. It is a flowchart which shows an example of a prize ball ACK waiting process. It is a flowchart which shows an example of a prize ball transmission completion process. It is a flowchart which shows an example of abnormal operation alert setting processing. It is a flowchart which shows an example of abnormal operation alert setting processing. It is a flowchart which shows an example of the main side reception process. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows an example of the command control process for payout. It is a flowchart which shows an example of the main side error cancellation process. It is a flowchart which shows an example of payout control main processing. It is a flowchart which shows an example of the payment side power-off process. It is a flowchart which shows an example of a serial communication error interruption process. It is a flowchart which shows an example of the timer interruption process for payout control. It is a flowchart which shows an example of a payout side reception process. It is a flowchart which shows an example of a prize ball reception confirmation process. It is a flowchart which shows an example of a payout operation control process. It is a flowchart which shows an example of a payout number memory | storage abnormality determination process. It is a flowchart which shows an example of payout control normal processing. It is a flowchart which shows an example of a prize ball payout operation | movement process. It is a flowchart which shows an example of a prize ball payout number calculation process. It is a flowchart which shows an example of a prize ball payout drive process. It is a flowchart which shows an example of a ball lending / dispensing operation process. It is a flowchart which shows an example of a ball | brick rental payout number calculation process. It is a flowchart which shows an example of a ball rental payout drive process. It is explanatory drawing which shows the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an example of the payment side transmission process. It is a flowchart which shows an example of the payout side error cancellation process. It is a flowchart which shows an example of production control main processing. It is a flowchart which shows an example of production control process processing. It is a flowchart which shows an example of alerting | reporting process. It is a flowchart which shows an example of alerting | reporting process. It is a figure which shows the example of a display operation in an image display apparatus. It is a timing chart for demonstrating operation | movement of a random number circuit. It is a block diagram which shows an example of a structure in the modification of the random number circuit shown in FIG. 79 is a timing chart for explaining the operation of the random number circuit shown in FIG. 78.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a front view of a pachinko gaming machine 1 according to the present embodiment, and shows an arrangement layout of main members. The pachinko gaming machine (gaming machine) 1 is roughly composed of a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. The game board 2 is formed with a substantially circular game area surrounded by guide rails.

  A special symbol display device 4 for variably displaying a special symbol as identifiable identification information is provided above the central position of the game area. Below the special symbol display device 4, there is provided an image display device 5 that can perform variable display of decorative symbols different from the special symbol, image display that is a predetermined effect display, and the like. Below the image display device 5, an ordinary variable winning ball device 6 that forms a start winning opening is arranged. Below the ordinary variable winning ball apparatus 6, a special variable winning ball apparatus 7 that forms a large winning opening and a normal symbol display 40 are provided.

  The special symbol display device 4 includes, for example, 7-segment or dot matrix LEDs. The special symbol display device 4 is, for example, “0” to “9” in a special game as a variable display game that is executed based on a start condition established by winning a game ball in the normal variable winning ball device 6. The special symbol which consists of the number etc. which show and functions as several types of identification information which can identify each is variably displayed. Each special symbol is assigned a symbol number corresponding to each special symbol, for example, the same number as the number indicated by each symbol. The special symbol display device 4 is configured to variably display more types of symbols such as numbers indicating “00” to “99”, for example, in order to make it difficult for the player to grasp a specific stop symbol. It may be.

  In the special symbol game performed by the special symbol display device 4, when a predetermined time elapses after the variation of the special symbol is started, the fixed special symbol that is a variable symbol display result is stopped (derived display). At this time, if a special symbol (big hit symbol) is stopped and displayed as a confirmed special symbol in the special symbol game on the special symbol display device 4, it becomes a “big hit” as a specific display result, and a special symbol other than the big bonus symbol is displayed. If it is stopped, it will be “lost”. When the variation display result in the special figure game is “big hit”, the big hit game state as the specific game state is controlled by opening and closing the opening / closing plate of the special variable winning ball apparatus 7. In the pachinko gaming machine 1 according to this embodiment, as a specific example, a special symbol indicating “7” is a jackpot symbol, and a special symbol indicating other numerical values is a lost symbol.

  In the jackpot gaming state based on the special symbol indicating “7” which is a jackpot symbol as a confirmed special symbol in the special symbol game by the special symbol display device 4, by the opening / closing plate of the special variable winning ball device 7, A game ball that drops on the surface of the game board 2 during a predetermined opening period (for example, 29 seconds) or a period until a predetermined number (for example, 10) of winning balls are generated and the large winning opening is opened. Is received, and it becomes possible to enter the grand prize opening, and then the round is closed by closing the grand prize opening. The round as the open / close cycle can be repeated up to a predetermined upper limit number (for example, 15 rounds).

  The image display device 5 is composed of, for example, an LCD or the like, and may be any device that performs screen display by a dot matrix method using a large number of pixels (pixels). On the display screen of the image display device 5, each can be identified by, for example, a variable display section as a display area divided into three corresponding to the special symbol variation display in the special symbol game by the special symbol display device 4. A variable display that displays various types of decorative designs in a variable manner is performed. As a specific example, variable display portions “left”, “middle”, and “right” are arranged on the image display device 5, and decorative symbols are variably displayed on the variable display portions. When the special symbol variation display on the special symbol display device 4 is started, the decorative symbol variation display (for example, switching) is displayed on each of the “left”, “middle”, and “right” variable display portions in the image display device 5. Display and scroll display) is started, and thereafter, when the confirmed special symbol is stopped and displayed as a special symbol variation display result in the special symbol display device 4, "left", "middle", "right" in the image display device 5 ”Is stopped and displayed on each variable display section, and the combination of decorative designs that are variable display results is stopped and displayed (derived display).

  For example, in each of the “left”, “middle”, and “right” variable display portions, symbols representing ten types of numbers “0” to “9” are displayed as decorative symbols in a variable manner. Each decorative symbol is given a symbol number corresponding to each decorative symbol, for example, the same number as the number indicated by each symbol. Then, in each of the “left”, “middle”, and “right” variable display sections, when the decorative symbol variation display is started, for example, the display from which the number indicated by the symbol is changed to the larger one is switched or scrolled. After the decorative pattern “9” is displayed, the decorative pattern “0” is displayed. Then, when the special symbol determined in the special symbol game on the special symbol display device 4 is a big hit symbol, that is, when a big hit occurs, a fixed combination of “left”, “middle” and “right” is determined by a predetermined combination. The decorative design is stopped and displayed. Specifically, when the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol, the same decorative symbol is displayed on the “left”, “middle”, and “right” variable display portions. Is stopped.

  In this embodiment, the decorative symbols “1”, “3”, “5”, “7” or “9” whose symbol numbers are odd numbers are used as decorative symbols (probable variable symbols) for probability variation big hits. The decorative pattern “0”, “2”, “4”, “6” or “8” in which is an even number is usually used as a decorative pattern for a big hit (normal pattern). When the same probability variation symbol (decorative symbol combination symbol ornament) is stopped and displayed on the variable display portion of “left”, “middle”, and “right” as a variable symbol display result, a probability variation big hit is obtained. When a promising big hit is reached, after the big hit gaming state based on the probable big hit is finished, until a special number of games (for example, 100 times) is executed or until a variable display result in the special figure game becomes a big hit As one of the special game states, a high probability state (probability improvement state) in which probability variation control (probability variation control) is continuously performed is obtained. In this high probability state, the probability that the jackpot symbol is stopped and displayed as a variable display result in the special figure game and is controlled to the jackpot gaming state is improved as compared with the normal gaming state. The normal gaming state is a gaming state other than the big hit gaming state or the special gaming state, and the probability that the big hit symbol is stopped and displayed as a confirmed special symbol in the special figure game, such as immediately after the power is turned on. It is controlled in the same way as the initial setting state.

  When the same normal symbol (decorative symbol of a combination of normal jackpots) is stopped and displayed on the variable display portions “left”, “middle”, and “right” as a variable display result of the decorative symbols, a normal big hit is obtained. Since the probability change control is not performed when the normal big hit, the probability that the variable display result in the special figure game becomes a big hit and is controlled to the big hit gaming state is not improved. On the other hand, when a big hit is made, a high probability state is until a predetermined number of times (for example, 100 times) the execution of a special figure game is started, or until the execution of a special figure game that is a big hit is started. As one of the different special game states, a time reduction state in which time reduction control (time reduction control) is continuously performed may be set. In the time reduction state where the time reduction control is performed, the probability of being a big hit in each special figure game and being controlled to the big hit gaming state is the same as the normal gaming state, but the special symbol variable display is started in the special figure game. The variable display time, which is the time from when the displayed special symbol as the display result is stopped and displayed, is controlled to be shorter than the normal gaming state.

  In each of the “left”, “middle”, and “right” variable display portions, a plurality of types of symbols representing alphabets may be displayed as decorative designs, and a plurality of types of character designs related to a predetermined motif may be displayed. May be variably displayed as a decorative pattern. Further, in the image display device 5, during the execution of the special symbol game by the special symbol display device 4, it is possible to perform effect display in any of various effect modes. The variable display unit may be a fixed area, but may move or change in size in the display area of the image display device 5 while the game is in progress.

  In addition, the image display device 5 has a special symbol start memory display area for displaying the number of effective winning balls, that is, the number of reserved memories (starting winning memory number) entered into the starting winning opening provided in the normal variable winning ball device 6. It may be provided. In the special symbol start memory display area, a winning display is performed in response to an effective start winning when the number of reserved memories is less than a predetermined upper limit (for example, “4”). As a specific example, the display that is normally blue is changed to a red display. In this case, by providing the decorative symbol display area (variable display portion) and the special symbol start memory display area separately, the number of reserved memories can be displayed during variable display of decorative symbols. The special symbol start memory display area may be provided in a part of the decorative symbol display area. In this case, the display of the reserved storage number may be interrupted during the variable display of the decorative design. In addition, a display (special symbol start storage display) for displaying the number of reserved memories may be provided separately from the image display device 5.

  The normal variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces which are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 81 (FIG. 3). (Community). The normal variable winning ball apparatus 6 is configured to wait until a predetermined time elapses when the display result is “winning” in the variable symbol display (ordinary symbol game) on the normal symbol indicator 40. By controlling to the tilting position, it becomes easier for the game ball to win the start winning opening than when the movable wing piece is set to the vertical position. The game ball that has won the normal variable winning ball apparatus 6 is detected by the start port switch 22 (FIGS. 2 and 3). Based on the detection of the game ball by the start port switch 22, a predetermined number (for example, four) of prize balls are paid out.

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a large winning opening by a solenoid 82 (FIG. 3). This opening / closing plate is used for a predetermined period or a period until a predetermined number of winning balls are generated when a big hit gaming state is obtained based on a variation display result in a special symbol game by the special symbol display device 4. As a first state which is advantageous to the user, the large winning a prize opening is opened by the solenoid 82 and then closed. On the other hand, at a normal time, for example, before the big hit gaming state occurs after the power of the pachinko gaming machine 1 is turned on, the prize winning opening is closed by the solenoid 82 as a second state disadvantageous to the player. When the special variable winning ball apparatus 7 opens the big winning opening when the opening / closing plate opens, the gaming ball is detected by the count switch 24 (FIGS. 2 and 3). Based on this, a predetermined number (for example, 15) of prize balls are paid out. Of the game balls introduced to the grand prize opening and led to the back of the game board 2, those that entered one area (V winning area; special area) were detected by the V winning switch 23 (FIG. 3). A game ball that is later detected by the count switch 24 and enters the other area may be detected by the count switch 24 as it is. In this case, a solenoid for switching the route in the special winning opening may be provided on the back of the game board 2. Alternatively, it may be possible to always shift to the next round in a round other than the final round in the big hit gaming state without providing the V winning area.

  The game board 2 is provided with a plurality of winning holes 42A to 42D, and winning of game balls to the winning holes 42A to 42D is detected by winning hole switches 25A to 25D (FIGS. 2 and 3), respectively. . Based on the detection of the game balls by the winning ports 42A to 42D, a predetermined number (for example, 7) of payout balls is paid out. That is, each of the winning openings 42A to 42D constitutes a winning area provided in the game board 2 as an area for accepting a game ball as a game medium and allowing winning. In addition, the start winning opening formed in the normal variable winning ball apparatus 6 and the large winning opening formed in the special variable winning ball apparatus 7 constitute a winning area that accepts a game ball as a game medium and allows winning. .

  FIG. 2 is an explanatory diagram showing the relationship of each switch for detecting a game ball won in a winning area such as a winning opening provided on the game board 2. As shown in FIG. 2, the game balls detected by the start port switch 22, the count switch 24, and the winning port switches 25 </ b> A to 25 </ b> D are, for example, the installation positions of the all winning ball detection switches 29 on the back of the game board 2. Is detected by the all winning ball detection switch 29. Here, the installation position of the all winning ball detection switch 29 may be, for example, a position where the winning ball paths meet or a predetermined position downstream of the position.

  The normal symbol display 40 is composed of, for example, an LED or the like, and in a normal diagram game in which a game ball that has passed through a passing gate 41 provided in the gaming area is detected by the gate switch 21 (FIG. 3). , Lighting, blinking, coloring, etc. are controlled. When display is performed with a predetermined hit pattern in the normal game, the display result in the normal game is “win”. Here, in the above-described high probability state and time reduction state, the variable display time in the normal game by the normal symbol display device 40 is shorter than that in the normal game state, and the display result is the winning symbol in each normal game. May be improved. At this time, the tilting time of the movable wing piece in the normal variable winning ball apparatus 6 may be longer than that in the normal gaming state, and the number of tilts may be increased compared to that in the normal gaming state. As described above, in the high probability state and the time reduction state, the gaming state is advantageous to the player, which is different from the big hit gaming state. Here, in the time shortening state, probability variation control is not performed, and the probability of being in the big hit gaming state is the same as in the normal gaming state, so the high probability state is more advantageous for the player than the time shortening state.

  In addition to the above-described configuration, the game area of the game board 2 is provided with a windmill having a decorative lamp, an outlet, and the like. Two speakers 8L and 8R that emit sound effects are provided on the left and right upper portions outside the game area. A game effect lamp 9 that is lit or blinks is provided on the outer periphery of the game area. In the lower right position outside the game area, an operation knob 30 that is operated by a player or the like to launch a game ball toward the game area is provided. In addition, a prize ball lamp that is turned on when there is a remaining number of prize balls may be provided on the outer left side of the game area. An out-of-ball lamp may be provided on the outer top of the game area, which is turned on when the supply ball is cut.

  Further, FIG. 1 also shows a prepaid card unit (hereinafter referred to as a card unit) 70 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card. The card unit 70 includes a usable indicator lamp that indicates whether or not the card unit 70 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 70, and the card unit 70. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock or the like for opening the card unit 70 is provided.

  The pachinko gaming machine 1 includes various power supply boards 10, a main board 11, an effect control board 12, an audio control board 13, a lamp control board 14, a payout control board 15, and a launch control board 17 as shown in FIG. A control board is mounted. The pachinko gaming machine 1 is also equipped with a relay board 18 for relaying various control signals transmitted between the main board 11 and the effect control board 12. Note that the audio control board 13 and the lamp control board 14 may be configured as independent boards that are separate from the effect control board 12, or may be integrated into the effect control board 12 and configured as one board. In addition, various control boards such as an information terminal board are disposed on the back surface of the pachinko gaming machine 1.

  The power supply board 10 is installed independently of each control board such as the main board 11, the effect control board 12, and the payout control board 15, and generates a voltage used by each control board and mechanism component in the pachinko gaming machine 1. For example, in the power supply board 10, as shown in FIG. 4, AC24V, VLP (DC + 24V), VSL (DC + 30V), VDD (DC + 12V), VCC (DC + 5V), and VBB (DC + 5V) are generated. For example, as illustrated in FIG. 4, the power supply substrate 10 includes a transformer circuit 301, a DC voltage generation circuit 302, a power supply monitoring circuit 303, and a clear switch 304. Further, the power supply substrate 10 may be provided with a capacitor serving as a backup power supply. For example, this capacitor may be charged from a power supply line of VBB (DC + 5V). In addition, the power supply board 10 may be provided with a power switch for executing or cutting off the power supply to each control board and the mechanical components in the pachinko gaming machine 1. Alternatively, the power switch may be provided outside the power supply board 10 in the pachinko gaming machine 1.

  For example, the transformer circuit 301 may be configured to include a transformer to which commercial power is applied to the input side (primary side), a varistor as an overvoltage protection circuit provided on the input side of the transformer, and the like. Here, the transformer included in the transformer circuit 301 only needs to be for electrically insulating the commercial power supply from the inside of the power supply substrate 10. The transformer circuit 301 generates 24V AC as its output voltage. The DC voltage generation circuit 302 includes a rectifying / smoothing circuit that generates VSL by, for example, rectifying and boosting AC 24V with a rectifying element. VSL is used as a power supply voltage for driving the solenoid. The DC voltage generation circuit 302 includes a rectifier circuit that generates VLP by rectifying AC 24V with a rectifier, for example. VLP is used as a power supply voltage for lighting the lamp. In addition, the DC voltage generation circuit 302 includes a DC-DC converter that generates VDD and VCC based on, for example, VSL. This DC-DC converter includes, for example, one or more switching regulators and a relatively large capacitor connected to the input side of the switching regulator, and power supply to the pachinko gaming machine 1 from the outside is stopped. Sometimes, it may be configured so that the direct current voltage such as VSL, VDD, VBB, etc. decreases relatively slowly. The VDD is supplied to various switches for detecting game media such as the gate switch 21, the start port switch 22, the V winning switch 23, the count switch 24, the winning port switches 25A to 25D, and the all winning ball detection switch 29. Used to activate the switch.

  As shown in FIG. 4, AC24V output from the transformer circuit 301 is transmitted to the payout control board 15 via a predetermined connector or a power supply line, for example. The VLP is transmitted to the lamp control board 14 via, for example, a predetermined connector or a power supply line. VSL, VDD, and VCC are transmitted to the main board 11, the lamp control board 14, and the payout control board 15 through, for example, predetermined connectors and power supply lines. The VBB is transmitted to the main board 11 and the payout control board 15 through, for example, a predetermined connector and a power supply line. Note that each voltage may be supplied to the effect control board 12 and the audio control board 13 via the lamp control board 14.

  The power monitoring circuit 303 is configured by using, for example, a power failure monitoring reset module IC, and is a circuit that realizes a power monitoring unit that outputs a power interruption signal. For example, the power supply monitoring circuit 303 has a predetermined period of time (56 milliseconds as an example) during which the predetermined voltage (VLP as an example) used in the pachinko gaming machine 1 is equal to or lower than a predetermined value (+20 V as an example). When the above is continued, a power-off signal is output. Alternatively, the power monitoring circuit 303 may output a power-off signal immediately when a predetermined voltage used in the pachinko gaming machine 1 becomes a predetermined value or less. The power-off signal may be an electrical signal that is turned on when it is at a low level, for example. The power-off signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10 and then transmitted to the payout control board 15 via a predetermined connector or signal line. The condition for detecting the stop of the supply of power supplied to the pachinko gaming machine 1 from the outside is not limited to the fact that the predetermined voltage used in the pachinko gaming machine 1 has become a predetermined value or less. Any condition can be used as long as it is possible to detect that has stopped. For example, the AC wave itself such as AC 24V may be monitored to detect that the AC wave has stopped, or a signal obtained by digitizing the AC wave may be monitored and the AC signal may be generated when the digital signal becomes flat. It may be a detection condition for the interruption.

  The power supply monitoring circuit 303 may output a reset signal when, for example, a predetermined voltage (VCC as an example) becomes equal to or lower than a predetermined value (as an example, + 5V or more). The reset signal may be an electric signal that is turned on when the reset signal becomes low level, for example. The reset signal output from the power supply monitoring circuit 303 is amplified by, for example, an output driver circuit mounted on the power supply board 10 and then, via a predetermined connector or signal line, the main board 11, the lamp control board 14, and the payout control board. 15 is transmitted. It should be noted that a reset signal may be transmitted to the effect control board 12 via the lamp control board 14. Furthermore, the circuit that outputs the reset signal may be configured by using a watchdog timer built-in IC provided separately from the power supply monitoring circuit 303, a system reset IC, or the like.

  When the power supply to the pachinko gaming machine 1 is stopped, the power monitoring circuit 303 outputs a reset signal (sets to a low level) when a predetermined period elapses after the power-off circuit 303 outputs a power-off signal (sets to a low level). ) During the predetermined period, for example, the game control microcomputer 100 mounted on the main board 11 and the payout control microcomputer 150 mounted on the payout control board 15 perform power-off processing (described in FIG. 36). It suffices if the time is sufficient to execute the main-side power-off process and the payout-side power-off process shown in FIG. That is, the power monitoring circuit 303 outputs a power-off signal as a power failure signal, and after the game control microcomputer 100 and the payout control microcomputer 150 complete execution of predetermined power-off processing, The reset signal is output (set to low level). The game control microcomputer 100 and the payout control microcomputer 150 that have received the reset signal output from the power supply monitoring circuit 303 are in an operation stop state, and execution of various control processes is stopped. In addition, when the power supply to the pachinko gaming machine 1 is started, for example, when a predetermined voltage (VCC as an example) exceeds a predetermined value (+5 V as an example), the power monitoring circuit 303 stops outputting the reset signal (high Level).

  FIG. 5 is a timing diagram schematically showing the states of AC 24 V, VLP, VCC, reset signal, and power-off signal when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. is there. As shown in FIG. 5, when the power supply to the pachinko gaming machine 1 is started, VLP and VCC gradually reach specified values (DC + 24V and DC + 5V). At this time, when VLP exceeds the first predetermined value, the power supply monitoring circuit 303 stops outputting the power-off signal (sets it to a high level) and turns it off. When VCC exceeds the second predetermined value, the power supply monitoring circuit 303 stops outputting the reset signal (sets it to a high level) and turns it off. On the other hand, when the power supply to the pachinko gaming machine 1 is stopped, VLP and VCC gradually decrease. At this time, when the VLP drops to the first predetermined value, the power supply monitoring circuit 303 outputs the power-off signal as an ON state (sets it to a low level). When VCC decreases to the second predetermined value, the power supply monitoring circuit 303 outputs the reset signal as an ON state (sets it to a low level).

  The clear switch 304 included in the power supply substrate 10 illustrated in FIG. 4 has, for example, a push button structure, and outputs a clear signal in response to an operation such as pressing. The clear signal may be an electric signal that is turned on when the clear signal is at a low level, for example. The clear signal output from the clear switch 304 is transmitted to the main board 11 via, for example, a predetermined connector or signal line. When the clear switch 304 is not operated, the output of the clear signal is stopped (set to a high level). Note that the clear switch 304 may have a configuration other than a push button structure (for example, a slide switch structure, a toggle switch structure, a dial switch structure, or the like).

  In this embodiment, as shown in FIG. 6, the power supply board 10 and the payout control board 15 are installed in the gaming machine frame 3, and the main board 11 is installed in the gaming board 2. Then, a power cut signal is transmitted from the power supply board 10 to the payout control board 15, and the power cut signal is input to the main board 11 via the payout control board 15. In addition, a clear signal is transmitted from the power supply board 10 to the main board 11, and the clear signal is input to the dispensing control board 15 via the main board 11.

  The main board 11 shown in FIG. 3 is a main-side control board, and various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 is a sub-side mainly composed of a random number setting function used in a special game, a function of inputting a signal from a switch arranged at a predetermined position, an effect control board 12, a payout control board 15, and the like. A control board is provided with a function of outputting and transmitting a control command as an example of command information as a control signal to each control board, and a function of outputting various information to a hall management computer. The main board 11 controls the special symbol display on the special symbol display device 4 by controlling the lighting / extinguishing of each segment constituting the special symbol display device 4 while the normal symbol display 40 is turned on. By controlling / flashing / coloring control, the normal symbol display on the normal symbol display 40 is controlled.

  As shown in FIG. 3, the main board 11 receives detection signals from the gate switch 21, start port switch 22, V winning switch 23, count switch 24, winning port switches 25 </ b> A to 25 </ b> D, and all winning ball detection switches 29. Wiring to connect is connected. Note that the gate switch 21, the start port switch 22, the V winning switch 23, the count switch 24, the winning port switches 25A to 25D, and the all winning ball detection switch 29 are used as game media such as a sensor. What is necessary is just to have the arbitrary structures which can detect this game ball. Here, each of the start port switch 22, the count switch 24, and the winning port switches 25A to 25D is provided corresponding to each of a plurality of winning regions provided in the gaming region, and the game ball to each winning region is provided. It becomes a winning opening switch that detects a winning and outputs a winning detection signal. Further, even if a game ball that has passed through the passing gate 41 such as the gate switch 21 is detected, if the payout of the winning ball is performed, the winning of the gaming ball to the winning area is detected and won. It will be included in the winning opening switch that outputs the detection signal. Further, the start port switch 22 detects that the game ball has won the start winning port, and outputs a start winning signal indicating that a start condition for executing the special game by the special symbol display device 4 is satisfied. It becomes a start winning detection switch.

  In addition, on the main board 11, wiring for transmitting a command signal for performing tilt control of the movable blade piece in the normal variable winning ball apparatus 6 to the solenoid 81, and opening / closing of the opening / closing plate in the special variable winning ball apparatus 7 A wiring for transmitting a command signal for performing control to the solenoid 82 is connected. Further, the main board 11 is connected to wiring for transmitting a command signal for performing display control of the special symbol display device 4 and the normal symbol display 40. In addition, wiring for receiving a detection signal from the error release switch 31 is connected to the main board 11. Here, the error release switch 31 is a switch for releasing the error state by software reset when the game control microcomputer 100 is controlled to a predetermined error state.

  A control signal output from the main board 11 toward the effect control board 12 is relayed by the relay board 18. Here, the main board 11 is provided with a main board side connector corresponding to the relay board 18, for example, and an output buffer circuit is connected between the main board side connector and the game control microcomputer 100. May be. This output buffer circuit can pass a control signal only in the direction from the main board 11 to the effect control board 12 via the relay board 18, for example, and prevents the signal input from the relay board 18 to the main board 11. . Therefore, there is no room for signals to be transmitted from the production control board 12 or the relay board 18 side to the main board 11 side.

  The relay board 18 only needs to be provided with a transmission direction regulating circuit for each wiring for transmitting a control signal output from the main board 11 to the effect control board 12, for example. Each transmission direction regulating circuit has an anode connected to a main board connector provided corresponding to the main board 11 and a cathode connected to an effect control board connector provided corresponding to the effect control board 12. The diode is composed of a resistor having one end connected to the cathode of the diode and the other end connected to the ground (GND). With this configuration, each transmission direction regulating circuit can prevent the signal input from the effect control board 12 to the relay board 18 and allow the signal to pass only in the direction from the main board 11 to the effect control board 12. Therefore, there is no room for signals to be transmitted from the production control board 12 side to the main board 11 side. In order to prevent illegal signal input to the main board, a one-way data transfer means for restricting signal input from the sub board to the main board between the main board and the sub board has already been proposed. (For example, see JP-A-8-224339). However, since there is nothing that restricts signal input to the main board between the main board and the one-way data transfer means, it is possible to input illegal signals to the main board by modifying the one-way data transfer means. Was possible. In this embodiment, a transmission direction regulating circuit is provided for each wiring for transmitting a control signal in the relay board 18, and an output buffer circuit is provided between the game control microcomputer 100 and the main board side connector on the main board 11. By providing, illegal signal input from the outside to the main board 11 can be more reliably prevented.

  The effect control board 12 is a sub-side control board independent of the main board 11, receives a control command transmitted from the main board 11 via the relay board 18, and receives the image display device 5, the speakers 8L, 8R. In addition, various circuits for controlling electric parts for production such as the game effect lamp 9 are mounted. That is, the effect control board 12 has a function of controlling the display operation in the image display device 5, the sound output operation from the speakers 8 </ b> L and 8 </ b> R, the lamp lighting operation and the extinguishing operation in the game effect lamp 9. The effect control board 12 is connected to wiring for transmitting a control signal to the sound control board 13 and the lamp control board 14, wiring for transmitting an image data signal to the image display device 5, and the like.

  Various control commands and notification signals are transmitted between the main board 11 and the payout control board 15 by, for example, bidirectional serial communication. The payout control board 15 is a sub-side control board independent of the main board 11, receives a control command and a notification signal transmitted from the main board 11, and controls the payout operation of the game ball by the payout motor 51. Various circuits are installed. That is, the payout control board 15 has a function of controlling the award ball payout operation by the payout motor 51. The payout control board 15 has a function of controlling the ball lending operation by controlling the driving of the payout motor 51 in accordance with the communication result with the card unit 70. The payout control board 15 receives wiring for receiving detection signals from the full tank switch 26 and the ball break switch 27, and detection signals from the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. Wiring for is connected. In addition, a wiring for transmitting a command signal for performing payout control of the game ball in the payout motor 51 and a command signal for performing display control in the error display LED 74 are transmitted to the payout control board 15. Wiring, wiring for communication with the card unit 70, and the like are connected. The payout control board 15 may be connected to a wiring for branching a connection signal from the card unit 70 and transmitting it to the firing control board 17.

  Here, the full tank switch 26 is installed on the side wall of the surplus ball passage that communicates between the striking ball supply tray and the surplus ball receiving tray, for example, below the back of the game board 2, and detects the full tank of the surplus ball receiving tray. Is. When a lot of game balls based on award balls or ball lending requests are paid out and the batting supply tray is full and the game balls reach the contact point, when game balls are further paid out, the game balls pass through the surplus ball passage. It is led to the extra ball tray. When the game ball is further paid out, for example, a predetermined sensing lever presses the full switch 26 to turn on.

  In addition, the ball break switch 27 is installed downstream of the guide rail that guides the game ball to the payout device in which the payout motor 51 is installed, for example, on the back of the game board 2, and via a curve rod downstream of the guide rail. This is for detecting the presence or absence of game balls in two rows of ball passages communicated with each other. As an example, the ball break switch 27 is locked by a locking piece at a position where it can be detected that 27 to 28 game balls are present in the ball path, and the maximum payout number (for example, 100) It is possible to confirm that at least 25 pieces corresponding to a circle are secured. The guide rail guides a game ball from a storage tank that stores a game ball as a supply ball above the back of the game board 2 to a payout device, and a payout motor 51 is provided below the ball passage. The payout device in which is installed is fixed.

  The error release switch 73 is a switch for releasing the error state by software reset when the payout control microcomputer 150 is controlled to a predetermined error state. The error display LED 74 is composed of, for example, a 7-segment LED, and is used to display error codes corresponding to various errors based on an error flag set by the payout control microcomputer 150.

  The launch control board 17 shown in FIG. 3 is for controlling the launch operation of the game ball by a predetermined launch device in accordance with the operation amount of the operation knob 30. For example, a wiring for transmitting a driving signal from the power supply board 10 or the main board 11, a wiring for transmitting a connection signal from the card unit 70, and a wiring from the operation knob 30 are connected to the launch control board 17. A wiring to the firing motor 61 is connected. The connection signal from the card unit 70 may be branched by the payout control board 15 and transmitted to the launch control board 17 or may be transmitted from the card unit 70 to the launch control board 17 without going through the payout control board 15. It may be transmitted. The firing control board 17 adjusts the driving force of the firing motor 61 in accordance with the operation amount of the operation knob 30. For example, the launch motor 61 elastically deforms the launch spring by a driving force adjusted by the launch control board 17, and transmits the biasing force of the launch spring to the hitting hammer to hit the game ball, thereby operating the game ball on the operation knob 30. It is fired toward the game area at a speed corresponding to the operation amount.

  The control command transmitted from the main board 11 to the effect control board 12 via the relay board 18 is, for example, an effect control command transmitted as an electric signal. The effect control command includes, for example, a display control command used for controlling an image display operation in the image display device 5, a voice control command used for controlling sound output from the speakers 8L and 8R, and a game effect lamp 9. And a lamp control command used for controlling the lighting operation of the decoration LED and the like. FIG. 7 is an explanatory diagram showing an example of the contents of the display control command used in this embodiment. The display control command has, for example, a 2-byte configuration. The first byte indicates MODE (command classification), and the second byte indicates EXT (command type). The first bit of the MODE data (seventh bit [bit 7]) is always “1”, and the first bit of the EXT data is “0”. Note that the form of the display control command shown in FIG. 7 is an example, and other command forms may be used. In this example, the display control command has a 2-byte configuration, but the number of bytes constituting the display control command may be 1 or a plurality of 3 or more. In this embodiment, as a display control command, variable display start command, display result notification command, jackpot start command, jackpot end command, initialization notification command, recovery notification command, main side payout abnormality start command, main side payout error A notification end command, a prize ball excess notification command, a prize ball shortage notification command, a payout side abnormality notification start command, a payout side abnormality notification end command, a serial communication abnormality notification start command, a serial communication abnormality notification end command, etc. are prepared in advance. Yes.

  In the example shown in FIG. 7, the command 80XXh is a variable display start command that is transmitted when the special symbol display device 4 starts the variable symbol special symbol display in the special symbol game. XXh indicates an unspecified hexadecimal number, and may be a value that is arbitrarily set according to the instruction content by the display control command. The variable display start command is, for example, a special symbol variable display time (total variation time), which is a time from when the special symbol display device 4 starts the variable symbol variable display to when the fixed special symbol is stopped and displayed, or a decorative symbol. EXT data indicating whether or not the variable display mode is a reach loss that is lost after reaching, or a normal loss that is lost without reaching, is included.

  Here, the reach means that a decorative display (referred to as a reach variation pattern) that has not yet been derived and displayed when the decorative pattern derived and displayed on the image display device 5 forms a part of the jackpot combination is a variable display. It is a display mode that is being performed, or a display mode in which all or some of the decorative symbols are synchronously displayed while constituting all or part of the jackpot symbol. Specifically, on the combination effective line that has not been stopped yet when the symbols constituting the predetermined jackpot combination are stopped and displayed on some of the variable display portions on the predetermined combination effective line. Display mode in which variable display is performed in the variable display section (for example, "left", "right" variable display sections among "left", "middle", "right" variable display sections provided in the display area Is a display mode in which part of the big hit symbol (for example, “7”) is stopped and displayed, and the “middle” variable display section is still displaying a variable display) or variable on the effective line A display mode (for example, “left”, “middle”, “ The state of change is displayed on all the `` Right '' variable display sections. Is but display mode in variable display is being performed aspects be displayed have all the same decorative pattern). Also, during the reach, unusual effects may be performed with lamps or sounds. This production is called reach production. Further, during the reach, the image display device 5 displays a character (an effect display imitating a person or the like, which is different from the decorative design), changes the display mode of the background, or changes the decorative design. The display mode may be changed. This change in character display, background display mode, and decorative pattern variation mode is referred to as reach effect display.

  The command 90XXh is a display result notification command indicating a confirmed special symbol in the special symbol game on the special symbol display device 4, whether or not the game state becomes a probable big hit that becomes a high probability state, and the like. As a specific example, the command 9000h is a command indicating that the confirmed special symbol in the special game is a lost symbol. The command 9001h is a command indicating that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol and that the gaming state is a normal jackpot that does not become a high probability state. . Further, the command 9002h is a command indicating that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as a jackpot symbol and that the game state is a probable big hit that makes the gaming state a high probability state. Based on such a display result notification command, on the side of the effect control board 12, the type of display result of the decorative pattern that is stopped and displayed after the variable display of the decorative pattern is performed is lost or is usually a big hit, It becomes possible to decide what to do.

  The command A000h is a big hit start command indicating that the big hit gaming state is started by the big hit in the special figure game by the special symbol display device 4 or the variable display of the decorative symbols in the image display device 5. The command A100h is a jackpot end command indicating that the jackpot gaming state is ended.

  The command D000h is an initialization notification command for notifying that a predetermined initialization process has been executed by the gaming control microcomputer 100 when power supply to the pachinko gaming machine 1 is started. The command D001h indicates that when power supply to the pachinko gaming machine 1 is started, a predetermined restoration process based on data stored in the RAM 106 (FIG. 10) built in the gaming control microcomputer 100 is executed. This is a recovery notification command.

  The command D002h is a main-side payout abnormality notification start command for starting notification that an abnormality relating to the payout of the prize ball has been detected on the main board 11 side. The command D003h is a main-side payout abnormality notification end command for ending the notification started based on the main-side payout abnormality notification start command. The command D004h is a prize ball excess notification command for notifying that an excess of prize balls, which is an excessive payout of prize balls, has occurred. The command D005h is a prize ball shortage notification command for notifying that a shortage of prize balls, which is an excessive payout of prize balls, has occurred.

  The command D006h is a payout side abnormality notification start command for starting notification that an abnormality related to the payout of the prize ball has occurred on the payout control board 15 side. The command D007h is a payout side abnormality notification end command for ending the notification started based on the payout side abnormality notification start command. The command D008h is a serial communication abnormality notification start command for starting notification that an operation abnormality has occurred in the serial communication performed between the main board 11 and the payout control board 15. The command D009h is a serial communication abnormality notification end command for ending notification started based on the serial communication abnormality notification start command.

  The control command transmitted from the main board 11 to the payout control board 15 is, for example, a payout control command transmitted as an electrical signal. Also, for example, a payout notification command as an electrical signal is transmitted from the payout control board 15 to the main board 11. In the following description, not only a command for a predetermined operation from one of the main board 11 and the payout control board 15 to the other, but also a notification signal for notifying the other of the operating state of the other is a payout control command or a payout notice. It shall be included in the command.

  FIG. 8 is an explanatory diagram showing a configuration example of commands transmitted / received between the main board 11 and the payout control board 15. As shown in FIG. 8A, the payout control command transmitted from the main board 11 to the payout control board 15 and the payout notification command transmitted from the payout control board 15 to the main board 11 are both. It has a 2-byte configuration, and is configured to be the second byte by inverting the first byte. Then, the first bit (7th bit [bit 7]) of each byte is used as a header, and the header is made different so that the first byte and the second byte can be distinguished. For example, the header in the first byte is set to a fixed value of “0”, while the header in the second byte is set to a fixed value of “1”.

  The payout control command transmitted from the main board 11 to the payout control board 15 includes a payout initialization command, a payout number designation command, and an ACK feedback command. The payout initialization command is a command indicating that a predetermined initialization process has been executed by the gaming control microcomputer 100 when power supply to the pachinko gaming machine 1 is started. For example, FIG. ) As shown in the figure (CF30h in hexadecimal notation). The payout number designation command is a command indicating the number of prize balls to be paid out, and is composed of, for example, a bit value as shown in FIG. Here, the 3rd to 0th bits [bits 3-0] of the first byte and the second byte in the payout number designation command may be values set according to the number of prize balls to be paid out. FIG. 8D shows a payout number designation command used in this embodiment in hexadecimal notation. A command E11Eh shown in FIG. 8D is a first payout number designation command indicating that the number of prize balls to be paid out is fifteen. The command E916h is a second payout number designation command indicating that the number of prize balls to be paid out is seven. The command EC13h is a third payout number designation command indicating that the number of prize balls to be paid out is four. In this embodiment, four game balls are paid out when a game ball is detected by the start port switch 22, and seven game balls are paid out when a game ball is detected by any of the game port switches 25A to 25D. When a game ball is detected by the count switch 24, 15 prize balls are paid out.

  A payout motor 51 that performs a rotation operation for paying out a game ball in accordance with the payout control of the payout control board 15 is provided inside a payout case constituted by, for example, three cases 91, 92, and 93 as shown in FIG. It is included in the provided dispensing device. The upper portions of the cases 91 and 92 are provided with holes 85 and 86 communicating with the ball passages, respectively, and the game balls flow into the payout device through the holes 85 and 86. Further, a gear 87 is fitted to the rotation shaft of the dispensing motor 51, and a gear 88 that meshes with the gear 87 and a ball mounting portion that is fitted to the central axis of the gear 88 are provided inside the dispensing case. A cam 89 and a ball passage 90 below the cam 89 are provided. For example, the game balls that have flowed in from the holes 85 and 86 fall one by one alternately through the ball passages 90 every time the ball mounting portion of the cam 89 rotates 1/3. Furthermore, a payout motor position sensor 71 composed of, for example, a light emitting element (LED) and a light receiving element is provided inside the payout case. The payout motor position sensor 71 is a sensor for detecting the rotational position of the payout motor 51, and is used for detecting clogging of game balls, so-called ball biting. At the lower part of the ball passage 90 provided inside the payout case, for example, a payout count switch 72 by a proximity switch is arranged. The payout count switch 72 is turned on every time one game ball falls from the ball passage 90, and transmits a predetermined detection signal to the payout control board 15.

  The command F00Fh shown in FIG. 8D is an ACK feedback command serving as a reception confirmation acceptance signal indicating that the prize ACK command transmitted from the payout control board 15 to the main board 11 is received on the main board 11 side. It is.

  FIG. 8F is an explanatory diagram illustrating a configuration example of a payout notification command transmitted from the payout control board 15 to the main board 11. The payout notification command includes a prize ball ACK command, a payout error notification command, and a payout error cancel command. A command A0F5h shown in FIG. 8F is a prize ball ACK that becomes a reception confirmation signal indicating that the payout number specifying command transmitted from the main board 11 to the payout control board 15 is received on the payout control board 15 side. It is a command. The command B0F4h is a payout error notification command for notifying the main board 11 that an abnormality relating to the payout of game balls has occurred on the payout control board 15 side. The command B1E4h is a payout error cancel command for notifying the main substrate 11 side that the error generated on the payout control board 15 side has been cancelled.

  As shown in FIG. 3, a game control microcomputer 100, a switch circuit 111, and a solenoid circuit 112 are mounted on the main board 11. The switch circuit 111 includes detection signals from various switches such as the gate switch 21, the start port switch 22, the V winning switch 23, the count switch 24, the winning port switches 25 </ b> A to 25 </ b> D, the all winning ball detection switch 29, and the error release switch 31. Is entered. The switch circuit 111 takes in these detection signals and transmits them to the game control microcomputer 100. The solenoid circuit 112 outputs drive signals for the solenoids 81 and 82 in accordance with a command from the game control microcomputer 100.

  FIG. 10 is a diagram illustrating a configuration example of the game control microcomputer 100 mounted on the main board 11. A game control microcomputer 100 shown in FIG. 10 is, for example, a one-chip microcomputer, and includes a clock circuit 101, a reset / interrupt controller 102, a random number circuit 103, a CPU (Central Processing Unit) 104, and a ROM (Read Only). A memory (RAM) 105, a RAM (Random Access Memory) 106, a timer circuit (PIT) 107, a serial communication circuit (SCI) 108, and an external bus interface 109 are provided.

  The clock circuit 101 is a circuit that generates a clock signal to be supplied to each circuit in the game control microcomputer 100 such as a CPU 104. As a specific example, the clock circuit 101 divides an external clock input to a predetermined clock input terminal by 4 to generate an internal system clock CLK, and the generated internal system clock CLK is used for a game control micro, such as the CPU 104. This is supplied to each circuit in the computer 100.

  The reset / interrupt controller 102 is for controlling various reset and interrupt requests generated in the game control microcomputer 100. The reset controlled by the reset / interrupt controller 102 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to a predetermined SRST terminal for a certain period. A user reset has occurred when a low-level signal is input to a predetermined URST terminal for a certain period of time, a watchdog timer (WDT) time-out signal is generated, or an out-of-designated-area travel prohibition (IAT) signal is generated. Or a reset caused by a predetermined factor such as the occurrence of an interval reset signal.

  The interrupt controlled by the reset / interrupt controller 102 includes four types of interrupts such as an X class interrupt (XIRQ), an I class interrupt (IRQ), a software interrupt (SWI), and an illegal opcode trap (ILGOP). . The X class interrupt is an interrupt that occurs when a low level signal is input to a predetermined XIRQ terminal for a certain period. The I class interrupt is an interrupt that can allow / prohibit acceptance of an interrupt request by a user program. When a low level signal is input to a predetermined IRQ terminal for a certain period of time, an interrupt request signal from the timer circuit 107 is received. This is an interrupt generated by various predetermined interrupt factors such as the occurrence of an interrupt request signal from the serial communication circuit 108.

  The random number circuit 103 is a circuit that generates a plurality of types of random numbers having different update ranges, such as a 12-bit random number and a 16-bit random number. FIG. 11 is a block diagram illustrating a configuration example of the random number circuit 103. As shown in FIG. 11, the random number circuit 103 includes a clock signal output circuit 171 having all or part of the function as the clock signal output means, and an initial value setting having all or part of the function as the initial value setting means. Circuits 172A and 172B, random number generation circuits 173A and 173B having a function as numerical value updating means, selectors 174A and 174B having a function as permutation change method selection means, and ARSC 175A and BRSC175B having a function as a numerical permutation change register And random number sequence changing circuits 176A and 176B having a function as numerical permutation changing means, maximum value comparison circuits 177A and 177B, an inverting circuit 178 having a function as clock signal inverting means, and a function as a timer means. Timer circuit 179 and latch signal output means A latch signal generation circuit 180 with a capability, random number register 181A with the function of the random number storage means, and a 181B. Note that the initial value setting circuit 172A, the random number generation circuit 173A, the selector 174A, the ARSC 175A, the random number sequence change circuit 176A, the maximum value comparison circuit 177A, and the random value register 181A are the first random numbers used to generate a 12-bit random number. Configure the circuit. The clock signal output circuit 171, the initial value setting circuit 172B, the random number generation circuit 173B, the selector 174B, BRSC 175B, the random number sequence change circuit 176B, the maximum value comparison circuit 177B, the inversion circuit 178, the timer circuit 179, the latch signal generation circuit 180, The random value register 181B constitutes a second random number circuit used for generating a 16-bit random number.

  The clock signal output circuit 171 receives the internal system clock CLK supplied from the clock circuit 101 and outputs a clock signal having the same cycle as the internal system clock CLK or a clock signal obtained by dividing the internal system clock CLK by 16. Then, the random number generation circuit 173B and the inverting circuit 178 are input. The initial value setting circuits 172A and 172B are for setting the start value of the generated random number sequence. For example, the initial value setting circuits 172A and 172B are configured to set initial values for the first round when the random number circuit 103 starts generating random values after power supply to the pachinko gaming machine 1 is started, When the numerical data is updated cyclically from a predetermined initial value to a predetermined final value by 173A and 173B, a new initial value is set. The initial value setting circuit 172A outputs an initial value setting signal SK1 indicating the set initial value, and inputs it to the random number generation circuit 173A. The initial value setting circuit 172B outputs an initial value setting signal SK2 indicating the set initial value, and inputs it to the random number generation circuit 173B.

  The random number generation circuits 173A and 173B are composed of, for example, a counter having a predetermined number of bits, and based on an input such as a clock signal output from the clock signal output circuit 171, a predetermined initial value within a predetermined range in which numerical data can be updated. Is a circuit that cyclically updates from a predetermined value to a predetermined final value. For example, the random number generation circuit 173A counts up one by one from the initial value set in the range from “1” to “4095” in response to the rising edge in the input signal to the predetermined clock input terminal. Go. Then, after counting up to “4095”, the numerical data is cyclically updated by counting up from “1” to a numerical value that is one final value smaller than the initial value by one. In this embodiment, the clock input terminal of the random number generation circuit 173A is a signal (for example, stored) that combines the stored value update signal KT from the random value register 181A and the reset signal MS1 from the maximum value comparison circuit 177A. A sum signal as an output signal from an OR circuit having the value update signal KT and the reset signal MS1 as input signals. In addition, for example, the random number generation circuit 173B responds to a rising edge in an input signal to a predetermined clock input terminal, one by one from an initial value set within a range from “1” to “65535” to “65535”. Count up numerical data. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “1” to a numerical value that is one final value smaller than the initial value. In this embodiment, a signal (for example, a clock) obtained by synthesizing the clock signal output from the clock signal output circuit 171 and the reset signal MS2 from the maximum value comparison circuit 177B is provided at the clock input terminal of the random number generation circuit 173B. The sum signal as an output signal from the OR circuit using the signal and the reset signal S2 as input signals. When the random number generation circuit 173A updates the numerical data to a predetermined final value, it outputs a random number loop signal RIJ1. Further, when the random number generation circuit 173B updates the numerical data to a predetermined final value, it outputs a random number loop signal RIJ2.

  The selectors 174A and 174B are circuits for selecting a method for changing the permutation, which is the update order of the numerical data, in response to the random number cyclic signals RIJ1 and RIJ2 being output by the random number generation circuits 173A and 173B, respectively. In this embodiment, a plurality of methods are defined in advance as methods for changing the permutation when the numerical data is updated from a predetermined initial value to a predetermined final value. For example, the first method is a method in which the permutation is automatically changed when the numerical data is updated to the final value. The ARSC 175A, which is a 12-bit random number sequence change register, and the BRSC 175B, which is a 16-bit random number sequence change register. The permutation is changed regardless of the stored value at. The second method is a method in which the permutation is changed according to the fact that predetermined numerical permutation change data is set in the ARSC 175A and the BRSC 175B when the numerical data is updated to the final value. The third method is a method in which the permutation is not changed even when the numerical data is updated to the final value, and the random number sequence changing circuits 176A and 176B are numerical values whose random values are always in an order according to a certain rule. Data R1 and R2 are output.

  12A is a block diagram illustrating a configuration example of the ARSC 175A, and FIG. 12B is a block diagram illustrating a configuration example of the BRSC 175B. The ARSC 175A shown in FIG. 12A is an 8-bit register that can be written by the user program and read by the random number sequence change circuit 176A via the selector 174A, and its initial value is “0” (= 00h). Is set. Note that only “1” writing to the 0th bit [bit 0] is effective for writing to the ARSC 175A by the user program. As a method for changing the permutation, when “1” is written to the 0th bit [bit 0] of the ARSC 175A when the second method described above is selected by the selector 174A, the numerical data reaches the final value. The update rule, which is a rule for determining the order in which the random number sequence change circuit 176A outputs numerical data, can be changed from the beginning of the updated next cycle. The BRSC 175B shown in FIG. 12B is an 8-bit register that can be written by the user program and read by the random number sequence change circuit 176B via the selector 174B, and its initial value is “0” (= 00h). Is set. As for writing to BRSC 175B by the user program, only writing “1” to the 0th bit [bit 0] is effective. As a method for changing the permutation, when “1” is written to the 0th bit [bit 0] of the BRSC 175B when the second method described above is selected by the selector 174B, the numerical data reaches the final value. The update rule, which is a rule for determining the order in which the random number sequence change circuit 176B outputs the numerical data, can be changed from the beginning of the updated next cycle.

  The random number sequence changing circuits 176A and 176B are circuits that allow the numerical data generated by the random number generating circuits 173A and 173B to be changed to permutations according to a predetermined update rule. For example, the random number sequence change circuit 176A executes bit scramble processing such as bit replacement or transposition in the numerical data output from the random number generation circuit 173A, while the random number sequence change circuit 176B is output from the random number generation circuit 173B. Bit scramble processing such as bit replacement and transposition in numeric data is executed. Further, the random number sequence changing circuits 176A and 176B can change the permutation, which is the update order of numerical data, by changing the bit scramble key or the bit scramble table used for the bit scramble processing, for example.

  FIG. 13 is an explanatory diagram showing a permutation changing operation when the above-described first method is selected by the selector 174A as an example of the operation in the random number sequence changing circuit 176A provided for 12-bit random numbers. When the first method is selected by the selector 174A, the random number sequence C1 output from the random number generation circuit 173A is cyclically updated from a predetermined initial value to a predetermined final value. The change circuit 176A automatically changes the permutation. In the operation example shown in FIG. 13, the numerical data sequence R1 first output from the random number sequence change circuit 176A is “1 → 2 →... → 4095”.

  When the value of the numerical data sequence C1 output from the random number generation circuit 173A reaches a predetermined final value, the random number loop signal RIJ1 output from the random number generation circuit 173A is sent to the random number sequence change circuit 176A via the selector 174A. Is input. The random number sequence changing circuit 176A changes the update rule of the numerical data in response to the input of the random round signal RIJ1. At this time, the random number sequence changing circuit 176A may change the update rule by selecting the update rule according to a predetermined order from among a plurality of types of update rules prepared in advance. Alternatively, the random number sequence change circuit 176A may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 13, the numerical data sequence R1 output from the random number sequence change circuit 176A becomes “4095 → 4094 →... → 1” by the permutation change by the first update rule change. After that, the permutation is changed by changing the update rule for the second time, so that the numerical data sequence R1 output from the random number sequence changing circuit 176A becomes “1 → 3 →... → 4095 → 2 →. . In the operation example shown in FIG. 13, the numerical data string R1 output from the random number string changing circuit 176A is “4095 → 1 →... → 2047” by performing the permutation change by the third update rule change. . When the permutation is changed by the fourth update rule change, the numerical data sequence R1 output from the random number sequence changing circuit 176A becomes “1023 → 3072 →... → 3071”. When the permutation is changed by changing the update rule for the fifth time, the numerical data sequence R1 output from the random number sequence changing circuit 176A becomes “5 → 4 →... → 4091”. Further, when the initial value setting circuit 172A sets a new initial value when the random number generation circuit 173A cyclically updates the numerical data from a predetermined initial value to a predetermined final value, the random number sequence is changed. The circuit 176A changes the update rule of numerical data in response to the input of the random number round signal RIJ1, and the initial value setting circuit 172A sets a new initial value in the random number generation circuit 173A in response to the input of the random number round signal RIJ1. To do. Thereafter, the random number generation circuit 173A cyclically updates the numerical data from the initial value changed by the initial value setting circuit 172A, and the random number sequence change circuit 176A outputs the numerical data output from the random number generation circuit 173A according to the updated update rule. The arrangement of the column C1 is changed.

  The random number sequence change circuit 176B provided for the 16-bit random number also performs the same processing as the random number sequence change circuit 176A on the numeric data sequence R2 for 16-bit random number generation output from the random number generation circuit 173B. The numerical data string R2 is output in the order according to the update rule. When the first method described above is selected by the selector 174B, the numerical data string C2 output from the random number generation circuit 173B is cyclically updated from a predetermined initial value to a predetermined final value. Then, the random number sequence change circuit 176B automatically changes the permutation. Further, when the initial value setting circuit 172B sets a new initial value when the random number generation circuit 173B cyclically updates the numerical data from a predetermined initial value to a predetermined final value, the random number sequence is changed. The circuit 176B changes the update rule of the numerical data in response to the input of the random number round signal RIJ2, and the initial value setting circuit 172B sets a new initial value in the random number generation circuit 173B in response to the input of the random number round signal RIJ2. To do. Thereafter, the random number generation circuit 173B cyclically updates the numerical data from the initial value changed by the initial value setting circuit 172B, and the random number sequence change circuit 176B outputs the numerical data output from the random number generation circuit 173B in accordance with the updated update rule. The arrangement of the column C2 is changed.

  FIG. 14 is an explanatory diagram showing a permutation changing operation when the second method described above is selected by the selector 174A as another example of the operation in the random number sequence changing circuit 176A provided for 12-bit random numbers. . When the second method is selected by the selector 174A, the numerical data sequence C1 output from the random number generation circuit 173A is cyclically updated from a predetermined initial value to a predetermined final value, and the 12-bit random number sequence is changed. In response to the setting of “1” (= 01h), which is the numerical permutation change data, in the ARSC 175A that is the register, the update rule of the numerical data is changed. In the operation example shown in FIG. 14, the numerical data sequence R1 first output from the random number sequence change circuit 176A is “1 → 2 →... → 4095”. Thereafter, it is assumed that the CPU 104 executes the user program stored in the ROM 105 to write and set “1” (= 01h) as numerical permutation change data to the ARSC 175A at a predetermined timing.

  When the second method is selected by the selector 174A, the numerical permutation change data set in the ARSC 175A is read out by the random number sequence change circuit 176A, and the setting for changing the update rule of the numerical data is performed. . At this time, the random number sequence change circuit 176A selects, for example, one of a plurality of types of update rules in response to the value of the numerical data sequence C1 output from the random number generation circuit 173A reaching a predetermined final value. The update rule is changed by, for example. In the operation example shown in FIG. 14, after the random number sequence change circuit 176A outputs the numerical data “4095” corresponding to the final value in the numerical data sequence C1 output from the random number generation circuit 173A, the numerical permutation change data is set. Change the update rules accordingly. Thereafter, the random number sequence changing circuit 176A outputs “4095 → 4094 →... → 1” as the numerical data sequence R1 in accordance with the updated update rule. The ARSC 175A is initialized when the numerical permutation change data is read by the random number sequence change circuit 176A. Therefore, until the numerical permutation change data is set again in the ARSC 175A, the numerical data sequence R1 output from the random number sequence change circuit 176A is “4095 → 4094 →... → 1”.

  When the CPU 104 executes the user program stored in the ROM 105 and “1” (= 01h), which is the numerical permutation change data, is set again in the ARSC 175A, the update rule of the numerical data is changed again. In the operation example shown in FIG. 14, the random number sequence change circuit 176A outputs the numerical data “1” corresponding to the final value in the numerical data sequence C1 output from the random number generation circuit 173A, and then the numerical permutation change data is set. Change the update rules accordingly. After that, the random number sequence change circuit 176A outputs “1 → 3 →... → 4095 → 2 →.

  In the random number sequence changing circuit 176B provided for 16-bit random numbers, when the second method described above is selected by the selector 174B, the numerical data sequence C2 output from the random number generation circuit 173B is predetermined from a predetermined initial value. In response to the fact that “1” (= 01h), which is the numerical permutation change data, is set in BRSC175B, which is a 16-bit random number sequence change register, is updated cyclically to the final value of Change the rules. In this way, the random number sequence change circuit 176B can output the numerical data sequence R2 in accordance with the updated update rule.

  The maximum value comparison circuits 177A and 177B shown in FIG. 11 compare the numerical data sequences R1 and R2 output from the random number sequence change circuits 176A and 176B, respectively, with the predetermined maximum values. In this circuit, only numerical data within the use range is output. The maximum value comparison circuit 177A compares the numerical data output from the random number sequence change circuit 176A with the 12-bit random number maximum value (KRMS) set in the user program management area of the ROM 105. When the numerical data is less than or equal to the maximum value, the numerical value data is output by the maximum value comparison circuit 177A and input to the random value register 181A. On the other hand, when the numerical data is larger than the maximum value, the maximum value comparison circuit 177A outputs the reset signal MS1. The reset signal MS1 output from the maximum value comparison circuit 177A is input to the clock input terminal of the random number generation circuit 173A, whereby the numerical data output from the random number generation circuit 173A and the random number sequence change circuit 176A are output. Numeric data is changed. If the numerical data output from the random number sequence changing circuit 176A after this change is larger than the maximum value, the output of the reset signal MS1 is repeated until it becomes equal to or less than the maximum value. By performing such an output operation of the reset signal MS2 within a period sufficiently shorter than the cycle of the stored value update signal KT output from the random value register 181A, for example, only numerical data that is equal to or less than the maximum value is stored in the random value register. It can be output as a 12-bit random value stored in 181A.

  The maximum value comparison circuit 177B compares the numerical data output from the random number sequence change circuit 176B with the 16-bit maximum random value (KRXS) set in the user program management area of the ROM 105. When the numerical data is less than or equal to the maximum value, the numerical value data is output by the maximum value comparison circuit 177B and input to the random value register 181B. On the other hand, when the numerical data is larger than the maximum value, the maximum value comparison circuit 177B outputs the reset signal MS2. The reset signal MS2 output from the maximum value comparison circuit 177B is input to the clock input terminal of the random number generation circuit 173B, whereby the numerical data output from the random number generation circuit 173B and the random number sequence change circuit 176B are output. Numeric data is changed. If the numerical data output from the random number sequence changing circuit 176B after this change is larger than the maximum value, the output of the reset signal MS2 is repeated until it becomes equal to or less than the maximum value. By performing such an output operation of the reset signal MS2 within a period sufficiently shorter than the cycle of the clock signal S1 output from the clock signal output circuit 171, only numerical data that is equal to or less than the maximum value is stored in the random value register 181B. It can be output as a stored 16-bit random value.

  FIG. 15 is an explanatory diagram showing the operation of resetting numerical data by the maximum value comparison circuit 177A provided for 12-bit random numbers. In the operation example shown in FIG. 15, the 12-bit random number maximum value (KRMS) is set to “512” as shown in FIG. 1 → 2 → ... → 4096 ”.

  In this case, the maximum value comparison circuit 177A outputs the numerical data and inputs it to the random value register 181A during the period in which the numerical data output from the random number sequence change circuit 176A is “1” to “512”. On the other hand, when the numerical data output from the random number sequence change circuit 176A becomes larger than “512”, the maximum value comparison circuit 177A outputs the reset signal MS1 to be input to the random number generation circuit 173A. By repeating the output operation of the reset signal MS1, the maximum value comparison circuit 177A continuously changes the numerical data output from the random number sequence change circuit 176A from “513” to “4095”, and thereafter “1”. To return. At this time, the numerical data output from the maximum value comparison circuit 177A remains “512”. When the output operation of the reset signal MS1 is performed within a period sufficiently shorter than the normal update period of the random number value, and the numerical data “1” is output from the random number sequence change circuit 176A, the maximum value comparison circuit 177A outputs this numerical data as it is and inputs it to the random value register 181A. By such numerical value resetting operation by the maximum value comparison circuit 177A, only numerical data equal to or less than the maximum value set as the 12-bit random number maximum value (KRMS) can be input to the random value register 181A.

  The inversion circuit 178 illustrated in FIG. 10 inverts the clock signal S1 input from the clock signal output circuit 171 to generate an inversion clock signal S2. The inverting circuit 178 outputs the generated inverted clock signal S2 and inputs it to the latch signal generating circuit 180. The timer circuit 179 measures the time during which the start winning signal SS is input from the start port switch 22, and outputs the start winning signal SS when the measured time reaches a predetermined time (for example, 3 milliseconds). , Input to the latch signal generation circuit 180. For example, the timer circuit 179 is configured by an up counter or a down counter, and is activated in response to the start winning signal SS being turned on. In this case, the timer circuit 179 up-counts or down-counts the internal system clock CLK during the period in which the start winning signal SS is on. Then, when the count value obtained by counting up or down reaches a value corresponding to 3 milliseconds, the timer circuit 179 determines that the input signal is the start winning signal SS, and sets the start winning signal SS to the start winning signal SS. The data is output and input to the latch signal generation circuit 180.

  The latch signal generation circuit 180 is configured using, for example, a flip-flop. For example, when the latch signal generation circuit 180 is configured using a D flip-flop, the D input terminal is connected to the output terminal of the timer circuit 179, and the clock input terminal is connected to the output terminal of the inverting circuit 178. That's fine. The latch signal generation circuit 180 generates the latch signal SL by outputting the start winning signal SS output from the timer circuit 179 in synchronization with the rising edge of the inverted clock signal S2 output from the inversion circuit 178.

  The random value registers 181A and 181B store numerical data output from the maximum value comparison circuits 177A and 177B, respectively, as random values. FIG. 16A is a block diagram illustrating a configuration example of a random value register 181A serving as a 12-bit random value register (ARND), and FIG. 16B illustrates a random value serving as a 16-bit random value register (BRND). It is a block diagram which shows the structural example of the register | resistor 181B. The random value registers 181A and 181B are both 16-bit registers, but the random value register 181A that is a 12-bit random value register (ARND) is the seventh to fourth registers 8 of the upper 8-bit register ARND (H). The stored value in bits [bit 7-4] is invalid and is used as a register for storing a 12-bit random number.

  In this embodiment, the random value register 181A provided for the 12-bit random number is input from the maximum value comparison circuit 177A in response to the register read signal supplied from the CPU 104 being turned on, for example. Numeric data that is stored as a random value. When the random value register 181A stores a random value, for example, the stored value update signal KT is turned on for a predetermined period and then turned off. Thus, the random number generation circuit 173A only needs to be able to update the numerical data in response to the rising edge of the stored value update signal KT output from the random value register 181A. On the other hand, the random value register 181B provided for the 16-bit random number is a numerical value input from the maximum value comparison circuit 177B in response to the latch signal SL output from the latch signal generation circuit 180 being turned on. Capture and store data as random values.

  The random number circuit 103 is provided with a 12-bit random number maximum value reading register (ARMX) as shown in FIG. 16C and a 16-bit random number maximum value reading register (BRMX) as shown in FIG. It may be done. The 12-bit random number maximum value reading register (ARMX) shown in FIG. 16C is a register that enables confirmation of the 12-bit random number maximum value (KRMS) set in the user program management area of the ROM 105, and is a 16-bit register. Of these, by invalidating the stored value in the seventh to fourth bits [bit 7-4] of the upper 8-bit register ARMX (H), it is used as a register for storing a 12-bit numerical value. A 16-bit random number maximum value reading register (BRMX) shown in FIG. 16D is a 16-bit register that enables confirmation of the 16-bit random number maximum value (KRXS) set in the user program management area of the ROM 105.

  The CPU 104 shown in FIG. 10 reads the user program and data stored in the ROM 105, and uses the RAM 106 as a work area to perform a control operation according to the program. FIG. 17 is a diagram showing an example of an address map in the game control microcomputer 100. As shown in FIG. 17, the area from addresses 0000h to 01FFh is a work area assigned to the RAM 106. An area of addresses 1000h to 101Ch is a built-in register area assigned to built-in registers such as the random number circuit 103, the timer circuit 107, and the serial communication circuit 108. The area from address 2000h to address 200Fh is a chip select signal decode area assigned to an address decoder built in the game control microcomputer 100. The area from address E000h to FFFFh is allocated to the ROM 105, and includes a user program management area and a user program / data area.

  User programs and user data created in advance by the user are stored in the user program / data area, which is an area from addresses E080h to FFFFh in the ROM 105. The user program management area, which is an area from addresses E000h to E07Fh in the ROM 105, stores user program management data used when the CPU 104 executes the user program and sets the operation content of the pachinko gaming machine 1. .

  FIG. 18 is a diagram showing an example of an address map in the user program management area shown in FIG. As shown in FIG. 18, in the area of E01Bh, among the plurality of types of I class interrupt (IRQ) generated by the gaming control microcomputer 100, the highest priority is set. Data indicating the priority interrupt setting (KHPR) is stored. FIG. 19A is an explanatory diagram showing a setting example of the highest priority interrupt setting data stored in the area of address E01Bh. FIG. 19B shows, as an example of the specific setting of the highest priority interrupt setting data, the default priority of interrupt factors and the priority of interrupt factors when “05h” is set in the area E01Bh. It shows.

  As shown in FIG. 19B, in the default state where the highest priority interrupt setting data is not set in the area of E01Bh, the interrupt factor due to the signal input to the predetermined IRQ terminal has the highest priority, and then the timer circuit The priority of interrupt requests from the 107 channels (CH0 to CH3) is high, and the priority is set to be low in the order of error interrupt request, reception interrupt request, and transmission interrupt request from the serial communication circuit 108. . That is, even in the default state, among the interrupt requests from the serial communication circuit 108, the error interrupt request has a higher priority than other interrupt factors such as a reception interrupt request and a transmission interrupt request. Therefore, interrupt processing based on an error interrupt request from the serial communication circuit 108 is executed with priority over interrupt processing based on a reception interrupt request or transmission interrupt request that is different from the error interrupt request from the serial communication circuit 108. Will be.

  When “05h” is set as the highest priority interrupt setting data in the area of address E01Bh, the priority of the error interrupt request from the serial communication circuit 108 is determined by the interrupt factor due to the signal input to the IRQ terminal, the timer circuit It becomes higher than the priority of the interrupt request from 107, and has the highest priority among the factors of a plurality of types of I class interrupts (IRQ) generated in the game control microcomputer 100. In this way, by setting the highest priority interrupt setting data in the area of address E01Bh, the priority order of the factors of the plurality of types of I class interrupts (IRQ) can be changed from the default setting.

  In the area of E01Ch address and the area of E01Dh shown in FIG. Data indicating KRSS2) is stored. FIG. 20A is an explanatory diagram illustrating the contents of data indicating the first random number initial setting (KRSS1) stored in the area of the E01Ch address. FIG. 20B is an explanatory diagram illustrating the contents of data indicating the second random number initial setting (KRSS2) stored in the area of E01Dh address.

  As shown in FIGS. 20A and 20B, the first and second random number initial setting data are each composed of 8-bit data, but the seventh to fifth of the first random number initial setting data. Bits [bits 7-5] are unused. The fourth and third bits [bits 4-3] of the first random number initial setting data shown in FIG. 20A are random numbers used in the 12-bit random numbers and the 16-bit random numbers generated by the random number circuit 103. Show. In the example shown in FIG. 20A, when the fourth and third bits [bit 4-3] of the first random number initial setting data are “00”, neither the 12-bit random number nor the 16-bit random number is used. "01" indicates that only a 12-bit random number is used, "10" indicates that only a 16-bit random number is used, and "11" indicates that a 12-bit random number and a 16-bit random number are used. It shows that both are used. The second bit [bit 2] of the first random number initial setting data indicates the setting for the update cycle of the 16-bit random number generated by the random number circuit 103. In the example shown in FIG. 20A, when the second bit [bit 2] of the first random number initial setting data is “0”, the 16-bit random number is updated at the cycle of the internal system clock CLK. "" Indicates that a 16-bit random number is updated at a cycle 16 times the internal system clock CLK.

  The first and 0th bits [bits 1-0] of the first random number initial setting data indicate settings for the start values after the second round in the 12-bit random number. In the example shown in FIG. 20A, when the first and 0th bits [1-0] of the first random number initial setting data are “00”, the start value is not changed. In some cases, the value is changed to a value based on an ID number that is a unique identification number assigned to each game control microcomputer 100. In the case of "10", the value is changed to an addition value of stored data in the RAM 106 as a user RAM. "11" indicates that the value is changed to the value stored in the designated address in the RAM 106 which is the user RAM.

  The seventh bit [bit 7] of the second random number initial setting data shown in FIG. 20B indicates the setting for the start value of the first round in the 12-bit random number. In the example shown in FIG. 20B, when the seventh bit [bit 7] of the second random number initial setting data is “0”, the start value of the first round in the 12-bit random number is “001h” (the default value). When the value is “1”, the value is based on an ID number, which is a unique identification number assigned to each game control microcomputer 100.

  The sixth and fifth bits [bits 6-5] of the second random number initial setting data indicate settings for a method for changing a random number sequence in a 12-bit random number. In the example shown in FIG. 20B, when the sixth and fifth bits [bits 6-5] of the second random number initial setting data are “00”, the permutation is not changed (the third method is used). When it is “10”, it indicates that the user program can be changed after the second lap (the second method), and when it is “11”, it is automatically changed after the second lap. (The first method).

  The fourth bit [bit 4] of the second random number initial setting data indicates the setting for the start value of the first round in the 16-bit random number. In the example shown in FIG. 20B, when the fourth bit [bit 4] of the second random number initial setting data is “0”, the start value of the first round in the 16-bit random number is the default value “0001h” ( When the value is “1”, the value is based on an ID number that is a unique identification number assigned to each game control microcomputer 100.

  The third and second bits [bit 3-2] of the second random number initial setting data indicate the setting for the start value after the second round in the 16-bit random number. In the example shown in FIG. 20B, when the third and second bits [bit 3-2] of the second random number initial setting data are “00”, it indicates that the start value is not changed, and “01” Indicates that the value is changed to a value based on an ID number that is a unique identification number assigned to each game control microcomputer 100, and when “10”, the addition value of the stored data in the RAM 106, which is the user RAM, is indicated. When the value is “11”, the value is changed to the value stored in the designated address in the RAM 106 which is the user RAM.

  The first and 0th bits [bits 1-0] of the second random number initial setting data indicate settings for a method for changing a random number sequence in a 16-bit random number. In the example shown in FIG. 20B, when the first and 0th bits [bits 1-0] of the second random number initial setting data are “00”, the permutation is not changed (the third method is used). When it is “10”, it indicates that the user program can be changed after the second lap (the second method), and when it is “11”, it is automatically changed after the second lap. (The first method).

  In the area E01Eh address and the area E01Fh shown in FIG. 18, data indicating a 12-bit random number maximum value (KRMS) used for setting the maximum value of the 12-bit random number generated by the random number circuit 103 is stored. Remembered. In the example shown in FIG. 18, the upper byte (8 bits) of the data indicating the 12-bit random number maximum value (KRMS) is stored in the area of E01Eh address, and the 12-bit random number maximum value (KRMS) is stored in the area of E01Fh address. The lower byte (8 bits) of the indicated data is stored.

  Data indicating the 16-bit random number maximum value (KRXS) used for setting the maximum value of the 16-bit random number generated by the random number circuit 103 is stored in the area of the address E020h and the area of the address E021h. In the example shown in FIG. 18, the upper byte (8 bits) of the data indicating the 16-bit random number maximum value (KRXS) is stored in the area of address E020h, and the 16-bit random number maximum value (KRXS) is stored in the area of address E021h. The lower byte (8 bits) of the indicated data is stored.

  In the area of address E022h and the area of address E023h, data indicating the first serial communication initial setting (KSCM1) used for initial setting of the serial communication circuit 108, and the second serial communication initial setting (KSCM2) ) Is stored. FIG. 21A is an explanatory view exemplifying the contents of data indicating the first serial communication initial setting (KSCM1) stored in the area of address E022h. FIG. 21B is an explanatory diagram illustrating the contents of data indicating the second serial communication initial setting (KSCM2) stored in the area of address E023h.

  As shown in FIGS. 21A and 21B, each of the first and second serial communication initial setting data is composed of 8-bit data. The sixth bit [bit 7-6] and the seventh to fourth bits [bit 7-4] of the second serial communication initial setting data are unused. The fifth bit [bit 5] of the first serial communication initial setting data shown in FIG. 21A indicates whether to use an interrupt when the transmission data is empty. Here, the interruption at the time of transmission data empty is an interruption that occurs when data is transferred from the transmission data register provided in the transmission operation unit 202 (FIG. 25) of the serial communication circuit 108 to the transmission shift register. It is included in the transmission interrupt generated in the serial communication circuit 108. In the example shown in FIG. 21A, when the fifth [bit 5] of the first serial communication initial setting data is “0”, it indicates that an interrupt at the time of transmission data empty is not generated, and when it is “1”. It indicates that an interrupt is generated when transmission data is empty.

  The fourth bit [bit 4] of the first serial communication initial setting data indicates whether to use an interrupt when transmission is completed. Here, the transmission completion interrupt is an interrupt that occurs when the data transmission operation by the transmission operation unit 202 of the serial communication circuit 108 is completed, and is included in the transmission interrupt that occurs in the serial communication circuit 108. In the example shown in FIG. 21A, when the fourth bit [bit 4] of the first serial communication initial setting data is “0”, it indicates that an interrupt at the completion of transmission is not generated, and when it is “1”. Indicates that an interrupt is generated when transmission is completed.

  The third bit [bit 3] of the first serial communication initial setting data indicates a setting as to whether or not to use an interrupt when receiving data is transferred. Here, the interrupt at the time of receiving data transfer is an interrupt that occurs when the value of the receiving shift register provided in the receiving operation unit 201 (FIG. 25) of the serial communication circuit 108 is transferred to the receiving data register. It is included in the reception interrupt generated in the serial communication circuit 108. In the example shown in FIG. 21A, when the third bit [bit 3] of the first serial communication initial setting data is “0”, it indicates that an interrupt at the time of receiving data transfer is not generated and is “1”. It sometimes indicates that an interrupt is generated when receiving data is transferred.

  The second bit [bit 2] of the first serial communication initial setting data indicates whether to use an interrupt when an idle line is detected. Here, the interrupt at the time of detecting the idle line is an interrupt that occurs when an idle line consisting of “1” for one frame is detected as received data in the reception operation unit 201 of the serial communication circuit 108. It is included in the reception interrupt generated at 108. In the example shown in FIG. 21A, when the second bit [bit 2] of the first serial communication initial setting data is “0”, it indicates that no interrupt is generated when the idle line is detected, and is “1”. In some cases, an interrupt is generated when an idle line is detected.

  The first bit [bit 1] of the first serial communication initial setting data indicates whether to use the transmission operation unit 202 of the serial communication circuit 108 or not. In the example shown in FIG. 21A, when the first bit [bit 1] of the first serial communication initial setting data is “0”, it indicates that serial transmission by the transmission operation unit 202 is not used, and “1”. In some cases, serial transmission by the transmission operation unit 202 is used.

  The 0th bit [bit 0] of the first serial communication initial setting data indicates whether or not the reception operation unit 201 of the serial communication circuit 108 is used. In the example shown in FIG. 21A, when the 0th bit [bit 0] of the first serial communication initial setting data is “0”, it indicates that serial reception by the reception operation unit 201 is not used, and “1”. In some cases, serial reception by the reception operation unit 201 is used.

  The third bit [bit 3] of the second serial communication initial setting data shown in FIG. 21B indicates whether or not to use an interrupt at the time of an overrun error. Here, an interrupt at the time of an overrun error occurs when the reception shift register provided in the reception operation unit 201 receives the next data before the reception data in the serial communication circuit 108 is read by the user program. And is included in an error interrupt generated in the serial communication circuit 108. In the example shown in FIG. 21B, when the third bit [bit 3] of the second serial communication initial setting data is “0”, it indicates that an interrupt at the time of an overrun error is not generated and is “1”. It sometimes shows that an interrupt at the time of an overrun error is generated.

  The second bit [bit 2] of the second serial communication initial setting data indicates whether to use an interrupt at the time of a noise error. Here, an interrupt at the time of a noise error is an interrupt based on an error that occurs when noise of data received by the serial communication circuit 108 is detected, and is included in an error interrupt that occurs at the serial communication circuit 108. In the example shown in FIG. 21B, when the second bit [bit 2] of the second serial communication initial setting data is “0”, it indicates that an interrupt at the time of noise error is not generated, and when it is “1”. Indicates that an interrupt is generated when a noise error occurs.

  The first bit [bit 1] of the second serial communication initial setting data indicates whether to use an interrupt at the time of a framing error. Here, the interrupt at the time of a framing error is an interrupt based on an error that occurs when “0” is detected in the stop bit of the data received by the serial communication circuit 108, and an error interrupt that occurs in the serial communication circuit 108 include. In the example shown in FIG. 21B, when the first bit [bit 1] of the second serial communication initial setting data is “0”, it indicates that no framing error interrupt is generated, and when it is “1”. It indicates that an interrupt is generated when a framing error occurs.

  The 0th bit [bit 0] of the second serial communication initial setting data indicates whether to use an interrupt at the time of a parity error. Here, the interrupt at the time of a parity error is an interrupt based on an error that occurs when the parity of the data received by the serial communication circuit 108 and the parity bit in the received data do not match, and is generated by the serial communication circuit 108 Included in error interrupt. In the example shown in FIG. 21B, when the 0th bit [bit 0] of the second serial communication initial setting data is “0”, it indicates that an interrupt at the time of parity error is not generated, and when it is “1”. It indicates that an interrupt is generated when a parity error occurs.

  As described above, the error interrupt generated in the serial communication circuit 108 includes four types of interrupts, that is, an interrupt at the time of parity error, an interrupt at the time of overrun error, an interrupt at the time of framing error, and an interrupt at the time of noise error. It is included.

  In addition to the game control user program, the ROM 105 provided in the game control microcomputer 100 shown in FIG. 10 stores various data tables used for controlling the progress of the game. For example, the ROM 105 stores table data constituting a plurality of determination tables and determination tables prepared for the CPU 104 to make various determinations and determinations. The determination table includes a big hit determination table that is referred to for determining whether or not the variable display result is a big hit by using the confirmed special symbol in the special figure game by the special symbol display device 4 as a big hit symbol, or a big hit. Probability change determination table that is referred to determine whether to make a promiscuous big hit or a normal big hit, reach determination that is referred to in order to determine whether or not the variable display mode of decorative symbols is to be reached when lost Includes tables and the like. For example, the jackpot determination table includes determination data that associates a determination result as to whether or not the variable display result is a jackpot with a random value read from the random number circuit 103 (for example, a value of a 16-bit random number). It only has to be done.

  In addition, the determination table stored in the ROM 105 includes a confirmed special symbol determination table for determining a confirmed special symbol to be derived and displayed as a variable display result in the special symbol game, a special symbol game or an image by the special symbol display device 4. A variable display pattern determination table for determining a variable display pattern such as a symbol during variable display of decorative symbols on the display device 5, an effect display execution determination table for determining whether or not to perform various effect displays, etc. It is included.

  In the RAM 106 provided in the game control microcomputer 100, for example, a game control data holding area 130 as shown in FIG. 22 is provided as an area for holding various data used for controlling the game state and the like in the pachinko gaming machine 1. Is provided. At least a part of the RAM 106 is a backup RAM that is backed up by a backup power source created on the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 106 is stored for a predetermined period. In this embodiment, it is assumed that the entire RAM 106 is a backup RAM that is backed up. The game control data holding area 130 shown in FIG. 22 includes a special figure storage unit 131, a confirmed special symbol storage unit 132, a game control flag setting unit 133, a game control timer setting unit 134, and a game control counter setting unit. 135 and a game control buffer setting unit 136.

  The special figure holding storage unit 131 has a start condition for executing a special figure game by the special symbol display device 4 when a game ball is won in the start winning opening provided in the normal variable winning ball apparatus 6 and the special symbol display apparatus 4 is executed. The hold information relating to the special figure game in which the start condition for starting the variable display is not established due to the reason that the special figure game is being executed is stored. For example, the special figure hold storage unit 131 associates with the hold numbers in the order of winning to the start winning opening, and shows the random value for determining the big hit extracted from the random number circuit 103 by the CPU 104 based on the establishment of the starting condition by the winning. Numerical data is stored as pending data until the number reaches a predetermined upper limit (eg, “4”).

  The confirmed special symbol storage unit 132 stores data indicating a confirmed special symbol derived and displayed as a variable display result in the special symbol game by the special symbol display device 4. The game control flag setting unit 133 sets a plurality of types of flags that are set or cleared in accordance with the gaming state in the pachinko gaming machine 1 and signals transmitted from the winning prize switch or the like via the switch circuit 111. For storing data. The game control timer setting unit 134 stores data indicating a plurality of types of timer values used for game control in the pachinko gaming machine 1. The game control counter setting unit 135 stores data indicating a plurality of types of count values used for game control in the pachinko gaming machine 1. The game control buffer setting unit 136 temporarily stores various data used for game control in the pachinko gaming machine 1. The circuit used for flag setting and counter / timer may be constituted by a register circuit provided separately from the RAM 106.

  The game control flag setting unit 133 includes, for example, a clear flag, a main backup flag, a payout communication error detection flag, a serial communication error flag, a communication error notification flag, a transmission setting enable flag, a transmission completion flag, and a 12-bit random number start value. Change flag, 16-bit random number start value change flag, 12-bit random number permutation change flag, 16-bit random number permutation change flag, special symbol process flag, jackpot flag, probable change flag, prize ball process flag, retransmission flag, prize ball ACK A reception flag, a payout abnormality notification flag, a payout error notification flag, a payout error notification flag, a payout error release flag, and the like are provided.

  The clear flag indicates whether or not a clear signal from the clear switch 304 included in the power supply board 10 is in an ON state when power supply to the pachinko gaming machine 1 is started. That is, if the clear signal is in the on state at the start of power supply, the clear flag is set in the on state, while if the clear signal is in the off state, the clear flag is held in the off state. The main backup flag indicates whether or not a predetermined memory protection process has been executed by the gaming control microcomputer 100 when power supply to the pachinko gaming machine 1 is stopped. For example, when “55H” is set as the value of the main backup flag, backup is present (ON state), while when a value other than “55H” is set, backup is not present (OFF state).

  The payout communication error detection flag indicates that an error has occurred in the communication operation between the main board 11 and the payout control board 15. That is, when a predetermined error occurs during execution of processing for performing communication with the payout control board 15 in the main board 11, the payout communication error detection flag is set to the on state. The serial communication error flag indicates that an error has occurred in the communication operation in the serial communication circuit 108. For example, the serial communication error flag is set to an on state in response to an error interrupt request from the serial communication circuit 108. The communication error notification flag is set to the on state when notification that an abnormality has occurred by display on the image display device 5 is started in response to the serial communication error flag being turned on.

  The transmission setting enable flag indicates that the serial communication circuit 108 can be set to perform data transmission. For example, the transmission setting enable flag is set to an on state in response to an interrupt request from the serial communication circuit 108 when the transmission data is empty. The transmission completion flag indicates that data transmission has been completed in the serial communication circuit 108. For example, the transmission completion flag is set to an on state in response to an interrupt request when transmission is completed from the serial communication circuit 108.

  The 12-bit random number start value change flag indicates whether the user program changes the start value after the second round of the 12-bit random number generated by the random number circuit 103. For example, when the random number round circuit RIJ1 from the random number generation circuit 173A provided in the random number circuit 103 is output to the CPU 104, the CPU 104 sets 12 bits in response to the random number round signal RIJ1 being turned on. The random number start value change flag may be set to the on state. Alternatively, when the CPU 104 detects the elapse of a predetermined time during execution of the predetermined timer interrupt process, the 12-bit random number start value change flag may be set to the on state. When the 12-bit random number start value change flag is on, the CPU 104 executes a process for changing the start value of the next cycle in the 12-bit random number generated by the random number circuit 103. The 16-bit random number start value change flag indicates whether or not the user program changes the start value after the second round of the 16-bit random number generated by the random number circuit 103. For example, when the random number round circuit RIJ2 from the random number generation circuit 173B provided in the random number circuit 103 is output to the CPU 104, the CPU 104 uses the random number round circuit RIJ2 for the 16-bit random number in response to the ON state. The start value change flag may be set to the on state. Alternatively, when the CPU 104 detects the elapse of a predetermined time during execution of the predetermined timer interruption process, the 16-bit random number start value change flag may be set to an on state. When the 16-bit random number start value change flag is on, the CPU 104 executes a process for changing the start value of the next cycle in the 16-bit random number generated by the random number circuit 103.

  The 12-bit random number permutation change flag indicates whether or not the permutation in the second and subsequent rounds of the 12-bit random number generated by the random number circuit 103 is changed by the user program. For example, when the random number round circuit RIJ1 from the random number generation circuit 173A provided in the random number circuit 103 is output to the CPU 104, the CPU 104 sets 12 bits in response to the random number round signal RIJ1 being turned on. The random number permutation change flag may be set to the on state. Alternatively, the 12-bit random number permutation flag may be set to the on state when the CPU 104 detects the elapse of a predetermined time during execution of the predetermined timer interrupt process. When the 12-bit random number permutation flag is on, the CPU 104 executes processing for changing the permutation of the next cycle in the 12-bit random number generated by the random number circuit 103. The 16-bit random number permutation change flag indicates whether or not the permutation in the second and subsequent rounds of the 16-bit random number generated by the random number circuit 103 is changed by the user program. For example, when the random number loop signal RIJ2 from the random number generation circuit 173B provided in the random number circuit 103 is output to the CPU 104, the CPU 104 responds to the fact that the random number loop signal RIJ2 is turned on to 16 bits. The random number permutation change flag may be set to the on state. Alternatively, the 16-bit random number permutation change flag may be set to an on state when the CPU 104 detects the elapse of a predetermined time during execution of a predetermined timer interrupt process. When the 16-bit random number permutation change flag is in the ON state, the CPU 104 executes processing for changing the permutation of the next cycle in the 16-bit random number generated by the random number circuit 103.

  The special symbol process flag indicates which process should be selected and executed in the special symbol process (step S78 in FIG. 40 and FIG. 51) executed corresponding to the special symbol display device 4. The big hit flag is set to the on state when it is determined that the variable display result in the special figure game is a big hit when the special symbol display device 4 starts the special figure game. After that, when the big hit gaming state based on the big win in the special figure game ends, the big hit flag is cleared and turned off. The probable change flag is set to the on state when the variable display result in the special symbol game by the special symbol display device 4 becomes the probable big hit and the big hit gaming state based on the big hit ends. On the other hand, the flag during probability change is cleared when, for example, the number of executions of the special figure game in a high probability state reaches a predetermined probability change end reference value or when the variable display result in the special figure game is usually a big hit. Turns off.

  The prize ball process flag indicates which process should be selected and executed in the prize ball process (step S75 in FIG. 40 and FIG. 44A) for setting the number of prize balls. After the re-transmission flag is set to transmit a payout control command to the payout control board 15, a predetermined prize ball ACK waiting time elapses without receiving a prize ball ACK command from the payout control board 15 Is set to the on state. On the other hand, the retransmission flag is cleared and turned off, for example, when a winning ball ACK command is received before the winning ball ACK waiting time elapses.

  The prize ball ACK reception flag indicates whether or not a prize ball ACK command from the payout control board 15 has been received. That is, the prize ball ACK reception flag is set to the on state when the prize ball ACK command is received. The payout abnormality notification flag is in an on state when a notification that an abnormality has occurred due to display on the image display device 5 is started in response to the retransmission flag or the payout communication error detection flag being turned on. Set to

  The payout error notification flag indicates whether a payout error notification command from the payout control board 15 has been received. That is, the payout error notification flag is set to the on state when the payout error notification command is received. The payout error notification flag is set to the on state when notification that an abnormality has occurred due to the display on the image display device 5 is started in response to the payout error notification flag being turned on. The payout error cancel flag indicates whether or not a payout error cancel command from the payout control board 15 has been received. That is, the payout error release flag is set to the on state when the payout error release command is received.

  The game control timer setting unit 134 is provided with, for example, a prize ball control timer or a variable display time timer. The prize ball control timer is used to measure various times when various processes relating to the prize ball payout are executed on the main board 11. The variable display time timer is for measuring the variable display time (total variation time) of special symbols in the special game.

  The game control counter setting unit 135 includes, for example, a wait counter, a total prize ball number counter, first to third payout number instruction counters, a command transmission number counter, a command reception number counter, a command transmission waiting counter, and the like. . In addition, the game control counter setting unit 135 may be provided with a variable display number counter for counting the number of executions of the special figure game in the high probability state or the time reduction state.

  When the power supply to the pachinko gaming machine 1 is started and the game control process (process for controlling the progress of the game) can be executed by the game control microcomputer 100, the weight counter It is used to delay the timing for starting execution of the control process. For example, when the power supply to the pachinko gaming machine 1 is started and the game control microcomputer 100 is activated, an initialization wait number designation value corresponding to a predetermined delay time is set in the wait counter. Thereafter, an update process such as sequentially subtracting the weight count value, which is the value of the wait counter, is performed, and when the value reaches a predetermined delay end determination value, execution of the game control process is started.

  The total award ball counter has not yet completed a payout instruction from the main board 11 to the payout control board 15 among the winning balls to be paid out based on the detection of the game ball by each winning opening switch. This is for counting the total number of prize balls. For example, when the game control microcomputer 100 determines that the winning detection signal from the count switch 24 is in the ON state, 15 is added to the total prize ball count value which is the value of the total prize ball counter. When it is determined that the winning detection signal from any of the winning opening switches 25A to 25D is in the on state, the total winning ball count value is incremented by 7, and the winning detection signal from the start opening switch 22 is in the on state. 4 is added to the total prize ball count value. On the other hand, for example, when a prize ball ACK command transmitted from the payout control board 15 is received by the game control microcomputer 100 after the first payout number specifying command is transmitted from the main board 11 to the payout control board 15, The prize ball count value is decremented by 15. For example, when the prize ball ACK command is received after the second payout number designation command is transmitted from the main board 11 to the payout control board 15, the total prize ball number count value is subtracted by 7, for example, the third payout number. When the prize ball ACK command is received after the designation command is transmitted, 4 is subtracted from the total prize ball count value. The timing for subtracting the total prize ball count value is when a prize ball ACK command is received after any one of the first to third payout number designation commands is transmitted from the main board 11 to the payout control board 15. It is not limited, and may be a stage before setting for transmitting the first to third payout number designation commands. As described above, the total number of winning balls to be paid out by the total winning ball counter should be paid out in accordance with the winning detection signals from the start port switch 22, the count switch 24, and the winning port switches 25A to 25D. Data indicating the progress of the game, including the number of prize game media data that can specify the number of prize balls, is stored in the RAM 106.

  The first to third payout number instruction counters issue respective first to third payout number designation commands from the main board 11 to the payout control board 15 based on the detection of the game ball by each winning a prize opening switch. This is for counting the number of times to be transmitted. For example, when the game control microcomputer 100 determines that the winning detection signal from the count switch 24 is in the ON state, 1 is added to the first payout number instruction count value which is the value of the first payout number instruction counter. . When it is determined that the winning detection signal from any of the winning opening switches 25A to 25D is in the ON state, the second payout number instruction count value which is the value of the second payout number instruction counter is incremented by 1, and the start is started. When it is determined that the winning detection signal from the mouth switch 22 is in the ON state, the third payout number instruction count value that is the value of the third payout number instruction counter is incremented by one. On the other hand, for example, when the game control microcomputer 100 receives the prize ball ACK command after the first payout number designation command is transmitted from the main board 11 to the payout control board 15, the first payout number instruction count value is 1. Subtracted. Further, for example, when the game control microcomputer 100 receives a prize ball ACK command after the second payout number designation command is transmitted from the main board 11 to the payout control board 15, the second payout number instruction count value is 1. For example, when the game control microcomputer 100 receives a prize ball ACK command after the third payout number specifying command is transmitted from the main board 11 to the payout control board 15, for example, the third payout number instruction count value is calculated. 1 is subtracted. The timing for subtracting each of the first to third payout number instruction count values is, for example, after each of the first to third payout number designation commands is transmitted from the main board 11 to the payout control board 15. It may be a stage before receiving the prize ball ACK command.

  The command transmission number counter counts the number of times one of the first to third payout number designation commands has been sent to the payout control board 15, and the game detected according to the detection signal from the all winning ball detection switch 29 This is to specify the difference from the number of balls as a winning number difference. For example, a predetermined initial count value (for example, “200”) is set in the command transmission count counter when power supply to the pachinko gaming machine 1 is started. Then, when a prize ball ACK command is received after any of the first to third payout number designation commands is sent from the main board 11 to the payout control board 15, a command transmission which is a value of a command transmission number counter is transmitted. While the count value is incremented by 1, when the detection signal from the all winning ball detection switch 29 is turned on, the command transmission count value is decremented by 1.

  The command reception number counter is used to count the number of commands received from the sub-side control board such as the payout control board 15 in an identifiable manner. The command transmission waiting counter is used to count the number of commands waiting to be transmitted to the sub control boards such as the effect control board 12 and the payout control board 15 so as to be specified.

  The game control buffer setting unit 136 is provided with, for example, a main checksum buffer, a reception command buffer, a transmission command buffer, and the like. The main checksum buffer is for storing a checksum calculated using stored data in a specific area of the RAM 106 when power supply to the pachinko gaming machine 1 is stopped.

  The reception command buffer is used for temporarily storing a command received from the sub-side control board by the main board 11. FIG. 23 is a diagram illustrating a configuration example of the payout reception command buffer 191 included in the reception command buffer. The payout reception command buffer 191 is for temporarily storing a command received from the payout control board 15. The payout receive command buffer 191 shown in FIG. 23 includes 12 receive command buffers # 1 to # 12, and the receive command buffer for storing the command received from the payout control board 15 is designated by the command reception number counter. Is done. Each reception command buffer # 1 to # 12 is composed of, for example, 1 byte (8 bits), and a plurality of reception command buffers can be used as ring buffers to store six reception commands of 2 bytes. .

  The transmission command buffer is used to temporarily store a command to be transmitted from the main board 11 to the sub control board. FIG. 24 is a diagram illustrating a configuration example of the payout transmission command buffer 192 included in the transmission command buffer. The payout transmission command buffer 192 is for temporarily storing a command to be transmitted from the main board 11 to the payout control board 15. The payout transmission command buffer 192 shown in FIG. 24 includes twelve transmission command buffers # 1 to # 12. The command buffer for storing a command waiting for transmission from the main board 11 to the payout control board 15 is , Specified by the command transmission waiting counter. Each of the transmission command buffers # 1 to # 12 is composed of, for example, 1 byte (8 bits), and can store six transmission commands of 2 bytes by using a plurality of transmission command buffers as ring buffers. . The transmission command buffer may include an effect transmission command buffer for temporarily storing a command to be transmitted from the main board 11 to the effect control board 12.

  In addition, in the game control data holding area 130, although a game ball that has passed through the passing gate 41 is detected by the gate switch 21, a start condition for executing the normal diagram game by the normal symbol display 40 is satisfied. And a normal diagram hold storage unit for storing hold information related to the normal diagram game in which the start condition for starting variable display is not satisfied due to the reason that the conventional normal diagram game is being executed, etc. Also good. As described above, the hold information related to the special figure game or the normal figure game is stored in the game control data holding area 130 provided on the main board 11 and used for the control of the special figure game or the normal figure game by the CPU 104.

  The timer circuit 107 included in the game control microcomputer 100 shown in FIG. 10 is configured by, for example, four channels (CH0 to CH3) of built-in 8-bit programmable counters, and is capable of generating real-time interrupts and measuring time. is there. For example, the timer circuit 107 starts counting down at a predetermined cycle from a preset count value for each channel, and when there is a channel whose count value is “00”, the interrupt flag corresponding to that channel is turned on. set. At this time, if the interrupt is permitted, the timer circuit 107 generates an interrupt request to the CPU 104.

  The serial communication circuit 108 included in the game control microcomputer 100 is a circuit that handles communication data in a full duplex, asynchronous, standard NRZ (Non Return to Zero) format, for example, and has a configuration illustrated in FIG. ing. A serial communication circuit 108 illustrated in FIG. 25 includes a reception operation unit 201, a transmission operation unit 202, a serial communication data register 203, a serial status register 204, and a serial control register 205.

  The reception operation unit 201 can sample and acquire the reception data transmitted by serial communication and transfer the acquired reception data to the serial communication data register 203 by the reception operation based on the setting in the predetermined bit of the serial control register 205. And Further, the reception operation unit 201 sets a predetermined bit of the serial status register 204 to “0” or “1” according to an operation state in the reception operation. The reception operation unit 201 is, for example, a reception shift register that stores received data sequentially transmitted by serial communication while shifting, a reception data register that temporarily stores reception data read from the reception shift register, and serial communication Is provided with an interrupt control circuit for controlling the generation of interrupt factors related to the reception operation.

  The transmission operation unit 202 generates transmission data corresponding to the read data from the serial communication data register 203 by a transmission operation based on a setting in a predetermined bit of the serial control register 205, and enables transmission by serial communication. Further, the transmission operation unit 202 sets a predetermined bit of the serial status register 204 to “0” or “1” according to an operation state in the transmission operation. The transmission operation unit 202 is, for example, a transmission data register that temporarily stores data read from the serial communication data register 203, a transmission shift register that stores and shifts transmission data that is sequentially transmitted by serial communication, It includes an interrupt control circuit that controls the generation of interrupt factors related to transmission operations in serial communication.

  The serial communication data register 203 stores the reception data acquired by the reception operation unit 201 or stores data to be supplied to the transmission operation unit 202, thereby communicating between the serial communication circuit 108 and the CPU 104. This is a circuit that enables data exchange, and is composed of, for example, 1 byte (8 bits).

  The serial status register 204 is a register for confirming the operation state in the serial communication circuit 108. For example, as shown in FIG. 26A, the serial status register 204 includes a first register SIST1 and a second register SIST2. Yes. The seventh bit [bit 7] of the first register SIST1 shown in FIG. 26A is a bit (TDRE) indicating a transmission data empty flag. For example, when data is transferred from the transmission data register included in the transmission operation unit 202 to the transmission shift register, the seventh bit [bit 7] of the first register SIST1 is set to “1” and turned on. .

  The sixth bit [bit 6] of the first register SIST1 shown in FIG. 26A is a bit (TC) indicating a transmission completion flag. For example, when transmission of data stored in the transmission shift register included in the transmission operation unit 202 is completed, the sixth bit [bit 6] of the first register SIST1 is set to “1” to be turned on. The fifth bit [bit 5] of the first register SIST1 is a bit (RDRF) indicating a reception data full flag. For example, when the data stored in the reception shift register included in the reception operation unit 201 is transferred to the reception data register, the fifth bit [bit 5] of the first register SIST1 is set to “1” and turned on. It becomes.

  The fourth bit [bit 4] of the first register SIST1 shown in FIG. 26A is a bit (IDLE) indicating an idle line detection flag. For example, when a predetermined idle line is detected in the reception data in the reception operation unit 201, the fourth bit [bit 4] of the first register SIST1 is set to “1” to be turned on. The third bit [bit 3] of the first register SIST1 is a bit (OR) indicating an overrun flag. For example, when an overrun is detected during the reception operation in the reception operation unit 201, the third bit [bit 3] of the first register SIST1 is set to “1” to be turned on.

  The second bit [bit 2] of the first register SIST1 shown in FIG. 26A is a bit (NF) indicating a noise error flag. For example, when a noise error is detected during the reception operation in the reception operation unit 201, the second bit [bit 2] of the first register SIST1 is set to “1” and is turned on. The first bit [bit 1] of the first register SIST1 is a bit (FE) indicating a framing error flag. For example, when a framing error is detected during the reception operation in the reception operation unit 201, the first bit [bit 1] of the first register SIST1 is set to “1” to be turned on.

  The 0th bit [bit 0] of the first register SIST1 shown in FIG. 26A is a bit (PF) indicating a parity error flag. For example, when the parity of the received data in the reception operation unit 201 does not match the parity bit in the received data, the 0th bit [bit 0] of the first register SIST1 is set to “1” and the ON state is set. Become. The 0th bit [bit 0] of the second register SIST2 is a bit (RAF) indicating a reception active flag. For example, when the reception operation unit 201 detects “0” as the start bit, the 0th bit [bit 0] of the second register SIST2 is set to “1”, and is turned on.

  The serial control register 205 is a register for setting the communication format in the serial communication circuit 108 and permission / prohibition of various error interrupt requests. For example, as shown in FIG. 26B, the first to third registers SICL1 To SICL3. The fourth bit [bit 4] of the first register SICL1 shown in FIG. 26B is a bit (M) for selecting a data length in serial communication. For example, when the fourth bit [bit 4] of the first register SICL1 is “0”, the start bit is set to 1 bit, the data bit is set to 8 bits, and the stop bit is set to 1 bit, and when it is “1”, the start bit is set Is 1 bit, the data bit is 9 bits, and the stop bit is 1 bit. The third bit [bit 3] of the first register SICL1 is a bit (WAKE) for selecting a wakeup method. For example, when the third bit [bit 3] of the first register SICL1 is “0”, the reception operation unit 201 is set to wake up by recognition of the idle line, and when it is “1”, the reception operation by recognition of the address mark is set. The wakeup of the unit 201 is set.

  The second bit [bit 2] of the first register SICL1 shown in FIG. 26B is a bit (ILT) for selecting an idle line detection method. For example, when the second bit [bit 2] of the first register SICL1 is “0”, the detection method is set after the start bit, and when it is “1”, the detection method is set after the stop bit. The The first bit [bit 1] of the first register SICL1 is a bit (PE) for setting whether or not to use the parity function. For example, when the first bit [bit 1] of the first register SICL1 is “0”, it is set not to use the parity function, and when it is “1”, the parity function is set to be used.

  The 0th bit [bit 0] of the first register SICL1 shown in FIG. 26B is a bit (PT) for selecting the type of parity when the parity function is used. For example, when the 0th bit [bit 0] of the first register SICL1 is “0”, it is set to use even parity, and when it is “1”, it is set to use odd parity.

  The seventh bit [bit 7] of the second register SICL2 shown in FIG. 26B is a bit (TIE) for setting permission / prohibition of the transmission interrupt request. For example, when the seventh bit [bit 7] of the second register SICL2 is “0”, the transmission interrupt request is prohibited, and when it is “1”, the transmission interrupt request is permitted. The sixth bit [bit 6] of the second register SICL2 is a bit (TCIE) for setting permission / prohibition of the transmission completion interrupt request. For example, when the sixth bit [bit 6] of the second register SICL2 is “0”, the transmission completion interrupt request is prohibited, and when it is “1”, the transmission completion interrupt request is permitted.

  The fifth bit [bit 5] of the second register SICL2 shown in FIG. 26B is a bit (RIE) for setting permission / prohibition of the reception interrupt request. For example, when the fifth bit [bit 5] of the second register SICL2 is “0”, the reception interrupt request is prohibited, and when it is “1”, the reception interrupt request is permitted. The fourth bit [bit 4] of the second register SICL2 is a bit (ILIE) for setting permission / prohibition of the idle line interrupt request. For example, when the fourth bit [bit 4] of the second register SICL2 is “0”, the idle line interrupt request is prohibited, and when it is “1”, the idle line interrupt request is permitted.

  The third bit [bit 3] of the second register SICL2 shown in FIG. 26B is a bit (TE) for setting whether to use the transmission operation unit 202 or not. For example, when the third bit [bit 3] of the second register SICL2 is “0”, it is set not to use the transmission operation unit 202, and when it is “1”, it is set to use the transmission operation unit 202. The The second bit [bit 2] of the second register SICL2 is a bit (RE) for setting whether to use the reception operation unit 201 or not. For example, when the second bit [bit 2] of the second register SICL2 is “0”, the reception operation unit 201 is set not to be used, and when it is “1”, the reception operation unit 201 is set to be used. The

  The first bit [bit 1] of the second register SICL2 shown in FIG. 26B is a bit (RWU) for setting whether to use reception wakeup. For example, when the first bit [bit 1] of the second register SICL2 is “0”, it is set not to use the reception wakeup, and when it is “1”, the reception wakeup is set to be used. The 0th bit [bit 0] of the second register SICL2 is a bit (SBK) for setting whether or not to use break code transmission. For example, when the 0th bit [bit 0] of the second register SICL2 is “0”, it is set not to use break code transmission, and when it is “1”, it is set to use break code transmission.

  The seventh bit [bit 7] of the third register SICL3 shown in FIG. 26B is a bit (R8) for storing the ninth bit in the received data when the data bit is set to nine bits. The sixth bit [bit 6] of the third register SICL3 is a bit (T8) for storing the ninth bit in the transmission data when the data bit is set to nine bits.

  The third bit [bit 3] of the third register SICL3 shown in FIG. 26B is a bit (ORIE) for setting permission / prohibition of an interrupt request at the time of an overrun error. For example, when the third bit [bit 3] of the third register SICL3 is “0”, an interrupt request at the time of an overrun error is prohibited, and when it is “1”, an interrupt request at the time of an overrun error is permitted. The second bit [bit 2] of the third register SICL3 is a bit (NEIE) for setting permission / prohibition of an interrupt request at the time of a noise error. For example, when the second bit [bit 2] of the third register SICL3 is “0”, an interrupt request at the time of noise error is prohibited, and when it is “1”, an interrupt request at the time of noise error is permitted.

  The first bit [bit 1] of the third register SICL3 shown in FIG. 26B is a bit (FEIE) for setting permission / prohibition of an interrupt request at the time of a framing error. For example, when the first bit [bit 1] of the third register SICL3 is “0”, an interrupt request at the time of a framing error is prohibited, and when it is “1”, an interrupt request at the time of a framing error is permitted. The 0th bit [bit 0] of the third register SICL3 is a bit (PEIE) for setting permission / prohibition of an interrupt request at the time of a parity error. For example, when the 0th bit [bit 0] of the third register SICL3 is “0”, an interrupt request at the time of a parity error is prohibited, and when it is “1”, an interrupt request at the time of a parity error is permitted.

  An external bus interface 109 provided in the game control microcomputer 100 shown in FIG. 10 is an interface circuit that performs direction control and drive control of an address bus, a data bus, and each control signal.

  As shown in FIG. 3, an effect control microcomputer 120 is mounted on the effect control board 12. The effect control board 12 may be equipped with a VDP (Video Display Processor) that generates image data in accordance with a drawing command from the effect control microcomputer 120. The effect control microcomputer 120 is a one-chip microcomputer, for example, and includes a ROM 121, a RAM 122, a CPU 123, and an I / O port 124. In addition, the production control microcomputer 120 may include a random number circuit that generates numerical data indicating random values independently of the CPU 123. A control signal transmitted from the main board 11 via the relay board 18 is input to the CPU 123 via a predetermined connector or an input port in the I / O port 124. A control signal for the audio control board 13 is output from the CPU 123 to the audio control board 13 via an output port in the I / O port 124 or a predetermined connector. A control signal for the lamp control board 14 is output from the CPU 123 to the lamp control board 14 via an output port in the I / O port or a predetermined connector.

  A scaler circuit for converting the resolution in the image data may be provided between the effect control board 12 and the image display device 5. In this case, the image data generated by the VDP mounted on the effect control board 12 according to the drawing command from the effect control microcomputer 120 is supplied to the image display device 5 after the resolution is converted by the scaler circuit. . As a specific example, the scaler circuit inputs the image data with the first resolution generated by the VDP and performs the following processing on one or both of the vertical direction and the horizontal direction. The converted image data is converted to a second resolution different from the first resolution.

  For example, when converting the resolution in the vertical direction, after performing upsampling at a first sample rate along the vertical direction of the input image data, a filtering process using a filter (for example, an FIR filter) prepared in advance. Apply. Thereafter, downsampling may be performed at a second sample rate corresponding to a predetermined scaling coefficient along the vertical direction. When converting the resolution in the horizontal direction, upsampling, filtering, and downsampling similar to those in the vertical direction may be performed along the horizontal direction of the input image data. As a specific example, when image data in VGA mode (640 × 480 pixels) is generated by VDP, the image data is converted into SXGA mode (1280 × 1024 pixels) or other modes by conversion processing in the scaler circuit. Can be converted to

  As shown in FIG. 3, a payout control microcomputer 150 and a switch circuit 161 are mounted on the payout control board 15. The switch circuit 161 is input with detection signals from various switches and sensors such as the full tank switch 26, the ball-out switch 27, the payout motor position sensor 71, the payout count switch 72, and the error release switch 73. The switch circuit 161 takes in these detection signals and transmits them to the payout control microcomputer 150.

  FIG. 27 is a diagram showing a configuration example of the payout control microcomputer 150 mounted on the payout control board 15. The payout control microcomputer 150 shown in FIG. 27 is a one-chip microcomputer similar to the game control microcomputer 100, for example, and includes a clock circuit 211, a reset / interrupt controller 212, a random number circuit 213, a CPU 214, and a ROM 215. A RAM 216, a timer circuit (PIT) 217, a serial communication circuit (SCI) 218, and an external bus interface 219. The random number circuit 213 only needs to have the same configuration as the random number circuit 103 included in the game control microcomputer 100, and the serial communication circuit 218 is similar to the serial communication circuit 108 included in the game control microcomputer 100. What is necessary is just to have the structure of. Further, the payout control microcomputer 150 may not be provided with the random number circuit 213.

  The ROM 215 provided in the payout control microcomputer 150 stores a payout control program. In the payout control microcomputer 150, for example, the CPU 214 reads out a payout control program stored in the ROM 215, and performs various processes based on the payout control command transmitted from the main board 11 and the communication result with the card unit 70. Is executed to control the game ball payout operation.

  In the RAM 216 provided in the payout control microcomputer 150, for example, a payout control data holding area 140 as shown in FIG. 28 is provided as an area for holding various data used for controlling the payout operation of the game ball. It has been. Further, at least a part of the RAM 216 is a backup RAM that is backed up by a backup power source created in the power supply substrate 10. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 216 is saved for a predetermined time. In this embodiment, it is assumed that the entire RAM 216 is a backup RAM that is backed up. The payout control data holding area 140 shown in FIG. 28 includes a payout control flag setting unit 141, a payout control timer setting unit 142, a payout control counter setting unit 143, and a payout control buffer setting unit 144.

  The payout control flag setting unit 141 includes, for example, a payout backup flag, a payout control process flag, a prize ball payout operation process flag, a ball lending operation process flag, a transmission settable flag, a transmission completion flag, a prize ball ACK transmission flag, and feedback reception. A flag, a reception confirmation flag, an error flag, and the like are provided.

  The payout control process flag indicates which process should be selected and executed in the payout operation control process (step S555 of FIG. 57 and FIG. 60) for controlling the payout operation of the game ball by the payout motor 51. The prize ball payout operation process flag indicates which process in the prize ball payout operation process (steps S663 and FIG. 63 in FIG. 60) executed to drive the payout motor 51 to pay out a game ball as a prize ball. Indicates whether to select and execute. The ball lending operation process flag selects which process is selected in the ball lending / dispensing operation processing (steps S664 and 66 in FIG. 60) executed to drive the payout motor 51 to pay out the game ball to be lent.・ Indicates whether to execute.

  The transmission setting enable flag indicates that the serial communication circuit 218 can be set for data transmission. For example, the transmission setting enable flag is set to an on state in response to an interrupt request from the serial communication circuit 218 when the transmission data is empty. The transmission completion flag indicates that data transmission has been completed in the serial communication circuit 218. For example, the transmission completion flag is set to an ON state in response to an interrupt request when transmission is completed from the serial communication circuit 218.

  The prize ball ACK transmission flag indicates that a prize ball ACK command is transmitted when a payout number designation command from the main board 11 is received. That is, the winning ball ACK transmission flag is set to the ON state when any of the first to third payout number designation commands is received. The feedback reception flag indicates whether or not an ACK feedback command from the main board 11 has been received. That is, the feedback reception flag is set to an on state when an ACK feedback command is received.

  The reception confirmation flag indicates that the reception of the ACK feedback command from the main board 11 is being confirmed after the award ball ACK command is transmitted to the main board 11. In other words, the reception confirmation flag is set to the ON state when the winning ball ACK command is transmitted, and then when the ACK feedback command is received or when a predetermined period has elapsed without receiving the ACK feedback command. Cleared and turned off.

  The error flag provided in the payout control flag setting unit 141 indicates that a predetermined error occurs based on the payout operation state of the game ball by driving the payout motor 51, the command transmission / reception state with the main board 11, and the like. It is configured to include a plurality of types of flags that are set to the ON state when detected. For example, error flags include main board communication error flag, large amount unpaid error flag, ball out error flag, card unit unconnected error flag, ball clogged error flag, full tank error flag, ball bite error flag, idle cut (back) It includes an error flag, an empty (front) error flag, a serial communication error flag, and the like.

  Here, the main board communication error flag is set to the ON state when an error occurs in the communication state with the main board 11. The large amount unpaid error flag is set to ON when the number of unpaid award balls that have not been paid out after the payout is instructed by the payout number designation command from the main board 11 exceeds a predetermined number. . The ball break error flag is set to the on state in response to the detection signal from the ball break switch 27 being turned on. The card unit unconnected error flag is set to ON when an error occurs in the communication state with the card unit 70. The ball clogging error flag is set to an on state, for example, when a detection signal from the payout count switch 72 is continuously on for a predetermined time (as a specific example, 0.5 seconds). . The full tank error flag is set to the on state in response to the detection signal from the full tank switch 26 being turned on continuously for a predetermined period or longer (as a specific example, 0.1 second). The For example, when the dispensing motor 51 is driven, the ball biting error flag is set to the on state in response to the dispensing motor position sensor 71 being continuously on or off for a predetermined time or more. For example, when the payout motor 51 is driven, the idle cut (back) error flag indicates that the game ball on the back side of the ball passage 90 (the passage of the game ball flowing in from the hole 85) in the payout device as shown in FIG. When the passage cannot be detected by the payout count switch 72, the on state is set. For example, when the payout motor 51 is driven, the idle cut (front) error flag indicates that the game ball on the front side of the ball passage 90 (the passage of the game ball flowing in from the hole 86) in the payout device as shown in FIG. When the passage cannot be detected by the payout count switch 72, the on state is set. The serial communication error flag is set to an on state in response to an error interrupt request from the serial communication circuit 218.

  The payout control timer setting unit 142 is provided with, for example, a communication control timer and a transmission operation control timer. The communication control timer is used for measuring various times in a communication operation for transmitting / receiving commands to / from the main board 11. The transmission operation control timer is used for measuring an elapsed time after transmission of communication data by serial communication by the serial communication circuit 218.

  The payout control counter setting unit 143 includes, for example, a prize ball unpaid counter, a ball lending unpaid counter, an initialization command reception count counter, a payout count counter, a payout operation failure count counter, a payout motor rotation counter, a command receive count counter, A command transmission waiting counter is provided.

  Based on the first to third payout number designation commands transmitted from the main board 11, the prize ball unpaid counter stores the number of game balls to be paid out as prize balls in an updatable manner as a prize ball unpaid count value. Therefore, it is for counting. The ball lending unpaid counter is for counting the number of game balls to be paid out as a lending ball based on a ball lending request from the card unit 70 by storing it as a ball lending unpaid count value in an updatable manner. It is. The initialization command reception number counter is used for counting by storing the number of times of receiving the payout initialization command from the main board 11 in an updatable manner as the initialization command reception number count value. The payout number counter is used for counting by storing the number of game balls detected by the payout count switch 72 by driving the payout motor 51 in an updatable manner as a payout number count value. The payout operation failure frequency counter counts the number of times when a payout operation failure is detected when the payout motor 51 is driven to pay out a game ball by storing it updatable as a payout operation failure frequency count value. Is for. The payout motor rotation counter stores the payout motor rotation count value in accordance with the number of game balls to be paid out as prize balls or rental balls in an updatable manner, and sets the drive amount (rotation amount) of the payout motor 51 Used.

  The command reception number counter is for counting the number of commands received from the main board 11 in an identifiable manner. The command transmission waiting counter is used to count the number of commands waiting to be transmitted to the main board 11 in an identifiable manner.

  The payout control buffer setting unit 144 is provided with a payout checksum buffer, a reception command buffer, a transmission command buffer, and the like, for example. The payout checksum buffer is for storing a checksum calculated using stored data in a specific area of the RAM 216 when power supply to the pachinko gaming machine 1 is stopped. The reception command buffer is used for temporarily storing commands received from the main board 11 by the payout control board 15. The transmission command buffer is used to temporarily store a command transmitted from the payout control board 15 to the main board 11.

  Next, the operation (action) of the pachinko gaming machine 1 in this embodiment will be described. In the main board 11, when the power supply from the power supply board 10 is started and the reset signal to the game control microcomputer 100 becomes high level (off state), the game control microcomputer 100 is activated, A game control main process as shown in the flowcharts of FIGS. 29 and 30 is executed. Note that each process described below is executed by the CPU 104 provided in the game control microcomputer 100. An interrupt request based on various interrupt factors generated by the timer circuit 107 and the serial communication circuit 108 provided in the game control microcomputer 100 is for causing the CPU 104 to execute predetermined interrupt processing. The concept including the CPU 104 and various circuits other than the CPU 104 is sometimes referred to as a game control microcomputer 100. When the game control main process shown in FIG. 29 and FIG. 30 is started, the game control microcomputer 100 first sets the interrupt prohibition (step S1 in FIG. 29) and sets the interrupt mode (step S2). . For example, in step S2, the value (1 byte) of the specific register (I register) of the game control microcomputer 100 and the interrupt vector (1 byte: the least significant bit is “0”) output by the built-in device are synthesized. This sets an interrupt mode for maskable interrupts in which interrupt addresses are generated. When an interrupt that can be masked occurs, the microcomputer 100 for game control is automatically set to be in an interrupt disabled state, and the contents of the program counter may be saved in the stack.

  Subsequently, settings relating to the stack pointer, such as setting of a stack pointer designation address, are performed (step S3). The built-in device register is set (initialized) (step S4). For example, when the game control microcomputer 100 has a built-in CTC (counter / timer) and PIO (parallel input / output port), the processing in step S4 is executed, whereby a built-in device (built-in peripheral circuit). CTC or PIO setting (initialization) or the like may be performed.

  After executing the process of step S4, for example, by checking the state of a predetermined bit at the input port provided in the gaming control microcomputer 100, it is determined whether or not the power-off signal is in an off state. (Step S5). When power supply to the pachinko gaming machine 1 is started, various power supply voltages such as VCC gradually increase and reach a specified value. In the process of step S5, it is confirmed that the power-off signal is not output and is in an off state (high level). Here, the game control microcomputer 100 may confirm the state of the power-off signal only once through the input port, but may confirm the state of the power-off signal a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. In addition, it is possible to check twice and check again when the check results do not match.

  When the power-off signal is in the ON state in step S5 (step S5; No), after waiting for a predetermined time (for example, 0.1 second) to elapse (step S6), the process returns to step S5, It is determined again whether or not the power-off signal is off. Thereby, the microcomputer 100 for game control can confirm that the power supply voltage was stabilized. When the power-off signal is off in step S5 (step S5; Yes), for example, a clear signal is generated by checking the state of a predetermined bit in the input port provided in the game control microcomputer 100. It is determined whether or not it is in an on state (step S7). At this time, if the clear signal is on (step S7; Yes), for example, a clear flag provided in the game control flag setting unit 133 is set to the on state (step S8). On the other hand, when the clear signal is in the off state (step S7; No), the process of step S8 is skipped and the clear flag remains in the off state.

  Here, the game control microcomputer 100 may confirm the state of the clear signal only once through the input port, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed once that the state of the clear signal is OFF, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 seconds) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or a plurality of times. In addition, it is possible to check twice and check again when the check results do not match.

  Thereafter, a delay process for delaying the start timing of the game control process for controlling the progress of the game by executing the software is set (step S9). As a specific example, an initialization weight number designation value is set in a wait counter provided in the game control counter setting unit 135. Subsequently, the delay process based on the setting in step S9 is started, and the setting relating to the execution of the delay process is updated (step S10), for example, the count value in the wait counter is decremented by one. Then, for example, it is determined whether or not a predetermined delay time has elapsed by determining whether or not the count value in the wait counter has reached a predetermined delay end determination value (step S11). Here, the data indicating the delay end determination value may be stored in advance in the ROM 105 or the like. For example, the delay end determination value is from when the game control process becomes executable until at least execution of various processes for payout control by the payout control microcomputer 150 mounted on the payout control board 15 is started. A predetermined reference value may be used so that the delay time becomes longer than the time.

  When the delay time has not elapsed in step S11 (step S11; No), the processing returns to step S10, and when the delay time has elapsed (step S11; Yes), the RAM 106 is set to be accessible (step S11; Yes). Step S12). Subsequently, the game control microcomputer 100 determines whether or not the clear flag is on (step S13). When the clear flag is off (step S13; No), data check of the RAM 106 is performed to determine whether or not the check result is normal (step S14). In the process of step S14, for example, a checksum is calculated using data stored in a specific area of the RAM 106, and the calculated checksum is compared with the checksum stored in the main checksum buffer. Here, the main checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison results do not match, the data in the specific area of the RAM 106 is different from the data at the time of stopping the power supply, and therefore it is determined that the check result is not normal.

  When the check result in step S14 is normal (step S14; Yes), it is determined whether or not the main backup flag provided in the game control flag setting unit 133 is on (step S15). The state of the main backup flag is set in the game control flag setting unit 133 when the power supply is stopped. The main backup flag setting location is backed up by the backup power source, so that the state of the main backup flag is saved even when the power supply is stopped. In step S15, for example, if “55H” is set in the game control flag setting unit 133 as the value of the main backup flag, it is determined that there is a backup (ON state). On the other hand, if a value other than “55H” is set, it is determined that there is no backup (OFF state). Note that the determination as to whether or not the main backup flag is turned on as in step S15 is performed prior to the determination of the check result as in step S14, and the data check of the RAM 106 is performed when the main backup flag is turned on. You may make it determine whether a result is normal.

  If the main backup flag is on in step S15 (step S15; Yes), the main backup flag is cleared and turned off (step S16), and then the internal power supply of the game control microcomputer 100 is supplied. The setting at the time of restoration for returning to the state when stopped is performed (step S17). As a specific example, in the processing of step S17, the start address of the backup setting table stored in the ROM 105 is set as a pointer, and the contents of the backup setting table are sequentially set in the work area in the RAM 106. Here, the work area of the RAM 106 is backed up by a backup power source, and initialization data for an area that may be initialized among the work areas may be set in the backup time setting table. When the process of step S17 is executed, a setting for transmitting a recovery notification command to the effect control board 12 is performed (step S18). As a specific example, in the process of step S18, the start address of the backup command transmission table stored in the ROM 106 is set as a pointer, and control data for command transmission is played based on the contents of the backup command transmission table. The restoration notification command is transmitted from the main board 11 to the effect control board 12 by setting it in the effect transmission command buffer included in the transmission command buffer of the control buffer setting unit 136.

  Further, when the clear flag is on in step S13 (step S13; Yes), when the check result is not normal in step S14 (step S14; No), or the main backup flag is off in step S15. If there is (step S15; No), the RAM 106 is initialized (step S19). Subsequent to the processing in step S19, settings at the time of initialization for setting the internal state of the game control microcomputer 100 to an initial state are performed (step S20). As a specific example, in the processing of step S20, the start address of the initialization setting table stored in the ROM 105 is set as a pointer, and the contents of the initialization setting table are sequentially set in the work area in the RAM 106. . In step S20, a predetermined initial count value (eg, “200”) is set in the command transmission number counter provided in the game control counter setting unit 135. When the processes of steps S19 and S20 are executed, the setting for transmitting the initialization notification command to the effect control board 12 (step S21) and the payment initialization command to the payout control board 15 are transmitted. Are set (step S22). As a specific example, in the process of step S21, the head address of the initialization effect presentation command transmission table stored in the ROM 105 is set as a pointer, and the command transmission is performed based on the contents of the initialization presentation effect command transmission table. An initialization notification command is transmitted from the main board 11 to the effect control board 12 by setting control data in an effect transmission command buffer included in the transmission command buffer of the game control buffer setting unit 136. In the process of step S22, the start address of the payout command transmission table at initialization stored in the ROM 105 is set as a pointer, and control data for command transmission is played based on the contents of the payout command transmission table at initialization. By setting it in the payout transmission command buffer 192 included in the transmission command buffer of the control buffer setting unit 136, the main board 11 transmits a payout initialization command to the payout control board 15.

  After executing the processing of step S18 or step S22, a timer interrupt is generated every predetermined time (for example, 2 milliseconds) by setting a register of the timer circuit 107 provided in the gaming control microcomputer 100, for example. Next, internal setting of the game control microcomputer 100 is performed (step S23). Thereafter, the CPU 104 reads the fourth and third bits [bits 4-3] of the first random number initial setting data (KRSS1) stored in the ROM 105 (step S24 in FIG. 30), and based on the read value, the random number is read. Initial setting of the generation operation is performed (step S25). FIG. 31 is an explanatory diagram showing an example of the processing content executed in step S25.

  When the read value in step S24 is “00”, the process proceeds to step S26 without performing any process as the process in step S25. At this time, as a process in step S25, a process for stopping the generation operation of both the 12-bit random number and the 16-bit random number in the random number circuit 103 may be executed. When the read value in step S24 is “01”, a 12-bit random number initial setting process is executed as the process in step S25. At this time, processing for stopping the generation operation of the 16-bit random number in the random number circuit 103 may be executed. When the read value in step S24 is “10”, 16-bit random number initial setting processing is executed as processing in step S25. At this time, a process for stopping the generation operation of the 12-bit random number in the random number circuit 103 may be executed. When the read value in step S24 is “11”, a 12-bit random number initial setting process and a 16-bit random number initial setting process are executed as the process in step S25.

  Subsequent to the process of step S25, a serial communication initial setting process is executed as a process for initial setting of the serial communication operation (step S26). Thereafter, an interrupt initial setting process is executed as a process for performing an initial setting related to the interrupt process executed based on the interrupt request (step S27). Then, the game control microcomputer 100 sets the interrupt permitted state (step S28) and waits for the occurrence of various interrupts. At this time, it is determined whether or not the power-off signal has been turned on (whether or not it has been output) (step S29). If it is off (step S29; No), the generation of various interrupts is awaited. When the power-off signal is turned on (step S29; Yes), the main-side power-off process is executed (step S30), and then a predetermined loop process is executed to control the game by stopping the power supply. Wait until the microcomputer 100 stops operating. In the process of step S29, the state of the power-off signal may be confirmed only once through the input port, but the state of the power-off signal may be confirmed a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. In addition, it is possible to check twice and check again when the check results do not match. In this way, when checking the state of the power-off signal a plurality of times, for example, when starting a confirmation operation or when the first confirmation result and the second confirmation result are compared and there is a mismatch, Retriggering is performed to clear the WDT (watchdog timer) built in the control microcomputer 100. When the retrigger does not occur within a predetermined time due to some cause (for example, program runaway), a user reset is generated based on a timeout signal output from the WDT, and the reset / interrupt controller 102, CPU 104, timer circuit After initializing each circuit such as 107 and the serial communication circuit 108, execution of the user program may be started from an address indicated by a predetermined vector table to perform automatic recovery.

  FIG. 32 is a flowchart illustrating an example of a 12-bit random number initial setting process included in the process executed in step S25. In the 12-bit random number initial setting process shown in FIG. 32, in the game control microcomputer 100, first, the CPU 104 reads the seventh bit [bit 7] of the second random number initial setting data (KRSS2) stored in the ROM 105 ( In step S101), it is determined whether or not the read value is “0” (step S102). At this time, if the read value in step S101 is “0” (step S102; Yes), the start value for the first round for generating a 12-bit random number in the random number circuit 103 is “001h” which is a default value. Is determined to be set (step S103). On the other hand, if the read value in step S101 is “1” (step S102; No), the start value for the first round for generating a 12-bit random number in the random number circuit 103 is set for each game control microcomputer 100. A determination is made based on the ID number that is the assigned unique identification number (step S104). Here, in the process of step S104, the ID number of the game control microcomputer 100 may be set to the start value of the first round for generating a 12-bit random number as it is. Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for the first round for generating a 12-bit random number. . For example, an operation for performing a predetermined scramble process on the ID number of the game control microcomputer 100 or an operation such as addition / subtraction / multiplication / division using the ID number is performed to use the calculated value. That's fine.

  The start value determined in step S103 or step S104 is input to an initial value setting circuit 172A included in the random number circuit 103, and is set as a start value for the first round for generating a 12-bit random number. Note that the processing in step S103 and step S104 may be executed by the initial value setting circuit 172A included in the random number circuit 103. For example, when the CPU 104 determines that the read value is “0” in step S <b> 102, a predetermined first initial value setting signal is sent to the random number circuit 103. When the random number circuit 103 receives the first initial value setting signal from the CPU 104, the initial value setting circuit 172A reads data stored in a predetermined register and sets the read value in the random number generation circuit 173A. Is set to the default value “001h” (processing corresponding to step S103). On the other hand, when the CPU 104 determines that the read value is “1” in step S102, the CPU 104 sends a second initial value setting signal different from the first initial value setting signal to the random number circuit 103. When the random number circuit 103 receives the first initial value setting signal from the CPU 104, the initial value setting circuit 172A selects data generated based on the ID number stored in a predetermined register and generates the selected data as a random number. The start value for the first round for generating a 12-bit random number is set to a value based on an ID number that is a unique identification number assigned to each game control microcomputer 100 by setting the circuit 173A. (Processing corresponding to step S104). Here, as the ID number stored in the predetermined register, only a numerical value of a digit that is equal to or less than the maximum value of the 12-bit random number may be extracted and set in the random number generation circuit 173A. Alternatively, an ID number stored in a predetermined register is input to an arithmetic circuit (for example, a multiplier circuit) built in the initial value setting circuit 172A, so that a predetermined calculation using a numerical value in each digit of the ID number is performed, for example. Data that is executed and indicates a value calculated by this calculation may be set in the random number generation circuit 173A. Further, the CPU 104 may directly control the operation of the initial value setting circuit 172A to execute the processing corresponding to steps S103 and S104. For example, the CPU 104 is provided inside or outside the random number circuit 103 for initial value setting control. Then, the operation of the initial value setting circuit 172A may be indirectly controlled by setting control data corresponding to the read value in step S101 in a predetermined register that can be referred to by the initial value setting circuit 172A. . When the CPU 104 sets control data in the initial value setting control register, for example, when the random number circuit 103 starts generating a 12-bit random number, the initial value setting circuit 172A is stored in the initial value setting register. The initial value setting operation according to the control data is performed to generate a start value for the first round corresponding to the read value in step S101 and set it in the random number generation circuit 173A. be able to.

  After executing one of the processes in steps S103 and S104, the CPU 104 reads out the sixth and fifth bits [bits 6-5] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S105). ) Based on the read value, the selection operation is set in the selector 174A provided in the random number circuit 103 as a selector for a 12-bit random number (step S106). For example, when the read value in step S105 is “00”, the output signal of the selector 174A is set to be always off. As a result, a third method that does not change the permutation, which is the update order of the 12-bit random number, is set. When the read value in step S105 is “10”, the selector 174A is set to select and output the output signal from the ARSC 175A. At this time, the selector 174A only needs to output the output signal from the ARSC 175A in synchronization with the random number loop signal RIJ1 output from the random number generation circuit 173A. As a result, a second method is set that allows the user program to change the permutation of the 12-bit random number after the second round. When the read value in step S105 is “11”, the selector 174A is set to select and output the random number loop signal RIJ1 output from the random number generation circuit 173A. As a result, the first method for automatically changing the permutation in the second and subsequent rounds of the 12-bit random number is set. In the process of step S106, the CPU 104 may directly set the signal output operation of the selector 174A to output a signal corresponding to the read value in step S105. The signal output operation of the selector 174A may be indirectly controlled by setting control data corresponding to the read value in step S105 in a predetermined register that is provided outside and can be referred to by the selector 174A. . When the control data is set in the register in step S106, for example, when the random number loop signal RIJ1 is output from the random number generation circuit 173A, the selector 174A refers to the control data stored in the register, and the control data By performing the signal output operation according to this, a signal corresponding to the setting in step S106 can be output to the random number sequence change circuit 176A, and the permutation for generating the 12-bit random number can be changed or held.

  Following the processing of step S106, the CPU 104 reads the 12-bit random number maximum value (KRMS) stored in the ROM 105 (step S107), and is the read value within a range that can be set as the maximum value for the 12-bit random number? It is determined whether or not (step S108). For example, if the maximum value of the 12-bit random number can be arbitrarily set within the range from “256” to “4095”, is the read value at step S107 within the range from “256” to “4095”? Determine whether or not.

  When it is determined in step S108 that the read value is within a settable range (step S108; Yes), the read value in step S107 is set in the maximum value comparison circuit 177A included in the random number circuit 103 (step S108). S109). On the other hand, when it is determined in step S108 that the read value is not within the settable range (step S108; No), a predetermined value within the range that can be set as the maximum value for the 12-bit random number is set as the maximum value. It is reset and set in the maximum value comparison circuit 177A included in the random number circuit 103 (step S110). For example, when the read value in step S107 is not within the range from “256” to “4095”, the value “4095” within the range may be reset as the maximum value. In the processing of steps S109 and S110, the CPU 104 may directly control the operation of the maximum value comparison circuit 177A to set the maximum value for 12-bit random numbers. For example, it is provided inside or outside the random number circuit 103. Then, the operation of the maximum value comparison circuit 177A may be indirectly controlled by setting control data indicating the maximum value for 12-bit random numbers in a predetermined register that can be referred to by the maximum value comparison circuit 177A. . When the control data is set in the register in steps S109 and S110, for example, the maximum value comparison circuit 177A is stored in the register every time the value of the numerical data sequence R1 output from the random number sequence change circuit 176A is updated. By referring to the control data and comparing the maximum value for the 12-bit random number indicated by the control data with the numerical data output from the random number sequence changing circuit 176A, only the numerical data that is less than or equal to the maximum value is a random value. It can be output as a 12-bit random value stored in the register 181A.

  After executing one of the processes of steps S109 and S110, the CPU 104 reads the first and 0th bits [bits 1-0] of the first random number initial setting data (KRSS1) stored in the ROM 105 (step S111). ). Then, based on the read value in step S111, initial setting is made regarding the start value after the second round in the 12-bit random number (step S112). As a specific example, in the process of step S112, the read data indicating the first and 0th bits [bits 1-0] of the first random number initial setting data (KRSS1) read by the CPU 104 from the ROM 105 is stored in the random number circuit 103 or Setting related to the start value for the second and subsequent rounds in the 12-bit random number while the CPU 104 is executing the timer interrupt processing for game control by storing in a predetermined register built in the CPU 104 or a predetermined area of the RAM 106 It is only necessary to perform an initial setting so that can be referred to.

  FIG. 33 is a flowchart illustrating an example of a 16-bit random number initial setting process included in the process executed in step S25. In the 16-bit random number initial setting process shown in FIG. 33, in the game control microcomputer 100, first, the CPU 104 reads the second bit [bit 2] of the first random number initial setting data (KRSS1) stored in the ROM 105 ( In step S121), operation setting in the clock signal output circuit 171 provided in the random number circuit 103 is performed based on the read value (step S122). For example, when the read value in step S121 is “0”, the clock signal S1 output from the clock signal output circuit 171 is output in the same cycle as the internal system clock CLK input to the clock input terminal of the clock signal output circuit 171. Set to be a clock signal. When the read value in step S121 is “1”, the clock signal S1 output from the clock signal output circuit 171 is 16 times the internal system clock CLK input to the clock input terminal of the clock signal output circuit 171. The clock signal is set to have a period. In the process of step S122, the CPU 104 may directly set the operation of the clock signal output circuit 171 to output the clock signal corresponding to the read value in step S121. The operation of the clock signal output circuit 171 is indirectly controlled by setting control data corresponding to the read value in step S121 in a predetermined register which is provided inside or outside and can be referred to by the clock signal output circuit 171. You may make it do. When the control data is set in the register in step S122, for example, the clock signal output circuit 171 refers to the control data stored in the register when the random number circuit 103 starts generating the 16-bit random number, By performing a clock signal output operation in accordance with the control data, a clock signal according to the setting in step S121 can be output.

  Subsequent to step S122, the CPU 104 reads the fourth bit [bit 4] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S123), and whether or not the read value is “0”. Is determined (step S124). At this time, if the read value in step S123 is “0” (step S124; Yes), the start value for the first round for generating a 16-bit random number in the random number circuit 103 is the default value “0001h”. Is determined to be set (step S125). On the other hand, if the read value in step S123 is “1” (step S124; No), the start value for the first round for generating a 16-bit random number in the random number circuit 103 is set for each game control microcomputer 100. A determination is made based on the ID number that is the assigned unique identification number (step S126). Here, in the process of step S126, the ID number of the game control microcomputer 100 may be set to the start value for the first round for generating a 16-bit random number as it is. Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for the first round for generating a 16-bit random number. . For example, an operation for performing a predetermined scramble process on the ID number of the game control microcomputer 100 or an operation such as addition / subtraction / multiplication / division using the ID number is performed to use the calculated value. That's fine.

  The start value determined in step S125 or step S126 is input to an initial value setting circuit 172B included in the random number circuit 103, and is set as a start value for the first round for generating a 16-bit random number. Note that the processing of step S125 and step S126 may be executed by the initial value setting circuit 172B included in the random number circuit 103. For example, when the CPU 104 determines in step S 124 that the read value is “0”, it sends a predetermined third initial value setting signal to the random number circuit 103. When the random number circuit 103 receives the third initial value setting signal from the CPU 104, the initial value setting circuit 172B reads data stored in a predetermined register, sets the read value in the random number generation circuit 173B, and the like. Is set to the default value “0001h” (processing corresponding to step S125). On the other hand, when the CPU 104 determines that the read value is “1” in step S <b> 124, it sends a fourth initial value setting signal different from the third initial value setting signal to the random number circuit 103. When the random number circuit 103 receives the fourth initial value setting signal from the CPU 104, the initial value setting circuit 172B selects data generated based on the ID number stored in a predetermined register, and generates the selected data as a random number. The start value for the first round for generating a 16-bit random number is set to a value based on an ID number that is a unique identification number assigned to each game control microcomputer 100 by setting the circuit 173B. (Processing corresponding to step S126). Here, the ID number stored in the predetermined register may be set in the random number generation circuit 173B by extracting only the numerical value of the digit that is equal to or less than the maximum value of the 16-bit random number. Alternatively, the ID number stored in the predetermined register is input to an arithmetic circuit (for example, a multiplier circuit) built in the initial value setting circuit 172B, so that a predetermined calculation using a numerical value in each digit of the ID number is performed. Data that is executed and indicates a value calculated by this calculation may be set in the random number generation circuit 173B. Further, the CPU 104 may directly control the operation of the initial value setting circuit 172B to execute processing corresponding to steps S125 and S126. For example, the CPU 104 may be provided inside or outside the random number circuit 103 for initial value setting control. Then, the operation of the initial value setting circuit 172B may be indirectly controlled by setting control data corresponding to the read value in step S123 in a predetermined register that can be referred to by the initial value setting circuit 172B. . When the CPU 104 sets control data in the initial value setting control register, for example, when the random number circuit 103 starts generating a 16-bit random number, the initial value setting circuit 172B is stored in the initial value setting register. The initial value setting operation according to the control data is performed, and the start value for the first round corresponding to the read value in step S123 is generated and set in the random number generation circuit 173B. be able to.

  After executing one of the processes in steps S125 and S126, the CPU 104 reads the first and 0th bits [bits 1-0] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S127). Based on the read value, a selection operation is set in the selector 174B provided in the random number circuit 103 as a selector for a 16-bit random number (step S128). For example, when the read value in step S127 is “00”, the output signal of the selector 174B is set to be always in the off state. As a result, a third method that does not change the permutation that is the update order of the 16-bit random numbers is set. When the read value in step S127 is “10”, the selector 174B is set to select and output the output signal from the BRSC 175B. At this time, the selector 174B only needs to output the output signal from the BRSC 175B in synchronization with the random number round signal RIJ2 output from the random number generation circuit 173B. As a result, a second method is set that allows the user program to change the permutation in the second and subsequent rounds of the 16-bit random number. Further, when the read value in step S127 is “11”, the selector 174B is set to select and output the random number loop signal RIJ2 output from the random number generation circuit 173B. As a result, the first method for automatically changing the permutation in the second and subsequent rounds of the 16-bit random number is set. In the process of step S128, the CPU 104 may directly set the signal output operation of the selector 174B to output a signal corresponding to the read value in step S127. The signal output operation of the selector 174B may be indirectly controlled by setting control data corresponding to the read value in step S127 in a predetermined register that is provided outside and can be referred to by the selector 174B. . When the control data is set in the register in step S127, for example, when the random number round trip signal RIJ2 is output from the random number generation circuit 173B, the selector 174B refers to the control data stored in the register, and the control data By performing the signal output operation according to this, a signal corresponding to the setting in step S128 can be output to the random number sequence change circuit 176B, and the permutation for generating a 16-bit random number can be changed or held.

  Following the process of step S128, the CPU 104 reads the maximum 16-bit random number (KRXS) stored in the ROM 105 (step S129), and is the read value within a range that can be set as the maximum value for the 16-bit random number? It is determined whether or not (step S130). For example, when the maximum value of a 16-bit random number can be arbitrarily set within the range from “512” to “65535”, is the read value at step S129 within the range from “512” to “65535”? Determine whether or not.

  When it is determined in step S130 that the read value is within the settable range (step S130; Yes), the read value in step S129 is set in the maximum value comparison circuit 177B included in the random number circuit 103 (step S130). S131). On the other hand, when it is determined in step S130 that the read value is not within the settable range (step S130; No), a predetermined value within the range that can be set as the maximum value for 16-bit random numbers is set as the maximum value. It is reset and set in the maximum value comparison circuit 177B included in the random number circuit 103 (step S132). For example, when the read value in step S129 is not within the range from “512” to “65535”, “65535” that is the value within the range may be reset as the maximum value. In the processing of steps S131 and S132, the CPU 104 may directly control the operation of the maximum value comparison circuit 177B to set the maximum value for 16-bit random numbers. For example, it is provided inside or outside the random number circuit 103. Then, the operation of the maximum value comparison circuit 177B may be indirectly controlled by setting control data indicating the maximum value for 16-bit random numbers in a predetermined register that can be referred to by the maximum value comparison circuit 177B. . When control data is set in the register in steps S131 and S132, for example, the maximum value comparison circuit 177B is stored in the register every time the value of the numerical data sequence R2 output from the random number sequence change circuit 176B is updated. By referring to the control data and comparing the maximum value for the 16-bit random number indicated by the control data with the numerical data output from the random number sequence change circuit 176B, only the numerical data that is less than or equal to the maximum value is a random value. It can be output as a 16-bit random value stored in the register 181B.

  After executing one of the processes in steps S131 and S132, the CPU 104 reads the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S133). ). Then, based on the read value in step S133, initial setting is made regarding the start value after the second round in the 16-bit random number (step S134). As a specific example, in the process of step S134, the read data indicating the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) read by the CPU 104 from the ROM 105 is stored in the random number circuit 103 or Setting related to the start value for the second and subsequent rounds in the 16-bit random number while the CPU 104 is executing a timer interrupt process for game control by storing in a predetermined register built in the CPU 104 or a predetermined area of the RAM 106 It suffices if an initial setting is made so that reference can be made.

  FIG. 34 is an explanatory diagram showing an example of the contents of the serial communication initial setting process executed in step S26 shown in FIG. In this serial communication initial setting process, first, the CPU 104 reads the first and second serial communication initial setting data (KSCM1 and KSCM2) stored in the ROM 105, and the serial control register provided in the serial communication circuit 108 based on the read value. 205 is set.

  For example, when the fifth bit [bit 5] of the first serial communication initial setting data (KSCM1) is “0”, the TIE that is the seventh bit [bit 7] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, TIE is set to “1”. When the fourth bit [bit 4] of the first serial communication initial setting data (KSCM1) is “0”, TCIE which is the sixth bit [bit 6] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, TCIE is set to “1”. When the third bit [bit 3] of the first serial communication initial setting data (KSCM1) is “0”, the RIE that is the fifth bit [bit 5] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, RIE is set to “1”.

  When the second bit [bit 2] of the first serial communication initial setting data (KSCM1) is “0”, ILIE which is the fourth bit [bit 4] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, ILIE is set to “1”. When the first bit [bit 1] of the first serial communication initial setting data (KSCM1) is “0”, the third bit [bit 3] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when “1”, TE is set to “1”. When the 0th bit [bit 0] of the first serial communication initial setting data (KSCM1) is “0”, the second bit [bit 2] of the second register SICL2 in the serial control register 205 is set to “0”. On the other hand, when “1”, RE is set to “1”.

  When the third bit [bit 3] of the second serial communication initial setting data (KSCM2) is “0”, the ORIE that is the third bit [bit 3] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, ORIE is set to “1”. When the second bit [bit 2] of the second serial communication initial setting data (KSCM2) is “0”, NEIE which is the second bit [bit 2] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, if it is “1”, NEIE is set to “1”. When the first bit [bit 1] of the second serial communication initial setting data (KSCM2) is “0”, the FEIE that is the first bit [bit 1] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, FEIE is set to “1”. When the 0th bit [bit 0] of the second serial communication initial setting data (KSCM2) is “0”, the PEIE which is the 0th bit [bit 0] of the third register SICL3 in the serial control register 205 is set to “0”. On the other hand, when it is “1”, PEIE is set to “1”.

  FIG. 35 is a flowchart showing an example of the interrupt initial setting process executed in step S27 shown in FIG. In this interrupt initial setting process, the CPU 104 reads the highest priority interrupt setting (KHPR) stored in the ROM 105 (step S141), and sets the highest priority interrupt based on the read value (step S142). For example, in the process of step S142, it is specified whether the read value in step S141 is “00h” to “07h”, and the factor of the I class interrupt (IRQ) corresponding to the specified value is the highest priority. Set the interrupt vector so that it becomes a high interrupt factor.

  FIG. 36 is a flowchart showing an example of the main-side power-off process executed in step S30 shown in FIG. In the main-side power-off process shown in FIG. 36, in the game control microcomputer 100, first, the CPU 104 sets the interrupt prohibition (step S151). Subsequently, for example, the CPU 104 initializes the settings relating to the drive control of the solenoids 81 and 82 by setting clear data in a predetermined bit of an output port provided in the game control microcomputer 100 (step S152). At this time, clear data may be set for an output port to be cleared in addition to a predetermined bit of the output port. After executing the process of step S152, for example, check data is created by calculating the checksum using the data stored in the specific area of the RAM 106 (step S153) and provided in the game control flag setting unit 133. The main backup flag is set to the on state (step S154). The check data created at this time is stored in a predetermined area of the RAM 106 such as a main checksum buffer provided in the game control buffer setting unit 136, for example. Then, in the game control microcomputer 100, for example, the CPU 104 prohibits access to the RAM 106 by setting an access prohibition value in a predetermined RAM access register (step S155). As a result, even if a program runaway occurs with the stop of power supply, the stored contents of the RAM 106 can be prevented from being damaged. After such main-side power-off processing is executed, a standby state (loop processing) is entered.

  In addition, after executing the main-side power-off process as shown in FIG. 36 in step S30, for example, it is periodically determined whether or not the power-off signal is turned off. However, the processing may be resumed in response to the instantaneous interruption by proceeding again from step S1 shown in FIG. Alternatively, after executing the main-side power-off process as shown in FIG. 36 in step S30, for example, a predetermined time elapses that is longer than the time required until the time-out signal is output from WDT. Alternatively, when the power supply from the power supply substrate 10 is continued, the CPU 104 may restart the process in response to the instantaneous interruption by proceeding again from step S1 shown in FIG.

  After the interrupt enabled state is obtained by executing the process of step S28 shown in FIG. 30, for example, when a plurality of interrupt factors occur simultaneously in the timer circuit 107, the serial communication circuit 108, etc., step S142 shown in FIG. Based on the setting in, the reset / interrupt controller 102 accepts an interrupt factor having a high priority. The interrupt factor accepted by the reset / interrupt controller 102 is notified to the CPU 104, and the CPU 104 executes a program having the vector address of the interrupt factor as the head address, whereby interrupt processing based on each interrupt factor is started. As a result, when a plurality of interrupt factors occur simultaneously, for example, the default priority as shown in FIG. 19B or the priority changed by the highest priority interrupt setting (KHPR) stored in the ROM 105 is used. The interrupt processing based on the interrupt factor having the higher priority is executed with higher priority than the interrupt processing based on the interrupt factor having the lower priority.

  For example, when the highest priority interrupt setting (KHPR) stored in the ROM 105 is “06h”, the default priority order as shown in FIG. 19B is set by the setting in step S142 shown in FIG. As shown in FIG. 19A, the priority is changed so that the reception interrupt request from the serial communication circuit 108 has the highest priority. In this case, the interrupt process based on the reception interrupt request from the serial communication circuit 108 is executed with higher priority than the interrupt process based on the error interrupt request from the serial communication circuit 108. As shown in FIG. 19B, at the time of default, the interrupt process based on the interrupt request from the timer circuit 107 is executed with priority over the interrupt process based on the interrupt request from the serial communication circuit 108. It is set. On the other hand, when the highest priority interrupt setting (KHPR) stored in the ROM 105 is “05h”, “06h”, or “07h”, each is based on an error interrupt request from the serial communication circuit 108. The interrupt process, the interrupt process based on the reception interrupt request, and the interrupt process based on the transmission interrupt request are executed with higher priority than the interrupt process based on the interrupt request from the timer circuit 107.

  FIG. 37 is a flowchart showing an example of a serial communication error interrupt process executed each time an error interrupt occurs in the serial communication circuit 108 provided in the game control microcomputer 100. Here, the serial communication circuit 108 includes the serial status register 204 when an overrun error occurs based on the settings in the third to zeroth bits [bits 3-0] of the third register SICL3 included in the serial control register 205. The third bit [bit 3] of the first register SIST1 is set to “1” and turned on, and the second bit [bit 2] of the first register SIST1 is set to “1” due to the occurrence of a noise error. The first register that is set and turned on, that the first bit [bit 1] of the first register SIST1 is set to “1” due to the occurrence of a framing error, and that the parity register error occurs. Any of the cases where the 0th bit [bit 0] of SIST1 is set to “1” and turned on. When the actual factor is generated, to generate an error interrupt.

  In the serial communication error interrupt process shown in FIG. 37, in the game control microcomputer 100, first, the CPU 104 sets the transmission operation unit 202 provided in the serial communication circuit 108 to an unused state (step S41). As a specific example, the CPU 104 sets the TE that is the third bit [bit 3] of the second register SICL2 in the serial control register 205 included in the serial communication circuit 108 to “0”, thereby causing the transmission operation unit 202 to be changed. Set to not use. Subsequently, the CPU 104 sets the reception operation unit 201 provided in the serial communication circuit 108 to an unused state (step S42). As a specific example, the CPU 104 sets the reception operation unit 201 to “0” by setting RE, which is the second bit [bit 2] of the second register SICL2, in the serial control register 205 included in the serial communication circuit 108. Set to not use. Thereafter, in the game control microcomputer 100, for example, the CPU 104 sets the payout communication error detection flag provided in the game control flag setting unit 133 to the on state (step S43), and sets the serial communication error flag to the on state. Set (step S44).

  FIG. 38 is a flowchart showing an example of a serial reception interrupt process executed each time a reception interrupt occurs in the serial communication circuit 108 provided in the game control microcomputer 100. In the serial reception interrupt process shown in FIG. 38, the game control microcomputer 100 first sets the command reception number count value, which is the value of the command reception number counter provided in the game control counter setting unit 135, to a predetermined count maximum value ( For example, the CPU 104 determines whether or not “11”) (step S51).

  When the count reaches the maximum value in step S51 (step S51; Yes), the value of the command reception number counter is set to a predetermined initial value (eg, “0”) (step S52). On the other hand, when the count is not the maximum value in step S51 (step S51; No), the value of the command reception number counter is incremented by 1 (step S53). After executing one of the processes of steps S52 and S53, the CPU 104 reads the data stored in the serial communication data register 203 provided in the serial communication circuit 108 (step S54), and uses the read data as a payout reception command buffer. The received command buffers # 1 to # 12 provided in 191 are stored in the one corresponding to the value of the command reception number counter (step S55).

  FIG. 39 is a flowchart showing an example of a serial transmission interrupt process executed each time a transmission interrupt occurs in the serial communication circuit 108 provided in the game control microcomputer 100. In the serial transmission interrupt process shown in FIG. 39, in the game control microcomputer 100, first, the CPU 104 determines whether or not the generated transmission interrupt is an interrupt at the time of transmission data empty (step S61). If the transmission data is empty (step S61; Yes), the transmission setting enable flag provided in the game control flag setting unit 133 is set to the on state (step S62).

  If it is not an interruption at transmission data empty in step S61 (step S61; No), it is determined whether or not the transmission interruption is an interruption at the completion of transmission (step S63). If it is an interrupt at the completion of transmission (step S63; Yes), the transmission completion flag provided in the game control flag setting unit 133 is set to an on state (step S64). If it is not an interruption at the time of completion of transmission in step S63 (step S63; No), a flag corresponding to the type of transmission interruption that has occurred is set to an on state (step S65).

  FIG. 40 is a flowchart showing an example of a game control timer interrupt process executed each time a timer interrupt occurs in the game control microcomputer 100. In the game control timer interrupt process shown in FIG. 40, the game control microcomputer 100 first saves the internal register (step S71), and then executes a predetermined switch process to perform each switch via the switch circuit 111. The state of the detection signal input from the switch is determined (step S72). Subsequently, in the game control microcomputer 100, for example, the CPU 104 executes a random number start value change setting process for changing the start value in the second and subsequent rounds of the random number by the user program read from the ROM 105 (step S73). Further, for example, the CPU 104 executes a random number permutation change setting process for changing the permutation in the second and subsequent rounds of random numbers by the user program read from the ROM 105 (step S74).

  After executing the random number permutation change setting process in step S74, the game control microcomputer 100 sets the number of prize balls according to the input of the winning detection signal based on the execution result of the switch process in step S72. Sphere processing is executed (step S75). In addition, the game control microcomputer 100 executes abnormal operation notification setting processing for performing settings for notifying the occurrence of an abnormality in response to excessive prize balls, insufficient prize balls, or other payout abnormalities. (Step S76). Subsequently, a main-side reception process for receiving a command transmitted from the payout control board 15 by serial communication is executed (step S77).

  Thereafter, the game control microcomputer 100 executes a special symbol process (step S78). In the special symbol process, the value of the special symbol process flag provided in the game control flag setting unit 133 is updated according to the progress of the game in the pachinko gaming machine 1 to control the display operation in the special symbol display device 4 or special Various processes are selected and executed in order to set the special winning opening / closing operation in the variable winning ball apparatus 7 in a predetermined procedure. Following the special symbol process, a normal symbol process is executed (step S79). The game control microcomputer 100 executes the normal symbol process, thereby controlling the display operation (for example, turning on / off the LED) of the normal symbol display 40 to change the normal symbol variable display (for example, turning on / off). Flashing display, etc.) and the tilt control of the movable blade piece in the normal variable winning ball apparatus 6 can be set. Further, the game control microcomputer 100 executes predetermined information output processing, for example, jackpot information, start information, probability variation information, etc. supplied to a hall management computer installed outside the pachinko gaming machine 1. Is output (step S80).

  Furthermore, the game control microcomputer 100 transmits a payout control command from the main board 11 to the payout control board 15 by executing a payout command control process (step S81). In addition, the game control microcomputer 100 transmits an effect control command from the main board 11 to the effect control board 12 by executing an effect command control process (step S82). Thereafter, the game control microcomputer 100 executes a main-side error cancellation process, and enables a predetermined error to be canceled when the detection signal from the error cancellation switch 31 is turned on (step S83). . Then, after the contents of the register saved in step S71 are restored (step S84), the game control timer interrupt process is terminated.

  41 and 42 are flowcharts showing an example of the random number start value change setting process executed in step S73 shown in FIG. When the random number start value change setting process is started, in the game control microcomputer 100, first, for example, the CPU 104 determines whether or not the 12-bit random number start value change flag provided in the game control flag setting unit 133 is on. Is determined (step S201 in FIG. 41). At this time, if the start value change flag for the 12-bit random number is on (step S201; Yes), the CPU 104 reads the setting related to the start value after the second round in the 12-bit random number (step S202), and the read value is “01. Is determined (step S203). As a specific example of the processing in step S202, setting data relating to a start value for the second and subsequent rounds in a predetermined register built in the random number circuit 103 or the CPU 104, or a 12-bit random number stored in a predetermined area of the RAM 106, What is necessary is just the process which CPU104 reads.

  When it is determined in step S203 that the read value is “01” (step S203; Yes), the random number circuit 103 generates a start value (start value after the second round) for generating a 12-bit random number. A determination is made based on an ID number which is a unique identification number assigned to each control microcomputer 100 (step S204). Here, in the process of step S204, the ID number of the game control microcomputer 100 may be set to the start value for generating a 12-bit random number as it is. Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for generating a 12-bit random number. For example, an operation for performing a predetermined scramble process on the ID number of the game control microcomputer 100 or an operation such as addition / subtraction / multiplication / division using the ID number is performed to use the calculated value. That's fine.

  When it is determined in step S203 that the read value is not “01” (step S203; No), it is determined whether or not the read value is “10” (step S205). When it is determined that the read value is “10” (step S205; Yes), the random number circuit 103 stores a start value (start value after the second round) for generating a 12-bit random number in the RAM 106. A process for determining a value based on the data is executed. That is, the CPU 104 reads the stored value at each address in the RAM 106 (step S206), and sequentially adds the read stored values (step S207). Then, the start value for generating the 12-bit random number is changed to the addition value calculated by the addition process in step S207 (step S208). In the process of step S208, it is determined whether or not the addition value calculated by the addition process in step S207 exceeds the maximum value. If not, the addition value is set as the start value as it is. In such a case, a predetermined value (for example, “1” or the like) that is equal to or less than the maximum value may be reset as the start value.

  When it is determined in step S205 that the read value is not “10” (step S205; No), it is determined whether or not the read value is “11” (step S209). When it is determined that the read value is “11” (step S209; Yes), the stored value of the designated address (designated RAM address) in the RAM 106 is read (step S210), and a start for generating a 12-bit random number is started. The value is changed to the read value in step S210 (step S211).

  Note that the processes in steps S204, S206 to S208, S210, and S211 may be executed by the initial value setting circuit 172A included in the random number circuit 103. For example, when the CPU 104 determines that the read value is “01” in step S 203, it sends a predetermined first initial value change signal to the random number circuit 103. When the random number circuit 103 receives the first initial value change signal from the CPU 104, the initial value setting circuit 172A selects data generated based on the ID number stored in a predetermined register and generates the selected data as a random number. By setting the circuit 173A or the like, the start value for the second and subsequent rounds for generating a 12-bit random number is changed to a value based on an ID number that is a unique identification number assigned to each game control microcomputer 100. Set (processing corresponding to step S204). On the other hand, when the CPU 104 determines that the read value is not “01” in step S203 and then determines that the read value is “10” in step S205, the random number circuit 103 is supplied with a predetermined second initial value change signal. Send. When the random number circuit 103 receives the second initial value change signal from the CPU 104, the initial value setting circuit 172A reads the stored value at each address of the RAM 106, and sequentially adds the read stored values. By setting the random number generation circuit 173A or the like, the start value for the second and subsequent rounds for generating a 12-bit random number is set to a value based on the data stored in the RAM 106 (processing corresponding to steps S206 to S208). When the CPU 104 determines that the read value is not “10” in step S205 and then determines that the read value is “11” in step S209, the random number circuit 103 is supplied with a predetermined third initial value change signal. Send. When the random number circuit 103 receives the third initial value change signal from the CPU 104, the initial value setting circuit 172A reads the stored value at the designated address in the RAM 106, sets the read stored value in the random number generation circuit 173A, etc. The start value after the second round for generating the bit random number is set to be changed to the read stored value (processing corresponding to steps S210 and S211). Further, the CPU 104 may directly control the operation of the initial value setting circuit 172A to execute processes corresponding to steps S204, S206 to S208, S210, and S211. For example, the initial value may be set inside or outside the random number circuit 103. Control data corresponding to the read value in step S202 is set in a predetermined register provided for change control and which can be referred to by initial value setting circuit 172A (this data setting process is performed in step S111 shown in FIG. 32). After reading the first and 0th bits [bit 1-0] of the first random number initial setting data (KRSS1) from the ROM 105, it may be executed as the process of step S112). The operation may be indirectly controlled. When the CPU 104 sets control data in the initial value change control register, for example, when the random number generation circuit 173A outputs the random number loop signal RIJ1 in the random number circuit 103, the initial value setting circuit 172A uses the initial value change control. By referring to the control data stored in the register and performing an initial value changing operation according to the control data, a start value for the second and subsequent rounds corresponding to the read value in step S202 is generated, and a random number is generated. It can be set in the generation circuit 173A.

  After executing any of the processes of steps S204, S208, and S211, or when it is determined in step S209 that the read value is not “11” (step S209; No), a 12-bit random number start value change flag is set. It is cleared and turned off (step S212). After executing the process of step S212 or when it is determined in step S201 that the 12-bit random number start value change flag is off (step S201; No), the 16-bit provided in the game control flag setting unit 133 It is determined whether or not the random number start value change flag is on (step S213 in FIG. 42). At this time, if the 16-bit random number start value change flag is off (step S213; No), the random number start value change setting process ends. On the other hand, if the start value change flag for the 16-bit random number is on (step S213; Yes), the setting related to the start value after the second round in the 16-bit random number is read (step S214), and the read value is “01”. Is determined (step S215). As a specific example of the processing in step S214, setting data relating to a start value for the second and subsequent rounds in a predetermined register built in the random number circuit 103 or the CPU 104, or a 16-bit random number stored in a predetermined area of the RAM 106, What is necessary is just the process which CPU104 reads.

  When it is determined in step S215 that the read value is “01” (step S215; Yes), the random number circuit 103 generates a start value (start value after the second round) for generating a 16-bit random number. The determination is made based on an ID number that is a unique identification number assigned to each control microcomputer 100 (step S216). Here, in the process of step S216, the ID number of the game control microcomputer 100 may be set to the start value for generating a 16-bit random number as it is. Alternatively, a value calculated by executing a predetermined calculation using the ID number of the game control microcomputer 100 may be set as a start value for generating a 16-bit random number. For example, an operation for performing a predetermined scramble process on the ID number of the game control microcomputer 100 or an operation such as addition / subtraction / multiplication / division using the ID number is performed to use the calculated value. That's fine.

  When it is determined in step S215 that the read value is not “01” (step S215; No), it is determined whether or not the read value is “10” (step S217). When it is determined that the read value is “10” (step S217; Yes), the random number circuit 103 stores a start value (start value after the second round) for generating a 16-bit random number in the RAM 106. A process for determining a value based on the data is executed. That is, the CPU 104 reads the stored value at each address in the RAM 106 (step S218), and sequentially adds the read stored values (step S219). Then, the start value for generating the 16-bit random number is changed to the addition value calculated by the addition process in step S219 (step S220). In the process of step S220, it is determined whether or not the addition value calculated by the addition process in step S219 exceeds the maximum value. If not, the addition value is set as the start value as it is. In such a case, a predetermined value (for example, “1” or the like) that is equal to or less than the maximum value may be reset as the start value.

  When it is determined in step S217 that the read value is not “10” (step S217; No), it is determined whether or not the read value is “11” (step S221). When it is determined that the read value is “11” (step S221; Yes), the stored value at the specified address (specified RAM address) in the RAM 106 is read (step S222), and a start for generating a 16-bit random number is performed. The value is changed to the read value in step S222 (step S223). After executing any of the processes of steps S216, S220, and S223, or when it is determined in step S221 that the read value is not “11” (step S221; No), a 16-bit random number start value change flag is set. Clear and turn off (step S224).

  Note that the processes of steps S216, S218 to S220, S222, and S223 may be executed by the initial value setting circuit 172B included in the random number circuit 103. For example, when the CPU 104 determines that the read value is “01” in step S 215, a predetermined fourth initial value change signal is sent to the random number circuit 103. When the random number circuit 103 receives the fourth initial value change signal from the CPU 104, the initial value setting circuit 172B selects data generated based on the ID number stored in a predetermined register, and generates the selected data as a random number. By setting in the circuit 173B, the start value for the second and subsequent rounds for generating a 16-bit random number is changed to a value based on an ID number that is a unique identification number assigned to each game control microcomputer 100. Set (processing corresponding to step S216). On the other hand, when the CPU 104 determines that the read value is not “01” in step S215 and then determines that the read value is “10” in step S217, the random number circuit 103 is supplied with a predetermined fifth initial value change signal. Send. When the random number circuit 103 receives the fifth initial value change signal from the CPU 104, the initial value setting circuit 172B reads out the stored value at each address of the RAM 106, and adds the obtained stored value sequentially. By setting the random number generation circuit 173B or the like, the start value after the second round for generating the 16-bit random number is set to a value based on the data stored in the RAM 106 (processing corresponding to steps S218 to S220). If the CPU 104 determines that the read value is not “10” in step S217 and then determines that the read value is “11” in step S221, the random number circuit 103 is supplied with a predetermined sixth initial value change signal. Send. When the random number circuit 103 receives the sixth initial value change signal from the CPU 104, the initial value setting circuit 172B reads the stored value at the designated address in the RAM 106, sets the read stored value in the random number generation circuit 173B, etc. The start value for the second and subsequent cycles for generating the bit random number is set to be changed to the read stored value (processing corresponding to steps S222 and S223). Further, the CPU 104 may directly control the operation of the initial value setting circuit 172B to execute processes corresponding to steps S216, S218 to S220, S222, and S223. For example, the initial value is set inside or outside the random number circuit 103. Control data corresponding to the read value in step S214 is set in a predetermined register provided for change control and which can be referred to by initial value setting circuit 172B (this data setting process is performed in step S111 shown in FIG. 33). After the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) are read from the ROM 105, the initial value setting circuit 172B may execute the process in step S134. The operation may be indirectly controlled. When the CPU 104 sets the control data in the initial value change control register, for example, when the random number generation circuit 173B outputs the random number loop signal RIJ2 in the random number circuit 103, the initial value setting circuit 172B is used for the initial value change control. By referring to the control data stored in the register and performing an initial value changing operation according to the control data, a start value for the second and subsequent rounds corresponding to the read value in step S214 is generated, and a random number is generated. It can be set in the generation circuit 173B.

  FIG. 43 is a flowchart showing an example of the random number permutation change setting process executed in step S74 shown in FIG. When the random number permutation change setting process is started, in the game control microcomputer 100, first, for example, the CPU 104 stores the sixth and fifth bits [bits 6-5] of the second random number initial setting data (KRSS2) stored in the ROM 105. ] Is read (step S231), and it is determined whether or not the read value is “10” (step S232).

  When it is determined in step S232 that the read value is “10” (step S232; Yes), it is determined whether or not the 12-bit random number permutation flag provided in the game control flag setting unit 133 is on. (Step S233). At this time, if the 12-bit random number permutation change flag is on (step S233; Yes), for example, the CPU 104 sets “0” to the 0th bit [bit 0] of the ARSC 175A provided in the random number circuit 103 (step S234). ). At this time, the 12-bit random number permutation flag is cleared and turned off (step S235).

  When it is determined in step S232 that the read value is not “10” (step S232; No), or when it is determined in step S233 that the 12-bit random number permutation flag is off (step S233; No). Alternatively, after executing the process of step S235, for example, the CPU 104 reads the first and 0th bits [bits 1-0] of the second random number initial setting data (KRSS2) stored in the ROM 105 (step S236). It is determined whether or not the read value is “10” (step S237). At this time, if the read value is other than “10” (step S237; No), the random number permutation change setting process is terminated.

  On the other hand, when it is determined in step S237 that the read value is “10” (step S237; Yes), whether or not the 16-bit random number permutation change flag provided in the game control flag setting unit 133 is turned on. Is determined (step S238). At this time, if the 16-bit random number permutation change flag is off (step S238; No), the random number permutation change setting process is terminated. On the other hand, if the 16-bit random number permutation change flag is on (step S238; Yes), for example, the CPU 104 sets “1” to the 0th bit [bit 0] of the BRSC 175B provided in the random number circuit 103 ( Step S239). At this time, the 16-bit random number permutation change flag is cleared and turned off (step S240).

  FIG. 44A is a flowchart showing an example of the prize ball process executed in step S75 shown in FIG. In the prize ball process shown in FIG. 44A, in the game control microcomputer 100, first, for example, the CPU 104 based on the execution result of the switch process in step S72 shown in FIG. It is checked whether or not a prize detection signal from each prize opening switch such as the prize opening switches 25A to 25D is on (step S251). Subsequently, based on the check result in step S251, the count values in the first to third payout number instruction counters and the total prize ball number counter provided in the game control counter setting unit 135 are set (step S252).

  FIG. 44B is an explanatory diagram illustrating an example of the processing content in step S252. In the process of step S252, it is determined whether or not the winning detection signal from each winning opening switch is in an ON state (whether or not it is input). When the winning detection signal from the count switch 24 is in the on state, the value of the first payout number instruction counter provided in the game control counter setting unit 135 is incremented by 1 and the value of the total prize ball number counter is set to 15. to add. In addition, when the winning detection signal from any one of the winning opening switches 25A and 25B serving as the left and right sleeve winning opening switches is ON, the value of the second payout number instruction counter provided in the game control counter setting unit 135 is set. 1 is added and 7 is added to the value of the total prize ball counter. The value of the second payout number instruction counter provided in the game control counter setting unit 135 is also obtained when the winning detection signal from any of the winning opening switches 25C and 25D serving as the left and right winning winning opening switches is ON. 1 is added and 7 is added to the value of the total prize ball counter. Further, when the winning detection signal from the start port switch 22 is in the ON state, the value of the third payout number instruction counter provided in the game control counter setting unit 135 is incremented by 1 and the value of the total winning ball number counter is set. Add 4 After executing the processing in step S252 as described above, in the game control microcomputer 100, for example, the CPU 104 performs the following step S253 according to the value of the prize ball process flag provided in the game control flag setting unit 133, for example. Each process of S255 is executed.

  The prize ball transmission process in step S253 is executed when the value of the prize ball process flag is “0”. FIG. 45 is a flowchart illustrating an example of a process executed in step S253 illustrated in FIG. 44A as the prize ball transmission process. 45, in the game control microcomputer 100, first, for example, the CPU 104 determines whether or not the serial communication error flag provided in the game control flag setting unit 133 is on (step). S301). At this time, if the serial communication error flag is on (step S301; Yes), the prize ball transmission process is terminated as it is.

  When it is determined in step S301 that the serial communication error flag is off (step S301; No), it is determined whether or not the retransmission flag provided in the game control flag setting unit 133 is on (step). S302). Here, the retransmission flag is set to the on state when the process of step S336 shown in FIG. 46 described later is executed, while it is cleared to the off state when the process of step S323 shown in FIG. 46 is executed. It becomes. When the retransmission flag is OFF in step S302 (step S302; No), the variable N used for checking the value of the first to third payout number instruction counters provided in the game control counter setting unit 135 is set. The value is set to “1” as an initial value (step S303).

  Subsequently, it is determined whether or not the value corresponding to the value of the variable N among the first to third payout number instruction counters is “0” (step S304). For example, when the value of the variable N is “1”, it is determined whether or not the value of the first payout number instruction counter is “0”, and when the value of the variable N is “2”, the second It is determined whether or not the value of the payout number instruction counter is “0”. When the value of the variable N is “3”, whether or not the value of the third payout number instruction counter is “0”. Determine. When the value of the number-of-payout instruction counter that has been determined in step S304 is “0” (step S304; Yes), it is determined whether or not the value of the variable N is “3” (step S305). , “3” (step S305; Yes), the prize ball transmission process is terminated. On the other hand, when the value of variable N is a value other than “3” in step S305 (step S305; No), 1 is added to the value of variable N (step S306), and the process returns to step S304. To do.

  When the re-transmission flag is on in step S302 (step S302; Yes), or when the value of the number-of-payout instruction counter to be determined in step S304 is a value other than “0” (step S304; No), it is determined whether or not the value of the variable N is “1” (step S307). Then, when the value of the variable N is “1” (step S307; Yes), a setting for transmitting the first payout number designation command to the payout control board 15 is performed (step S308). As a specific example, in the process of step S308, the start address of the first payout number designation command setting table stored in the ROM 105 is set as a pointer, and a command is sent based on the contents of the first payout number designation command setting table. The trust control data is set in the payout transmission command buffer 192 included in the transmission command buffer of the game control buffer setting unit 136. When the value of the variable N is a value other than “1” in step S307 (step S307; No), it is determined whether or not the value of the variable N is “2” (step S309).

  If the value of the variable N is “2” in step S309 (step S309; Yes), a setting for transmitting the second payout number designation command to the payout control board 15 is performed (step S310). As a specific example, in the process of step S310, the start address of the second payout number designation command setting table stored in the ROM 105 is set as a pointer, and command transmission is performed based on the contents of the second payout number designation command setting table. The credit control data is set in the payout transmission command buffer 192. If the value of the variable N is not “2” in step S309 (step S309; No), it is determined that the value of the variable N is “3”, and the third payout is made to the payout control board 15. Settings for transmitting the number designation command are performed (step S311). As a specific example, in the process of step S311, the start address of the third payout number designation command setting table stored in the ROM 105 is set as a pointer, and a command is sent based on the contents of the third payout number designation command setting table. The credit control data is set in the payout transmission command buffer 192.

  After executing any one of the processes of steps S308, S310, and S311, in the game control microcomputer 100, for example, the CPU 104 stores in advance a prize ball control timer provided in the game control timer setting unit 134 as an initial value for a prize ball ACK. A predetermined timer initial value is set (step S312). Then, the value of the winning ball process flag is updated to “1” (step S313).

  The prize ball ACK waiting process in step S254 shown in FIG. 44A is executed when the value of the prize ball process flag is “1”. FIG. 46 is a flowchart illustrating an example of a process executed in step S254 illustrated in FIG. 44A as the winning ball ACK waiting process. In the prize ball ACK waiting process shown in FIG. 46, in the game control microcomputer 100, first, for example, the CPU 104 determines whether or not a prize ball ACK reception flag provided in the game control flag setting unit 133 is on. (Step S321).

  When it is determined in step S321 that the prize ball ACK reception flag is on (step S321; Yes), the prize ball ACK reception flag is cleared and turned off (step S322), and the retransmission flag is cleared. To turn off (step S323). Subsequently, one of the values corresponding to the value of the variable N among the first to third payout number instruction counters is decremented by 1 (step S324), and the command transmission number counter provided in the game control counter setting unit 135 is also subtracted. 1 is added to the command transmission count value which is the value at (step S325).

  After executing the process of step S325, it is determined whether or not the value of the variable N is “1” (step S326). At this time, if the value of the variable N is “1” (step S326; Yes), it is determined that the instruction for paying out 15 prize balls has been completed by transmitting the first payout number designation command. The value of the prize ball number counter is decremented by 15 (step S327). When the value of the variable N is a value other than “1” in step S326 (step S326; No), it is determined whether or not the value of the variable N is “2” (step S328).

  If the value of the variable N is “2” in step S328 (step S328; Yes), it is determined that the instruction for paying out seven prize balls has been completed by transmitting the second payout number designation command. Then, 7 is subtracted from the value of the total prize ball counter (step S329). If the value of the variable N is not “2” in step S328 (step S328; No), the transmission of the third payout number designation command corresponding to the value of the variable N being “3” results in four pieces. It is determined that the instruction for paying out the winning ball has been completed, and the value of the total winning ball counter is decremented by 4 (step S330).

  After performing any of the processes of steps S327, S329, and S330, settings for transmitting an ACK feedback command to the payout control board 15 are performed (step S331). As a specific example, in the process of step S331, the start address of the ACK feedback command setting table stored in the ROM 105 is set as a pointer, and control data for command transmission is issued based on the contents of the ACK feedback command setting table. To the transmission command buffer 192. Subsequent to the processing in step S331, for example, the CPU 104 sets a predetermined timer initial value as an initial value for feedback in the prize ball control timer (step S332). Then, the value of the winning ball process flag is updated to “2” (step S333).

  When it is determined in step S321 that the prize ball ACK reception flag is off (step S321; No), the timer value in the prize ball control timer is updated by subtracting, for example, 1 (step S334). Then, it is determined whether or not the award ball ACK waiting time has elapsed by determining whether or not the award ball control timer has timed out due to the update in step S334 (step S335). At this time, if the prize ball ACK waiting time has not elapsed (step S335; No), the prize ball ACK waiting process is terminated. On the other hand, when the winning ball ACK waiting time has elapsed (step S335; Yes), the retransmission flag is set to the on state (step S336), and the value of the winning ball process flag is updated to “0” (step S336). Step S337).

  The prize ball transmission completion process of step S255 shown in FIG. 44A is executed when the value of the prize ball process flag is “2”. FIG. 47 is a flowchart showing an example of processing executed in step S255 shown in FIG. 44A as the winning ball transmission completion processing. In the prize ball transmission completion process shown in FIG. 47, in the game control microcomputer 100, first, for example, the CPU 104 updates the timer value in the prize ball control timer by subtracting 1 (step S341). Subsequently, it is determined whether or not the feedback transmission waiting time has elapsed by determining whether or not the prize ball control timer has timed out due to the update in step S341 (step S342).

  When the feedback transmission waiting time has not elapsed in step S342 (step S342; No), the prize ball transmission completion process is terminated. In contrast, when the feedback transmission waiting time has elapsed (step S342; Yes), the prize ball control timer is initialized (step S343), and the value of the prize ball process flag is updated to “0” (step S344). ).

  48 and 49 are flowcharts showing an example of the abnormal operation notification setting process executed in step S76 shown in FIG. When the abnormal operation notification setting process is started, the game control microcomputer 100 first turns on the detection signal from the all winning ball detection switch 29 based on the execution result of the switch process in step S72 shown in FIG. It is determined whether it is in a state (step S261 in FIG. 48).

  When the detection signal from the all winning ball detection switch 29 is on in step S261 (step S261; Yes), 1 is subtracted from the value of the command transmission number counter (step S262). On the other hand, when the detection signal from the all winning ball detection switch 29 is OFF in step S261 (step S261; No), the process of step S262 is skipped. Thereafter, in the game control microcomputer 100, for example, the CPU 104 determines whether or not the serial communication error flag is on (step S263). When the serial communication error flag is on in step S263 (step S263; Yes), it is determined whether or not the communication error notification flag provided in the game control flag setting unit 133 is on (step S264). ). Note that the communication error notification flag is set to the on state when the process of step S266 described later is executed, and is cleared to the off state when the process of step S269 is executed.

  When the communication error notification flag is on in step S264 (step S264; Yes), it is determined that a notification that a serial communication error has already occurred is performed, and the abnormal operation notification setting process is terminated. On the other hand, when the communication error notification flag is OFF in step S264 (step S264; No), setting for transmitting a serial communication abnormality notification start command to the effect control board 12 is performed (step S265). As a specific example, in the process of step S265, the start address of the serial communication error notification start command setting table stored in the ROM 105 is set as a pointer, and command transmission is performed based on the contents of the serial communication error notification start command setting table. The trust control data is set in the effect transmission command buffer of the game control buffer setting unit 136. When the process of step S265 is executed, the communication error notification flag is set to the on state (step S266).

  If the serial communication error flag is off in step S263 (step S263; No), it is determined whether or not the communication error notification flag is on (step S267). When the communication error notification flag is on (step S267; Yes), a setting for transmitting a serial communication abnormality notification end command to the effect control board 12 is performed (step S268). As a specific example, in the process of step S268, the start address of the serial communication error notification end command setting table stored in the ROM 105 is set as a pointer, and the command is determined based on the contents of the serial communication error notification end command setting table. The transmission control data is set in the production transmission command buffer. After executing the process of step S268, the communication error notification flag is cleared and turned off (step S269).

  When the communication error notification flag is off in step S267 (step S267; No), after executing the process of step S269, the value of the command transmission count counter is set to a predetermined excessive ball reference value (for example, “ 250 ") or more, for example, the CPU 104 determines (step S270). When the value of the command transmission count counter is equal to or greater than the award ball excess reference value (step S270; Yes), a setting for transmitting an award ball excess notification command to the effect control board 12 is performed (step S271). As a specific example, in the process of step S271, the start address of the excessive ball notification command setting table stored in the ROM 105 is set as a pointer, and command transmission is performed based on the content of the excessive ball notification command setting table. The control data is set in the production transmission command buffer. On the other hand, when the value of the command transmission number counter is less than the excessive ball reference value in step S270 (step S270; No), the command ball number counter value is a predetermined prize ball shortage reference value (for example, “0”). ) Is determined (step S272).

  When the value of the command transmission count counter has reached the prize ball shortage reference value in step S272 (step S272; Yes), settings are made to send a prize ball shortage notification command to the effect control board 12 (step S272). S273). As a specific example, in the process of step S273, the start address of the winning ball shortage notification command setting table stored in the ROM 105 is set as a pointer, and based on the content of the winning ball shortage notification command setting table, the command transmission The control data is set in the production transmission command buffer. After executing one of the processes in steps S271 and S273, a predetermined initial count value (for example, “200”) is set in the command transmission number counter (step S274).

  When the value of the command transmission count counter does not reach the winning ball shortage reference value in step S272 (step S272; No), after executing the process of step S274, whether or not the retransmission flag is on. Is determined (step S275). At this time, if the retransmission flag is off (step S275; No), it is determined whether or not the payout communication error detection flag is on (step S276). When the re-transmission flag is turned on in step S275 (step S275; Yes), or when the payout communication error detection flag is turned on in step S276 (step S276; Yes), the game control flag setting unit 133 It is determined whether or not the payout abnormality notification flag provided in is turned on (step S277). The payout abnormality notification flag is set to an on state when a process of step S279 described later is executed, and is cleared to an off state when the process of step S282 shown in FIG. 49 is executed.

  If the payout abnormality notification flag is on in step S277 (step S277; Yes), it is determined that a notification that an abnormality in the payout operation has already occurred is performed, and the abnormal operation notification setting process is terminated. On the other hand, when the payout abnormality notification flag is off in step S277 (step S277; No), a setting for transmitting a main-side payout abnormality notification start command to the effect control board 12 is performed (step S278). As a specific example, in the process of step S278, the head address of the main-side payout abnormality notification start command setting table stored in the ROM 105 is set as a pointer, and the command is determined based on the contents of the payout abnormality notification start command setting table. The transmission control data is set in the production transmission command buffer. Moreover, when the process of step S278 is executed, the payout abnormality notification flag is set to the on state (step S279).

  When the payout communication error detection flag is off in step S276 (step S276; No), it is determined whether or not the payout abnormality notification flag is on (step S280 in FIG. 49). When the payout abnormality notification flag is on (step S280; Yes), a setting for transmitting a main-side payout abnormality notification end command to the effect control board 12 is performed (step S281). As a specific example, in the process of step S281, the head address of the main-side payout abnormality notification end command setting table stored in the ROM 105 is set as a pointer, and the command is determined based on the contents of the payout abnormality notification end command setting table. The transmission control data is set in the production transmission command buffer. After executing the process of step S281, the payout abnormality notification flag is cleared and turned off (step S282).

  When the payout abnormality notification flag is off in step S280 (step S280; No), it is determined whether or not the payout error notification flag provided in the game control flag setting unit 133 is on (step S283). When the payout error notification flag is on (step S283; Yes), it is determined whether or not the payout error notification flag provided in the game control flag setting unit 133 is on (step S284). The payout error notification flag is set to an on state when a process of step S286 described later is executed, and is cleared to an off state when the process of step S289 is executed.

  When the payout error notification flag is on in step S284 (step S284; Yes), it is determined that a notification that an abnormality has occurred in the payout control board 15 has already been performed, and the abnormal operation notification setting process ends. To do. On the other hand, when the payout error notification flag is OFF in step S284 (step S284; No), a setting for transmitting a payout side abnormality notification start command to the effect control board 12 is performed (step S285). As a specific example, in the process of step S285, the start address of the payout side abnormality notification start command setting table stored in the ROM 105 is set as a pointer, and the command is determined based on the contents of the payout side abnormality notification start command setting table. The transmission control data is set in the production transmission command buffer. When the process of step S285 is executed, the payout error notification flag is set to the on state (step S286).

  When the payout error notification flag is off in step S283 (step S283; No), it is determined whether or not the payout error notification flag is on (step S287). When the payout error notification flag is off (step S287; No), the abnormal operation notification setting process is terminated. On the other hand, when the payout error notification flag is ON in step S287 (step S287; Yes), a setting for transmitting a payout side abnormality notification end command to the effect control board 12 is performed (step S288). . As a specific example, in the process of step S288, the start address of the payout side abnormality notification end command setting table stored in the ROM 105 is set as a pointer, and the command is determined based on the contents of the payout side abnormality notification start command setting table. The transmission control data is set in the production transmission command buffer. Further, when the process of step S288 is executed, the payout error notification flag is cleared and turned off (step S289).

  FIG. 50 is a flowchart showing an example of main-side reception processing executed in step S77 shown in FIG. When the main-side reception process is started, in the game control microcomputer 100, for example, the CPU 104 first determines whether or not the payout communication error detection flag is on (step S401). If the payout communication error detection flag is on in step S401 (step S401; Yes), the main-side reception process is terminated as it is. Thus, when an error relating to communication with the payout control board 15 occurs in the main board 11, the receiving control of the payout notification command transmitted from the payout control board 15 is stopped. .

  On the other hand, when the payout communication error detection flag is OFF in step S401 (step S401; No), for example, the value of the command reception number counter provided in the game control counter setting unit 135 by the CPU 104 is other than “0”. It is determined whether or not there is a reception command by determining whether or not there is (step S402). At this time, if it is determined that there is no reception command (step S402; No), the main-side reception process is terminated.

  When it is determined in step S402 that there is a reception command (step S402; Yes), the command reception number counter value is set to the value of the command reception number counters # 1 to # 12 provided in the payout reception command buffer 191. The stored data is read from the corresponding one (step S403), and the value of the command reception number counter is updated by subtracting, for example, the number of stored data read in step S403 (step S404). Subsequently, it is checked whether or not the received command read in step S403 is an appropriate command transmitted from the payout control board 15 (step S405). As a specific example, the exclusive command of the first byte and the second byte of the received command is calculated, and it is determined whether the calculated result is a normal value. It is possible to check whether the command is correct. In this embodiment, since the command transmitted from the payout control board 15 to the main board 11 is configured to be the second byte by inverting the first byte, one byte of the received command As a result of calculating the exclusive OR of the first and second bytes, if all the bit values are “1”, it can be determined that the received command is an appropriate command.

  As a result of the check in step S405, when it is determined that the received command is not an appropriate command (step S405; No), the payout communication error detection flag is set to the on state (step S406), and the main-side reception process is performed. finish. On the other hand, when it is determined as a result of the check in step S405 that the received command is an appropriate command (step S405; Yes), it is determined whether or not the received command is a prize ball ACK command (step S405). S407). When the received command is a prize ball ACK command (step S407; Yes), the prize ball ACK reception flag is set to an on state (step S408).

  On the other hand, when it is determined in step S407 that the received command is not a prize ball ACK command (step S407; No), it is determined whether or not the received command is a payout error notification command (step S409). When the received command is a payout error notification command (step S409; Yes), the payout error notification flag is set to an on state (step S410). When it is determined in step S409 that the received command is not a payout error notification command (step S409; No), it is determined whether or not the received command is a payout error cancel command (step S411). When the received command is a payout error cancel command (step S411; Yes), the payout error cancel flag is set to an on state (step S412). When it is determined in step S411 that the received command is not a payout error cancel command (step S411; No), the command reception flag corresponding to the type of the received command may be set to the on state (step S413).

  FIG. 51 is a flowchart showing an example of the special symbol process executed in step S78 shown in FIG. When the special symbol process is started, the game control microcomputer 100 first sets the start winning signal from the start port switch 22 to the ON state based on the execution result of the switch process in step S72 shown in FIG. It is determined whether or not (step S421). Here, in the process of step S421, for example, a timer value in a start port switch timer for measuring a period during which the start winning signal from the start port switch 22 is in an on state is loaded, and the loaded timer value is set to a predetermined value. Compared with a switch-on determination value (for example, “2”). Here, the switch-on determination value may be determined in advance corresponding to the number of executions of the game control timer interrupt process shown in FIG. 40 (for example, “2”). Accordingly, whether or not the start winning signal from the start port switch 22 is continuously on during a period (for example, 4 milliseconds) in which a predetermined number (for example, two times) of game control timer interrupt processing is executed. Can be determined. As described above, the switch-on determination value is a period (3) required for the output signal to rise from the low level to the high level after the timer circuit 179 included in the random number circuit 103 starts measuring the input time of the start winning signal SS. It is only necessary to be determined so that it can be determined that the start winning signal is on for a period longer than (milliseconds). In the process of step S421, when the loaded timer value has reached the switch-on determination value, it may be determined that the start winning signal is on.

  When it is determined in step S421 that the start winning signal is on (step S421; Yes), a predetermined winning process is executed to extract numerical data indicating a random value for jackpot determination. This is performed (step S422). On the other hand, when it is determined in step S421 that the start winning signal is off (step S421; No), the winning process in step S422 is skipped.

  In the winning process in step S422, the reserved storage number, which is the number of numerical data indicating the random value for jackpot determination stored in the special figure storage unit 131, becomes a predetermined upper limit value (eg, “4”). It is determined whether or not. At this time, if the reserved storage number is the upper limit value, the start detection by the current winning is invalidated and the winning process is terminated as it is. On the other hand, when the reserved storage number is less than the upper limit value, for example, the CPU 104 extracts numerical data indicating a random number value for jackpot determination from the random value register 181B provided for the 16-bit random number in the random number circuit 103 or the like. The numeric data indicating the extracted random number value is set at the head of the empty entry in the special figure reservation storage unit 131.

  Thereafter, in the game control microcomputer 100, for example, the CPU 104 executes the following steps S430 to S436 according to the value of the special symbol process flag provided in the game control flag setting unit 133.

  The special symbol normal process of step S430 is executed when the value of the special symbol process flag is “0”. In this special symbol normal process, in the game control microcomputer 100, for example, the CPU 104 determines whether or not the number of reserved storage in the special symbol storage unit 131 is “0”. Then, when the number of reserved memories is “0”, it is determined that the starting condition which is a precondition for starting the special figure game is not satisfied, and the special symbol normal process is ended as it is. On the other hand, when the number of reserved memories is other than “0”, the value of the special symbol process flag is updated to “1”.

  The variable display start process in step S431 is executed when the value of the special symbol process flag is “1”. The variable display start processing includes processing for determining a confirmed special symbol in the special symbol game by the special symbol display device 4, variable display time of the special symbol (total variation time), and variable display mode of the decorative symbol in the image display device 5. This includes the process of determining As a specific example, in the variable display start time process in step S431, first, numerical data indicating the jackpot determination random number value stored in correspondence with the hold number “1” is read from the special figure hold storage unit 131. At the same time, the numerical data indicating the random number values stored in the entries lower than the holding number “1” (for example, entries corresponding to the holding numbers “2” to “4”) are shifted up by one entry.

  Based on the numerical data indicating the random number value read from the special figure holding storage unit 131 in this way, for example, by referring to the big hit determination table stored in the ROM 105, the display result in the special display game or variable display of the decorative symbols is a big hit. It is determined whether or not. At this time, if it is determined that a big hit is made, the big hit flag provided in the game control flag setting unit 133 is set to an ON state, and numerical data indicating a random number value for probability change determination is extracted. Subsequently, based on the numerical data indicating the extracted random number value for probability variation determination, for example, by referring to the probability variation determination table stored in the ROM 105, the gaming state after the end of the big hit gaming state is high probability by probability variation control. It is determined whether or not to enter a state. Then, when it is determined that the high probability state is set, the probability change confirmation flag provided in the game control flag setting unit 133 is set to the on state. Further, in the variable display start process in step S431, the special symbol display device 4 is set to start the variable symbol variable display in the special symbol display device 4, for example, to start the lighting / extinguishing operation of each segment or each dot in the special symbol display device 4. I do. Thereafter, the value of the special symbol process flag is updated to “2”.

  The variable display control process of step S432 is executed when the value of the special symbol process flag is “2”. This variable display control process includes a process of measuring the remaining variable display time of the special symbol in the special symbol game by the special symbol display device 4 based on the value of the variable display time timer. When the special symbol variable display time (total variation time) has elapsed, the value of the special symbol process flag is updated to “3”.

  The variable display stop process in step S433 is executed when the value of the special symbol process flag is “3”. In the variable display stop process, it is determined whether the variable display result of the special symbol or the decorative symbol is a big hit or a loss. Further, when the pachinko gaming machine 1 is in a high probability state, it is determined whether or not the gaming state is returned from the high probability state to the normal gaming state. Transition from state to normal gaming state. As a specific example, when the number of special figure games executed in the high probability state reaches a predetermined probability variation end reference value (for example, “100”), it is determined to return from the high probability state to the normal game state. When the variable display result is a big hit, the value of the special symbol process flag is updated to “4”, while when the variable display result is lost, the value of the special symbol process flag is updated to “0”.

  The pre-opening process for the special winning opening in step S434 is executed when the value of the special symbol process flag is “4”. In the pre-opening process for the big winning opening, setting of the longest opening period of the big winning opening in each round in which the big winning opening is opened by the opening / closing plate provided in the special variable winning ball apparatus 7 in the big hit gaming state is performed. Thereafter, a setting for transmitting a big hit start command to the effect control board 12 is performed, and the value of the special symbol process flag is updated to “5”.

  The special winning opening opening process in step S435 is executed when the value of the special symbol process flag is “5”. In this special winning opening opening process, the driving of the solenoid 82 is controlled according to the setting in the pre-opening pre-opening process, thereby opening and closing the special winning opening by the opening / closing plate provided in the special variable winning ball apparatus 7. When the final round in the big hit gaming state is completed, the value of the special symbol process flag is updated to “6”. The jackpot end process in step S436 is executed when the value of the special symbol process flag is “6”. In this jackpot end process, after setting for transmitting a jackpot end command to the effect control board 12, the value of the special symbol process flag is updated to "0". Also, in the big hit end process, it is determined whether or not the probability change confirmation flag is on. When it is on, the probability change confirmation flag is cleared and turned off, and provided in the game control flag setting unit 133. Set the probable change flag to ON.

  FIG. 52 is a flowchart showing an example of the payout command control process executed in step S81 shown in FIG. When the payout command control process is started, in the game control microcomputer 100, for example, the CPU 104 first determines whether or not the serial communication error flag is on (step S451). At this time, if the serial communication error flag is ON (step S451; Yes), it is determined that the payout control command cannot be transmitted to the payout control board 15 using the serial communication circuit 108, and the payout command is determined. The control process ends.

  On the other hand, when the serial communication error flag is OFF in step S451 (step S451; No), for example, whether the elapsed time is measured by the payout communication control timer provided in the game control timer setting unit 134 or not. By determining (whether or not the timer value is other than “0”), it is determined whether or not the completion of the transmission of the payout control command is awaited (step S452). If it is determined in step S452 that transmission is not waiting (step S452; No), for example, the value of the command transmission waiting counter provided in the game control counter setting unit 135 by the CPU 104 is other than “0”. It is determined whether or not there is a transmission command by determining whether or not there is (step S453). At this time, if it is determined that there is no transmission command (step S453; No), the payout command control process is terminated.

  When it is determined in step S453 that there is a transmission command (step S453; Yes), it is determined whether the transmission setting enable flag is on (step S454). At this time, if the transmission setting enable flag is off (step S454; No), it is determined that the serial communication circuit 108 is not ready for setting the command transmission data, and the payout command control process is performed. finish. On the other hand, when the transmission setting enable flag is on in step S454 (step S454; Yes), the transmission setting enable flag is cleared and turned off (step S455).

  After executing the process of step S455, the stored data is read from the one corresponding to the value of the command transmission waiting counter among the transmission command buffers # 1 to # 12 provided in the payout transmission command buffer 192 (step S456). The read data is set in the serial communication data register 203 provided in the serial communication circuit 108 (step S457). Further, the value of the command transmission waiting counter is updated by subtracting, for example, the number of stored data read in step S456 (step S458). Subsequently, a predetermined timer initial value is set as a transmission completion waiting initial value in the payout communication control timer (step S459), and the payout command control process is terminated.

  If it is determined in step S452 that the transmission is in a standby state (step S452; Yes), for example, the CPU 104 determines whether or not the transmission completion flag is on (step S460). When the transmission completion flag is on in step S460 (step S460; Yes), the transmission completion flag is cleared and turned off (step S461), and the payout communication control timer is initialized (step S462). Then, the process proceeds to step S453 described above.

  When the transmission completion flag is OFF in step S460 (step S460; No), the value of the payout communication control timer is updated by subtracting, for example, 1 (step S463). Then, for example, by determining whether or not the payout communication control timer has timed out due to the update in step S463, it is determined whether or not the transmission completion waiting time has elapsed (step S464). At this time, if the transmission completion waiting time has elapsed (step S464; Yes), it is determined that transmission of the payout control command to the payout control board 15 could not be completed within the transmission completion waiting time, and a payout communication error is detected. The flag is set to an on state (step S465). On the other hand, if the transmission completion waiting time has not elapsed in step S464 (step S464; No), the process of step S465 is skipped and the payout command control process is terminated.

  FIG. 53 is a flowchart showing an example of the main-side error cancellation process executed in step S83 shown in FIG. When the main-side error release processing is started, in the game control microcomputer 100, first, for example, the CPU 104 determines that the detection signal from the error release switch 31 is in the ON state based on the execution result of the switch processing in step S72 shown in FIG. It is determined whether or not (step S481).

  If the detection signal from the error release switch 31 is on in step S481 (step S481; Yes), it is determined whether or not the payout communication error detection flag is on (step S482). At this time, if the payout communication error detection flag is off (step S482; No), the main-side error release processing is terminated. On the other hand, when the payout communication error detection flag is on in step S482 (step S482; Yes), the payout communication error detection flag is cleared and turned off (step S483).

  Following the processing in step S483, it is determined whether the serial communication error flag is on (step S484). At this time, if the serial communication error flag is off (step S484; No), the main-side error release processing is terminated. On the other hand, when the serial communication error flag is ON in step S484 (step S484; Yes), for example, by executing the serial communication initial setting process similar to step S26 shown in FIG. 30 (step S485), the serial communication circuit 108 is initialized. When the process of step S485 is executed, the serial communication error flag is cleared and turned off (step S486), and the main-side error release process is terminated.

  If the error release switch is off in step S481 (step S481; No), it is determined whether or not the payout error release flag is on (step S487). When the payout error release flag is on (step S487; Yes), it is determined that the payout error release command indicating that the error has been released is received from the payout control board 15, and the payout error notification flag is cleared. To turn it off (step S488). When the payout error release flag is off in step S487 (step S487; No), the processing in step S488 is skipped and the main side error release processing is terminated.

  Next, the operation in the payout control board 15 will be described. In the payout control board 15, the payout control microcomputer 150 is activated in response to the start of power supply from the power supply board 10 and the reset signal to the payout control microcomputer 150 becoming high level (off state). A payout control main process as shown in the flowchart of FIG. 54 is executed. Note that each process described below is executed by the CPU 214 included in the payout control microcomputer 150. An interrupt request based on various interrupt factors generated by the timer circuit 217, serial communication circuit 218, etc. provided in the payout control microcomputer 210 is for causing the CPU 214 to execute predetermined interrupt processing. The concept including the CPU 214 and various circuits other than the CPU 214 is sometimes referred to as a payout control microcomputer 150. When the payout control main process shown in FIG. 54 is started, the payout control microcomputer 150 first sets an interrupt prohibition (step S501) and sets an interrupt mode (step S502). Subsequently, settings relating to the stack pointer, such as setting of a stack pointer designation address, are performed (step S503). Also, the built-in device register is set (initialized) (step S504). For example, when the payout control microcomputer 150 has a built-in CTC (counter / timer) and PIO (parallel input / output port), the processing in step S504 is executed, whereby a built-in device (built-in peripheral circuit). CTC or PIO setting (initialization) or the like may be performed.

  After executing the process of step S504, it is determined whether or not the power-off signal is in an off state by checking the state of a predetermined bit at an input port provided in the payout control microcomputer 150, for example. (Step S505). For example, in the process of step S505, it is confirmed that the power-off signal is not output and is in an off state (high level).

  When the power-off signal is in the ON state in step S505 (step S505; No), after waiting for a predetermined time (for example, 0.1 second) to elapse (step S506), the process returns to the process of step S505, It is determined again whether or not the power-off signal is off. Thereby, the payout control microcomputer 150 can confirm that the power supply voltage is stable. If the power-off signal is off in step S505 (step S505; Yes), the RAM 216 is set to be accessible (step S507).

  After executing the processing of step S507, it is determined whether or not the clear signal is in an ON state by checking the state of a predetermined bit at an input port provided in the payout control microcomputer 150, for example (step S507). Step S508). Here, the payout control microcomputer 150 may confirm the state of the clear signal only once through the input port, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed once that the state of the clear signal is OFF, the state of the clear signal is confirmed once again after a predetermined time (for example, 0.1 seconds) has elapsed. At this time, if the clear signal is off, it is determined that the clear signal is off. On the other hand, if the state of the clear signal is on at this time, the state of the clear signal may be confirmed again after a predetermined time has elapsed. Note that the number of times of reconfirming the state of the clear signal may be one time or a plurality of times. In addition, it is possible to check twice and check again when the check results do not match.

  When it is determined in step S508 that the clear signal is in the OFF state (step S508; No), the data in the RAM 216 is checked to determine whether the check result is normal (step S509). In the process of step S509, for example, a checksum is calculated using data stored in a specific area of the RAM 216, and the calculated checksum is compared with the checksum stored in the payout checksum buffer. Here, the payout checksum buffer stores a checksum calculated by the same processing when the power supply was stopped last time. If the comparison results do not match, the data in the specific area of the RAM 216 is different from the data at the time of stopping the power supply, and therefore it is determined that the check result is not normal.

  When the check result in step S509 is normal (step S509; Yes), it is determined whether or not the payout backup flag provided in the payout control flag setting unit 141 is on (step S510). The state of the payout backup flag is set in the payout control flag setting unit 141 when the power supply is stopped. Then, the place where the payout backup flag is set is backed up by the backup power source, so that the state of the payout backup flag is saved even when the power supply is stopped. Whether the payout backup flag is turned on as in step S510 is determined before the check result is checked as in step S509. When the payout backup flag is on, the data check of the RAM 216 is performed. You may make it determine whether a result is normal.

  When the payout backup flag is on in step S510 (step S510; Yes), the payout backup flag is cleared and turned off (step S511), and then the internal power supply of the payout control microcomputer 150 is supplied. Settings at the time of recovery for returning to the state when stopped are performed (step S512). For example, when the value of the award ball non-payout counter provided in the payout control counter setting unit 143 is stored in the backup area of the RAM 216 when the power supply to the pachinko gaming machine 1 is stopped, in step S512 In the processing, the stored data in the backup area of the RAM 216 may be read out and set in the winning ball unpaid counter.

  Further, when the clear signal is on in step S508 (step S508; Yes), when the check result is not normal in step S509 (step S509; No), or in step S510, the payout backup flag is off. If there is (step S510; No), the RAM 216 is initialized (step S513). Subsequently, setting at the time of initialization is performed to set the internal state of the payout control microcomputer 150 to an initial state (step S514). For example, in the process of step S 514, various flags provided in the payout control flag setting unit 141, various timers provided in the payout control timer setting unit 142, or various types provided in the payout control counter setting unit 143. What is necessary is just to set each initial value to a counter etc. As a specific example, in the process of step S514, the value of the initialization command reception number counter provided in the payout control counter setting unit 143 is set to a predetermined count initial value (eg, “1”).

  After executing the processing of step S512 or step S514, for example, by setting a register of the timer circuit 217 included in the payout control microcomputer 150, a timer interrupt is generated every predetermined time (for example, 2 milliseconds). The internal setting of the payout control microcomputer 150 is performed (step S515). Thereafter, the CPU 214 reads the fourth and third bits [bit 4-3] of the first random number initial setting data (KRSS1) stored in the ROM 215 (step S516), and performs random number generation operation based on the read value. Initial setting is performed (step S517). For example, when the random number circuit 213 included in the payout control microcomputer 150 is not used on the payout control board 15 side, both the 12-bit random number and the 16-bit random number in the random number circuit 213 are generated in the process of step S517. It is only necessary to execute a process for stopping the operation.

  Subsequent to the process in step S517, the CPU 214 executes a serial communication initial setting process as a process for performing an initial setting of the serial communication operation (step S518). The serial communication initial setting process may be similar to the process shown in FIG. 34 executed by the game control microcomputer 100 on the main board 11 side. Further, the CPU 214 executes an interrupt initial setting process as a process for performing an initial setting related to the interrupt process executed based on the interrupt request (step S519). The interrupt initial setting process may be the same process as the process shown in FIG. 35 executed by the game control microcomputer 100 on the main board 11 side. Then, the CPU 214 sets the interrupt permitted state (step S520) and waits for occurrence of various interrupts. At this time, it is determined whether or not the power-off signal has been turned on (whether or not it has been output) (step S521). If it is off (step S521; No), the generation of various interrupts is awaited. When the power-off signal is turned on (step S521; Yes), the payout-side power cut-off process is executed (step S522), and then a predetermined loop process is executed to perform payout control by stopping power supply. Wait until the microcomputer 150 stops operating. In the process of step S521, the state of the power-off signal may be confirmed only once via the input port, but the state of the power-off signal may be confirmed a plurality of times. For example, if it is confirmed once that the power-off signal is in the OFF state, the power-off signal is confirmed once again after a predetermined time (for example, 0.1 second) has elapsed. At this time, if the power-off signal is off, it is determined that the power-off signal is off. On the other hand, if the state of the power-off signal is on at this time, the state of the power-off signal may be confirmed again after a predetermined time has elapsed. In addition, the number of times of reconfirming the state of the power-off signal may be one time or a plurality of times. In addition, it is possible to check twice and check again when the check results do not match. Thus, when confirming the state of the power-off signal multiple times, for example, when the confirmation operation is started or when the first confirmation result and the second confirmation result are compared and there is a mismatch, etc. Retriggering is performed to clear the WDT (watchdog timer) built in the control microcomputer 150. When the retrigger does not occur within a predetermined time due to some reason (for example, program runaway), a user reset is generated based on a timeout signal output from the WDT, and the reset / interrupt controller 212, CPU 214, timer circuit After initializing each circuit such as 217 and serial communication circuit 218, execution of the user program may be started from an address indicated by a predetermined vector table to perform automatic recovery.

  FIG. 55 is a flowchart showing an example of payout-side power-off processing executed in step S522 shown in FIG. In the payout-side power-off process shown in FIG. 55, in the payout control microcomputer 150, first, the CPU 214 sets the interrupt prohibition (step S531). Subsequently, for example, the CPU 214 performs setting for stopping the operation of the payout motor 51 by setting clear data in a predetermined bit of an output port provided in the payout control microcomputer 150 (step S532). At this time, clear data may be set for an output port to be cleared in addition to a predetermined bit of the output port. After executing the processing of step S532, check data is created, for example, by calculating the checksum using data stored in a specific area of the RAM 216 (step S533), and provided in the payout control flag setting unit 141. The payout backup flag is set to the on state (step S534). The check data created at this time is stored in a predetermined area of the RAM 216 such as a payout checksum buffer provided in the payout control buffer setting unit 144, for example. The payout control microcomputer 150 then prohibits access to the RAM 216, for example, by setting an access prohibition value in a predetermined RAM access register (step S535).

  In the payout control microcomputer 150, the interrupt processing executed by the game control microcomputer 100 mounted on the main board 11 is adapted to the payout control microcomputer 150 in response to the interrupt factor generated in the serial communication circuit 218. It is only necessary that the processed process is executed. For example, FIG. 56 is a flowchart showing an example of a serial communication error interrupt process executed every time an error interrupt occurs in the serial communication circuit 218 provided in the payout control microcomputer 150. The process shown in FIG. Is adapted to the payout control microcomputer 150.

  In the serial communication error interrupt process shown in FIG. 56, in the payout control microcomputer 150, first, the CPU 214 sets the transmission operation unit provided in the serial communication circuit 218 to an unused state (step S541). As a specific example, the CPU 214 does not use the transmission operation unit by setting TE that is the third bit [bit 3] of the second register SICL2 in the serial control register included in the serial communication circuit 218 to “0”. Set as stuff. Subsequently, the CPU 214 sets the reception operation unit provided in the serial communication circuit 218 to an unused state (step S542). As a specific example, the CPU 214 does not use the reception operation unit by setting RE, which is the second bit [bit 2] of the second register SICL2, in the serial control register included in the serial communication circuit 218 to “0”. Set as stuff. Thereafter, in the payout control microcomputer 150, for example, the CPU 214 sets the main board communication error flag provided in the payout control flag setting unit 141 to the on state (step S543), and sets the serial communication error flag to the on state. (Step S544).

  Each time a reception interrupt occurs in the serial communication circuit 218, the payout control microcomputer 150 executes serial reception interrupt processing in which the process shown in FIG. 38 is adapted to the payout control microcomputer 150, and the serial communication circuit Each time a transmission interrupt occurs at 218, the payout control microcomputer 150 may execute a serial transmission interrupt process in which the process shown in FIG. 39 is adapted to the payout control microcomputer 150.

  FIG. 57 is a flowchart showing an example of a payout control timer interrupt process executed each time a timer interrupt occurs in the payout control microcomputer 150. This payout control timer interruption process is a process that becomes a payout control process for controlling the payout motor 51 in accordance with the payout control command transmitted from the main board 11. In the payout control timer interrupt process shown in FIG. 57, the payout control microcomputer 150 executes a predetermined input / output process (step S551), for example, a predetermined bit at an input port provided in the payout control microcomputer 150. Or a predetermined control data is set for a predetermined bit in an output port provided in the payout control microcomputer 150.

  Subsequently, the payout control microcomputer 150 executes prepaid card unit processing and performs communication with the card unit 70 (step S552). Further, a payout side reception process for receiving the payout control command transmitted from the main board 11 by serial communication is executed (step S553). Then, a prize ball reception confirmation process is performed for performing a setting to transmit a prize ball ACK command when a payout number designation command from the main board 11 is received (step S554). Further, in accordance with a ball lending request from the card unit 70 or a payout number designation command from the main board 11, a payout operation control process for controlling the payout operation of the game ball is executed (step S555).

  Subsequent to the processing of step S555, the payout control microcomputer 150 performs, for example, a 7-segment display process for performing a predetermined display on the error display LED 74 in accordance with the state of various error flags provided in the payout control flag setting unit 141. Is executed (step S556). Further, a payout side transmission process for transmitting a payout notification command to the main board 11 is executed (step S557). Thereafter, the payout control microcomputer 150 executes a payout side error canceling process to enable a predetermined error to be canceled when the detection signal from the error canceling switch 73 is turned on (step S558). The payout control timer interrupt process is terminated.

  FIG. 58 is a flowchart showing an example of the payout-side reception process executed in step S553 shown in FIG. When the payout side reception process is started, the payout control microcomputer 150 first determines, for example, whether the main board communication error flag is on (step S601). If the main board communication error flag is ON in step S601 (step S601; Yes), the payout side reception process is terminated as it is. Thus, when an error relating to communication with the main board 11 occurs in the payout control board 15, the receiving control command transmitted from the main board 11 is controlled to be stopped.

  On the other hand, when the main board communication error flag is OFF in step S601 (step S601; No), for example, whether the value of the command reception number counter provided in the payout control counter setting unit 143 by the CPU 214 is other than “0”. It is determined whether or not there is a received command by determining whether or not (step S602). At this time, if it is determined that there is no reception command (step S602; No), the payout side reception process is terminated.

  When it is determined in step S602 that there is a received command (step S602; Yes), the received command buffer provided in the payout control buffer setting unit 144 stores data corresponding to the value of the command reception number counter. Data is read (step S603), and the value of the command reception number counter is updated by subtracting, for example, the number of stored data read in step S603 (step S604). Subsequently, it is checked whether or not the received command read in step S603 is an appropriate command transmitted from the main board 11 (step S605). As a specific example, the exclusive command of the first byte and the second byte of the received command is calculated, and it is determined whether the calculated result is a normal value. It is possible to check whether the command is correct. In this embodiment, since the command transmitted from the main board 11 to the payout control board 15 is configured to be the second byte by inverting the first byte, one byte of the received command. As a result of calculating the exclusive OR of the first and second bytes, if all the bit values are “1”, it can be determined that the received command is an appropriate command.

  As a result of the check in step S605, when it is determined that the received command is not an appropriate command (step S605; No), the main board communication error flag is set to the on state (step S606), and the payout side receiving process is terminated. To do. On the other hand, when it is determined that the received command is an appropriate command as a result of the check in step S605 (step S605; Yes), it is determined whether or not the received command is a payout initialization command ( Step S607). When the received command is a payout initialization command (step S607; Yes), the value of the initialization command reception number counter provided in the payout control counter setting unit 143 is a predetermined error determination value (eg, “0”). It is determined whether or not (step S608). If the error determination value is obtained in step S608 (step S608; Yes), the main board communication error flag is set to the on state (step S609), and the payout side reception process is terminated. On the other hand, when the value of the initialization command reception number counter is not the error determination value in step S608 (step S608; No), the count value is updated by subtracting 1 from the value of the initialization command reception number counter, for example. (Step S610).

  If it is determined in step S607 that the received command is not a payout initialization command (step S607; No), it is determined whether the received command is a payout number designation command (step S611). When the received command is a payout number designation command (step S611; Yes), the award ball payout number designated by the command is added to the value of the award ball unpaid counter and stored (step S612). At this time, the award ball ACK transmission flag provided in the payout control flag setting unit 141 is set to an on state (step S613), and a predetermined count initial value is set in the payout operation failure number counter provided in the payout control counter setting unit 143. A value (eg, “9”) is set (step S614), and a predetermined initial count value (eg, “1”) is set in the initialization command reception number counter (step S615).

  When it is determined in step S611 that the received command is not a payout number designation command (step S611; No), it is determined whether the received command is an ACK feedback command (step S616). When the received command is an ACK feedback command (step S616; Yes), the feedback reception flag provided in the payout control flag setting unit 141 is set to an on state (step S617). If it is determined in step S616 that the received command is not an ACK feedback command (step S616; No), a command reception flag corresponding to the type of the received command may be set to an on state (step S618).

  FIG. 59 is a flowchart showing an example of the winning ball reception confirmation process executed in step S554 shown in FIG. When the winning ball reception confirmation process is started, for example, the CPU 214 determines whether or not the main board communication error flag is turned on in the payout control microcomputer 150 (step S631). When the main board communication error flag is ON in step S631 (step S631; Yes), the prize ball reception confirmation process is ended as it is.

  On the other hand, when the main board communication error flag is off in step S631 (step S631; No), it is determined whether or not the reception confirmation flag provided in the payout control flag setting unit 141 is on (step). S632). Here, the reception confirmation in progress flag is set to the on state when the process of step S637 described later is executed, and is cleared to the off state when any of the processes of steps S641 and S646 is executed. Become.

  When the reception confirmation flag is off in step S632 (step S632; No), it is determined whether or not the prize ball ACK transmission flag is on (step S633). When the prize ball ACK transmission flag is OFF in step S633 (step S633; No), the prize ball reception confirmation process is terminated. On the other hand, when the prize ball ACK transmission flag is ON in step S633 (step S633; Yes), settings for transmitting the prize ball ACK command to the main board 11 are performed (step S634). As a specific example, in the process of step S634, the start address of the prize ball ACK command setting table stored in the ROM 215 is set as a pointer, and control for command transmission is performed based on the contents of the prize ball ACK command setting table. Data is set in a transmission command buffer provided in the payout control buffer setting unit 144. When the process of step S634 is executed, a timer initial value set in advance as a feedback standby initial value is set in the communication control timer provided in the payout control timer setting unit 142 (step S635). At this time, the winning ball ACK transmission flag is cleared and turned off (step S636), and the reception confirmation flag is set to on (step S637).

  If the reception confirmation flag is on in step S632 (step S632; Yes), it is determined whether the feedback reception flag is on (step S638). When the feedback reception flag is on (step S638; Yes), the feedback reception flag is cleared and turned off (step S639), the communication control timer is initialized (step S640), and the reception confirmation flag is set. It is cleared and turned off (step S641).

  When the feedback reception flag is off in step S638 (step S638; No), the value of the communication control timer is updated by subtracting, for example, 1 (step S642). Then, for example, it is determined whether or not the feedback waiting time has elapsed by determining whether or not the communication control timer has timed out due to the update in step S642 (step S643). At this time, if the feedback standby time has not elapsed (step S643; No), the winning ball reception confirmation process is terminated. On the other hand, when the feedback standby time has elapsed in step S643 (step S643; Yes), the main board communication error flag is set to the on state (step S644), and the payout number designation command received from the main board 11 is received. It is determined that it is invalid, and the number of payouts indicated by the payout number designation command is subtracted from the winning ball non-payout counter (step S645). That is, in the process of step S645, the number of payouts added to the value of the award ball unpaid counter in step S612 shown in FIG. 58 is subtracted from the value of the award ball unpaid counter and stored. At this time, the reception confirmation flag is cleared and turned off (step S646).

  FIG. 60 is a flowchart showing an example of the payout operation control process executed in step S555 shown in FIG. When the payout operation control process shown in FIG. 60 is started, the payout control microcomputer 150 first, for example, the payout number storage abnormality for the CPU 214 to determine whether or not an abnormality has occurred in the memory relating to the number of unpaid prize balls. A determination process is executed (step S661). After executing the payout number storage abnormality determination process in step S661, the processes in steps S662 to S664 as shown in FIG. Execute. Here, the payout control normal process in step S662 is executed when the value of the payout control process flag is “0”. The prize ball payout operation processing in step S663 is executed when the value of the payout control process flag is “1”. The ball lending payout operation process in step S664 is executed when the value of the payout control process flag is “2”.

  FIG. 61 is a flowchart showing an example of the payout amount storage abnormality determination process executed in step S661 shown in FIG. In the payout number storage abnormality determination process, first, an increment in the count value stored in the prize ball non-payout counter is specified (step S701). For example, the payout control data holding area 140 provided in the RAM 216 has a previous count value storage area, and when the value of the award ball non-payout counter is updated by executing the processing of step S612 shown in FIG. The count value in the award ball unpaid counter before the update is stored in the previous count value storage area. In the process of step S701, the increment in the count value can be specified by reading the stored data in the previous count value storage area and taking the difference from the value of the award ball unpaid counter.

  Subsequently, it is determined whether or not the increment of the count value specified in step S701 is equal to or less than a predetermined prize ball increase upper limit (eg, “15”) (step S702). In this embodiment, the maximum value of the number of payouts specified by the payout control command transmitted from the main board 11 to the payout control board 15 is specified by the first payout number specifying command shown in FIG. “15”. When it is determined by the payout control microcomputer 150 that a timer interruption has occurred, the payout side reception process in step S553 shown in FIG. 57 is executed once. Therefore, the increment of the count value in the award ball non-payout counter between the execution of the previous payout operation control process and the execution of the current payout operation control process is at most by the first payout number designation command. The designated “15”. Therefore, when it is determined in step S702 that the increment of the count value exceeds the award ball increase upper limit value (step S702; No), the count value in the award ball unpaid counter has increased abnormally, and the value is invalid. Is determined, the winning ball unpaid counter is cleared and the count value is initialized (step S703).

  When the increment of the count value is less than or equal to the upper limit value of the prize ball increase in step S702 (step S702; Yes), the increment in the count value stored in the ball lending unpaid counter provided in the payout control counter setting unit 143 Minutes are specified (step S704). Then, it is determined whether or not the increment of the count value specified in step S704 is equal to or less than a predetermined ball lending increase upper limit (for example, “25”) (step S705). At this time, if the increment of the count value exceeds the ball lending increase upper limit value (step S705; No), it is determined that the value is invalid because the count value in the ball lending unpaid counter has increased abnormally. The ball rental unpaid counter is cleared and the count value is initialized (step S706).

  When the increment of the count value is equal to or less than the ball lending increase upper limit value in step S705 (step S705; Yes), or after executing any one of steps S703 and S706, the value of the winning ball unpaid counter is It is determined whether or not it is less than a predetermined large amount unpaid upper limit value (eg, “50”) (step S707). At this time, if it is determined that it is less than the large amount unpaid upper limit (step S707; Yes), the large amount unpaid error flag provided in the payout control flag setting unit 141 is cleared and turned off (step S708). . On the other hand, when it is not less than the large amount unpaid upper limit (step S707; No), the large amount unpaid error flag is set to the on state (step S709).

  FIG. 62 is a flowchart showing an example of the payout control normal process executed in step S662 shown in FIG. When this payout control normal process is started, in the payout control microcomputer 150, for example, the CPU 214 first determines whether or not the main board communication error flag is on (step S721). When the main board communication error flag is on in step S721 (step S721; Yes), the payout control normal process is terminated as it is. As a result, when an error relating to communication with the main board 11 occurs in the payout control board 15, the payout control of the game ball that becomes a prize ball or a rental ball is controlled to stop. .

  On the other hand, when the main board communication error flag is OFF in step S721 (step S721; No), it is determined whether or not the value of the winning ball unpaid counter is a value other than “0” (step S722). . At this time, if the value of the award ball non-payout counter is a value other than “0” (step S722; Yes), for example, a ball runout error flag provided in the payout control flag setting unit 141 is checked. It is determined whether or not it is in a cut state (step S723). When the ball is out of play (step S723; Yes), the payout control normal process is terminated. On the other hand, if the ball is not out of state in step S723 (step S723; No), the value of the payout control process flag is updated to “1” which is a value corresponding to the prize ball payout operation process (step S723). S724).

  Further, when the value of the winning ball non-payout counter is “0” in step S722 (step S722; No), it is determined whether or not the BRDY signal transmitted from the card unit 70 is in an on state (step S722). S725). At this time, if the BRDY signal is in an OFF state (step S725; No), the payout control normal process is terminated. On the other hand, when the BRDY signal is in the on state in step S725 (step S725; Yes), it is determined whether or not the ball lending request signal (BRQ signal) transmitted from the card unit 70 is in the on state. (Step S726). When the ball lending request signal is in the off state (step S726; No), the payout control normal process is terminated.

  When the ball lending request signal is on in step S726 (step S726; Yes), for example, by checking a ball break error flag provided in the payout control flag setting unit 141 or a card unit unconnected error flag. Then, it is determined whether or not the ball can be lent (step S727). When it is determined that the ball lending error flag or the card unit unconnected error flag is in an on state, for example, it is determined that the ball lending is not possible (step S727; No), the payout control is normal. The process ends. On the other hand, when it is possible to lend a ball in step S727 (step S727; Yes), a count initial value (for example, “25”) determined in advance as a ball lending initial value in the ball lending unpaid counter. ) Is set (step S728). Then, the value of the payout control process flag is updated to “2” which is a value corresponding to the ball lending payout operation process (step S729).

  FIG. 63 is a flowchart showing an example of a prize ball payout operation process executed in step S663 shown in FIG. When the winning ball payout operation process is started, in the payout control microcomputer 150, first, for example, the CPU 214 detects that the detection signal from the payout count switch 72 is in the ON state based on the execution result of the input / output process in step S551 shown in FIG. It is determined whether or not (step S741). When the detection signal from the payout count switch 72 is on (step S741; Yes), 1 is added to the value of the payout number counter provided in the payout control counter setting unit 143 (step S742). On the other hand, when the detection signal from the payout count switch 72 is OFF in step S741 (step S741; No), the process of step S742 is skipped. Thereafter, according to the value of the prize ball payout operation process flag provided in the payout control flag setting unit 141, one of the processes of steps S743 and S744 shown in FIG. 63 is selected and executed. Here, the prize ball payout number calculation process in step S743 is executed when the value of the prize ball payout operation process flag is “0”. The prize ball payout driving process in step S744 is executed when the value of the prize ball payout operation process flag is “1”.

  FIG. 64 is a flowchart showing an example of a prize ball payout number calculation process executed in step S743 shown in FIG. When the winning ball payout number calculation process is started, the payout control microcomputer 150 first determines, for example, whether the main board communication error flag is on (step S801). If the main board communication error flag is ON in step S801 (step S801; Yes), the award ball payout number calculation process is terminated as it is. As a result, when an error relating to communication with the main board 11 occurs in the payout control board 15, the payout control of the game balls that are unpaid prize balls is controlled to stop. .

  On the other hand, when the main board communication error flag is OFF in step S801 (step S801; No), it is determined whether or not the value of the award ball non-payout counter is larger than the value of the payout number counter ( Step S802). Here, when the value of the award ball non-payout counter is equal to or smaller than the value of the number-of-payout counter in step S802 (step S802; No), it corresponds to the value of the award ball non-payout counter. It is determined that the game ball payout operation has been completed. At this time, the payout operation failure number counter provided in the payout control counter setting unit 143 is cleared to initialize the count value (step S803), and the award ball non-payout counter is cleared to initialize the count value ( Step S804).

  If the value of the award ball non-payout counter is larger than the value of the payout number counter in step S802 (step S802; Yes), the number of game balls counted by the award ball non-payout counter is It is determined that the payout operation has not been completed yet. Therefore, the number of game balls that have not yet been paid out is identified by subtracting the number of payouts that is the value of the payout number counter from the number of payouts that is the value of the award ball unpaid counter (step S805). . Subsequently, the subtraction value as the value specified by the subtraction process in step S805 is set in the payout motor rotation counter provided in the payout control counter setting unit 143 (step S806).

  Following the processing in step S806, it is determined whether or not the value of the payout operation failure frequency counter exceeds a predetermined failure frequency upper limit (eg, “9”) (step S807). At this time, if the defect count upper limit is exceeded (step S807; Yes), the ball clogging error flag provided in the dispensing control flag setting unit 141 is set to the on state (step S808), and the dispensing operation failure counter Is cleared and the count value is initialized (step S809). On the other hand, if it is equal to or less than the upper limit value of the number of defects in step S807 (step S807; No), it is determined whether or not a game ball payout operation as a prize ball is possible (step S810). As a specific example, in the process of step S810, a ball clogging error flag, a blanking error flag, a ball biting error flag, a ball biting error flag, a full tank error flag, etc. are checked, and one of the error flags is on. When it is, it is determined that the game ball serving as a prize ball cannot be paid out. On the other hand, when any of the error flags is in the off state, it is determined that the game ball as the winning ball can be paid out.

  After executing the process of step S804 or when the payout operation is impossible in step S810 (step S810; No), the value of the payout control process flag is updated to “0” (step S811). The payout number counter is cleared and the count value is initialized (step S812). Also, the payout motor rotation counter is cleared and the count value is initialized (step S813). On the other hand, when the payout operation is possible in step S810 (step S810; Yes), the winning ball is not paid out by setting the subtraction value obtained in step S805 in the winning ball non-payout counter. The counter value is updated (step S814). Then, the value of the winning ball payout operation process flag is updated to “1” which is a value corresponding to the winning ball payout driving process (step S815).

  FIG. 65 is a flowchart showing an example of a prize ball payout drive process executed in step S744 shown in FIG. When the winning ball payout driving process is started, the payout control microcomputer 150 first determines, for example, whether the main board communication error flag is on (step S821). When the main board communication error flag is OFF in step S821 (step S821; No), it is determined whether or not the value of the award ball non-payout counter is larger than the value of the payout number counter (step S822). ). Here, when the value of the award ball non-payout counter is larger than the value of the number-of-payout counter in step S822 (step S822; Yes), a normal payout operation of the game ball serving as a prize ball is performed. It is judged that At this time, for example, by determining whether the elapsed time is measured by the payout operation control timer provided in the payout control timer setting unit 142 (whether the timer value is other than “0”) or the like. Then, it is determined whether or not the completion of the winning ball payout operation is on standby (step S823).

  When it is determined in step S823 that the player is not waiting for a prize ball payout operation (step S823; No), for example, one game ball as a prize ball is paid out from the excitation time of the payout motor 51, for example. It is determined whether or not the payout operation is in progress (step S824). When the payout operation for paying out one game ball is not in progress (step S824; No), it is determined whether or not the value of the payout motor rotation counter is “0” (step S825). When the value of the payout motor rotation counter is “0” in step S825 (step S825; Yes), the setting for stopping the driving of the payout motor 51 is performed (step S826), and the payout operation control timer completes payout. A predetermined timer initial value is set as the waiting initial value (step S827), and the winning ball payout driving process is terminated. The payout completion waiting initial value corresponds in advance to the maximum time required for the game ball payout to be detected by the payout count switch 72 after the game ball payout operation is performed by driving the payout motor 51. Any predetermined timer initial value may be used.

  When the value of the payout motor rotation counter is a value other than “0” in step S825 (step S825; No), for example, one game ball is set such that the start address of a predetermined excitation pattern table is set as a pointer. Settings relating to a payout operation for payout are performed (step S828). At this time, the value of the payout motor number counter is updated by subtracting 1 (step S829), and the winning ball payout driving process is terminated.

  Further, when the payout operation for paying out one game ball is being performed in step S824 (step S824; Yes), for example, the state of various error flags provided in the payout control flag setting unit 141 is confirmed. Thus, it is checked whether or not an error has occurred in the payout operation by the payout motor 51 (step S830). At this time, if an error has occurred in the payout operation (step S830; No), for example, a setting for stopping the drive of the payout motor 51 is performed in the same manner as in step S826. Settings corresponding to the generated error are made (step S831). On the other hand, when it is determined in step S830 that no error has occurred in the payout operation (step S830; Yes), the process of step S831 is skipped and the prize ball payout drive process is terminated.

  When it is determined in step S823 that the award ball payout operation is waiting to be completed (step S823; Yes), the value of the payout operation control timer is updated, for example, by 1 (step S832). . Subsequently, it is determined whether or not the value of the payout number counter has reached the value of the award ball non-payout counter (step S833). At this time, if the value of the payout number counter has reached the value of the award ball non-payout counter (step S833; Yes), it is determined that the game ball as the award ball to be paid out has been normally completed, After the value of the ball payout control process flag is updated to “0” (step S834), the winning ball payout driving process is terminated. On the other hand, if the value of the payout number counter does not reach the value of the award ball non-payout counter in step S833 (step S833; No), for example, it is determined whether or not the payout operation control timer has timed out due to the update in step S832. It is determined whether or not the payout completion waiting time has elapsed (step S835). At this time, if the payout completion waiting time has not elapsed (step S835; No), the winning ball payout driving process is terminated. On the other hand, when the payout completion waiting time has elapsed in step S835 (step S835; Yes), the game counted by the payout counter as a game ball already paid out by driving the payout motor 51. It is determined that a waiting time for waiting for the completion of the prize ball payout operation has passed before the number of balls reaches the number of game balls counted by the prize ball non-payout counter as prize balls to be paid out. At this time, the value of the payout operation failure number counter is incremented by 1 (step S826), and then the process proceeds to step S834 to update the value of the winning ball payout control process flag to “0”.

  FIG. 58 shows a stage before the determination that the value of the payout motor rotation counter is “0” in step S825 after the award ball payout number calculation process in step S743 shown in FIG. 63 is executed. When it is determined in step S611 that the payout number designation command has been received, the number of game balls counted by the payout number counter reaches the number of game balls counted by the award ball non-payout counter. Before that, the value of the payout motor rotation counter becomes “0”, and it may be determined in step S835 that the payout completion waiting time has elapsed. In this embodiment, by setting the upper limit value of the number of failures compared with the value of the number of defective operation counters in step S807 shown in FIG. 64 to an appropriate value (for example, “9”), the number of payouts on the way Even when a designated command is received, it is possible to appropriately detect a failure in the payout operation due to occurrence of a clogged ball or the like in the payout device while preventing an error from being immediately determined.

  When the main board communication error flag is ON in step S821 (step S821; Yes), the value of the award ball non-payout counter is equal to or smaller than the value of the payout number counter in step S822. (Step S822; No), the setting for stopping the driving of the payout motor 51 is performed as in Step S826 (Step S837), and the value of the prize ball payout operation process flag is updated to “0”. (Step S838). As described above, when the main board communication error flag is ON in step S821, the process proceeds to step S837 to stop driving of the payout motor 51, so that the payout control board 15 is connected to the main board 11. When an error relating to communication has occurred, the payout control of the game ball that becomes an unpaid prize ball can be controlled to be stopped.

  FIG. 66 is a flowchart showing an example of the ball lending / dispensing operation process executed in step S664 shown in FIG. When the ball lending / dispensing operation process is started, in the payout control microcomputer 150, first, for example, the CPU 214 detects that the detection signal from the payout count switch 72 is on based on the execution result of the input / output process in step S551 shown in FIG. It is determined whether or not (step S761). When the detection signal from the payout count switch 72 is on (step S761; Yes), the value of the payout number counter provided in the payout control counter setting unit 143 is incremented by 1 (step S762). On the other hand, when the detection signal from the payout count switch 72 is OFF in step S761 (step S761; No), the process of step S762 is skipped. Thereafter, according to the value of the ball lending operation process flag provided in the payout control flag setting unit 141, one of the processes of steps S763 and S764 shown in FIG. 66 is selected and executed. Here, the ball lending / dispensing number calculation processing in step S763 is executed when the value of the ball lending operation process flag is “0”. The ball lending payout driving process in step S764 is executed when the value of the ball lending operation process flag is “1”.

  FIG. 67 is a flowchart showing an example of the ball lending / dispensing number calculation processing executed in step S763 shown in FIG. When the ball lending / dispensing count calculation process is started, the payout control microcomputer 150 first determines, for example, whether or not the value of the ball lending unpaid counter is larger than the value of the number-of-payout counter. (Step S841). Here, when the value of the unpaid ball lending counter is equal to or smaller than the value of the number-of-payout counter in step S841 (step S841; No), it corresponds to the value of the lending unpaid counter. It is determined that the game ball payout operation has been completed. At this time, the payout operation failure frequency counter is cleared and the count value is initialized (step S842), and the ball lending unpaid counter is cleared and the count value is initialized (step S843).

  On the other hand, when the value of the unpaid ball lending counter is larger than the value of the number-of-payout counter in Step S841 (Step S841; Yes), out of the number of game balls counted by the lending unpaid counter It is determined that the payout operation has not been completed yet. Therefore, the number of game balls for which the payout operation has not yet been completed is specified by subtracting the payout number that is the value of the payout number counter from the unpaid number that is the value of the ball lending unpaid counter (step S844). . Subsequently, the subtraction value as the value specified by the subtraction process in step S844 is set in the payout motor rotation counter (step S845).

  Following the process of step S845, it is determined whether or not the value of the payout operation failure frequency counter exceeds a predetermined failure frequency upper limit (eg, “9”) (step S846). At this time, if the upper limit value of the number of failures is exceeded (step S846; Yes), the ball clogging error flag is set to the on state (step S847), and the payout operation failure number counter is cleared and the count value is initialized. (Step S848). On the other hand, if it is equal to or less than the upper limit value of the number of defects in step S846 (step S846; No), it is determined whether or not a game ball serving as a rental ball can be paid out (step S849). As a specific example, in the process of step S849, the ball clogging error flag, empty cut error flag, ball biting error flag, ball cut error flag, full tank error flag, card unit unconnected error flag, etc. are checked. When such an error flag is in the on state, it is determined that the payout operation of the game ball to be rented is impossible. On the other hand, when any error flag is in the off state, it is determined that the payout operation of the game ball to be rented is possible.

  After executing the process of step S843 or when the payout operation is impossible in step S849 (step S849; No), the value of the payout control process flag is updated to “0” (step S850). The payout number counter is cleared and the count value is initialized (step S851). Further, the payout motor rotation counter is cleared and the count value is initialized (step S852). On the other hand, when the payout operation is possible in step S849 (step S849; Yes), the subtracted value obtained in step S844 is set in the award ball non-payout counter, thereby not lending the ball. The counter value is updated (step S853). Then, the value of the ball lending operation process flag is updated to “1” which is a value corresponding to the ball lending payout driving process (step S854).

  FIG. 68 is a flowchart showing an example of the ball lending / dispensing drive process executed in step S764 shown in FIG. When this ball rental payout driving process is started, the payout control microcomputer 150 first determines, for example, whether or not the value of the ball loan unpaid counter is larger than the value of the payout number counter. (Step S861). Here, when the value of the ball lending unpaid counter is larger than the value of the number-of-payout counter in step S861 (step S861; Yes), a normal payout operation of the game ball serving as the lending ball is performed. It is judged that At this time, for example, by determining whether the elapsed time is measured by the payout operation control timer provided in the payout control timer setting unit 142 (whether the timer value is other than “0”) or the like. Then, it is determined whether or not waiting for completion of the payout operation in the ball lending (step S862).

  When it is determined in step S862 that the payout operation is not waiting (step S862; No), for example, payout for paying out one game ball to be rented from the excitation time of the payout motor 51, etc. It is determined whether or not it is operating (step S863). When the payout operation for paying out one game ball is not in progress (step S863; No), it is determined whether or not the value of the payout motor rotation counter is “0” (step S864). When the value of the payout motor rotation counter is “0” in step S864 (step S864; Yes), setting is made to stop driving of the payout motor 51 (step S865), and payout is completed in the payout operation control timer. A predetermined timer initial value is set as a waiting initial value (step S866), and the ball lending / dispensing driving process is terminated.

  When the value of the payout motor rotation counter is a value other than “0” in step S864 (step S864; No), for example, one game ball is set such that the start address of a predetermined excitation pattern table is set as a pointer. Settings relating to a payout operation for payout are performed (step S867). At this time, after updating by subtracting 1 from the value of the payout motor number counter (step S868), the ball lending payout driving process is terminated.

  Further, when the payout operation for paying out one game ball is being performed in step S863 (step S863; Yes), for example, the state of various error flags provided in the payout control flag setting unit 141 is confirmed. Thus, it is checked whether or not an error has occurred in the payout operation by the payout motor 51 (step S869). At this time, if an error has occurred in the payout operation (step S869; No), for example, a setting for stopping the drive of the payout motor 51 is performed in the same manner as in step S865, during the payout operation by the payout motor 51. Settings corresponding to the generated error are made (step S870). On the other hand, when it is determined in step S869 that no error has occurred in the payout operation (step S869; Yes), the process of step S870 is skipped and the ball lending payout driving process is terminated.

  When it is determined in step S862 that the payout operation in the ball lending is completed (step S862; Yes), the value of the payout operation control timer is updated by, for example, subtracting 1 (step S871). ). Subsequently, it is determined whether or not the value of the payout number counter has reached the value of the unpaid ball lending counter (step S872). At this time, if the value of the payout number counter has reached the value of the ball lending unpaid counter (step S872; Yes), it is determined that the payout of the game ball as the lending ball to be paid out is completed normally. After the value of the lending operation process flag is updated to “0” (step S873), the ball lending / dispensing driving process is terminated. On the other hand, if the value of the payout number counter does not reach the value of the unpaid ball lending counter in step S872 (step S872; No), for example, it is determined whether or not the payout operation control timer has timed out by updating in step S871. It is determined whether or not the payout completion waiting time has elapsed (step S874). At this time, if the payout completion waiting time has not elapsed (step S874; No), the winning ball payout driving process is terminated. On the other hand, when the payout completion waiting time has elapsed in step S874 (step S874; Yes), the game counted by the payout counter as a game ball already paid out by driving the payout motor 51. It is determined that the waiting time for waiting for completion of the payout operation in the ball lending has elapsed before the number of balls reaches the number of game balls counted by the ball lending unpaid counter as lending balls to be paid out. At this time, the value of the payout operation failure number counter is incremented by 1 (step S875), and then the process proceeds to step S873, where the value of the ball lending operation process flag is updated to “0”.

  When the value of the unpaid ball lending counter is equal to or smaller than the value of the number-of-payout counter in step S861 (step S861; No), the payout motor 51 is driven in the same manner as in step S865. The setting for stopping is performed (step S876), and the value of the ball lending operation process flag is updated to “0” (step S877).

  In the 7-segment display process executed in step S556 shown in FIG. 57, for example, the CPU 214 provided in the payout control microcomputer 150 checks the states of various error flags provided in the payout control flag setting unit 141. Then, control data for controlling the lighting operation of the error display LED 74 corresponding to the error flag in the on state is set in a predetermined output port provided in the payout control microcomputer 150. FIG. 69 is an explanatory diagram showing the relationship between the type of error and the display of the LED 74 for error display.

  As shown in FIG. 69, when the main board communication error flag is turned on, the payout control microcomputer 150 performs control to display “0” on the error display LED 74 as the main board communication error. . When the ball-out error flag is turned on, control is performed to display “1” on the error display LED 74 as a ball-out error. When the ball biting error flag is turned on, control is performed to display “2” on the error display LED 74 as a ball biting error. When the idle error flag is turned on, control is performed to display “3” on the error display LED 74 as an idle error. When the serial communication error flag is turned on, control is performed to display “4” on the error display LED 74 as a serial communication error. When the ball clogging error flag is turned on, control is performed to display “5” on the error display LED 74 as a ball clogging error. When the card unit unconnected error flag is turned on, control is performed to display “7” on the error display LED 74 as a card unit unconnected error. When the large amount unpaid error flag is turned on, control is performed to display “9” on the error display LED 74 as a large amount unpaid error.

  FIG. 70 is a flowchart showing an example of the payout side transmission process executed in step S557 shown in FIG. When the payout-side transmission process is started, the payout control microcomputer 150 first determines, for example, whether the serial communication error flag is on (step S671). At this time, if the serial communication error flag is on (step S671; Yes), it is determined that the payout notification command cannot be transmitted to the main board 11 using the serial communication circuit 218, and the payout side transmission process is performed. Exit.

  On the other hand, when the serial communication error flag is OFF in step S671 (step S671; No), it is determined whether an error flag other than the serial communication error flag provided in the payout control flag setting unit 141 is on. Determination is made (step S672). At this time, if any one of the error flags is on (step S672; Yes), a setting for transmitting a payout error notification command to the main board 11 is performed (step S673). As a specific example, in the process of step S673, the start address of the payout error notification command setting table stored in the ROM 215 is set as a pointer, and control data for command transmission is set based on the content of the payout error notification command setting table. It is set in a transmission command buffer provided in the payout control buffer setting unit 144. On the other hand, when any error flag is OFF in step S672 (step S672; No), the process of step S673 is skipped.

  Thereafter, for example, by determining whether or not the elapsed time is measured by the transmission operation control timer provided in the payout control timer setting unit 142 (whether or not the timer value is other than “0”). Then, it is determined whether or not the completion of the transmission of the payout notification command is waiting (step S674). When it is determined in step S674 that transmission is not waiting (step S674; No), for example, the count value of the command transmission waiting counter provided in the payout control counter setting unit 143 by the CPU 214 is other than “0”. It is determined whether or not there is a transmission command by determining whether or not it is (step S675). At this time, if it is determined that there is no transmission command (step S675; No), the payout side transmission process is terminated.

  When it is determined in step S675 that there is a transmission command (step S675; Yes), it is determined whether or not the transmission setting enable flag provided in the payout control flag setting unit 141 is on (step S676). ). At this time, if the transmission setting enable flag is off (step S676; No), it is determined that the serial communication circuit 218 is not ready to set command transmission data, and the payout side transmission processing is terminated. To do. On the other hand, when the transmission setting enable flag is on in step S676 (step S676; Yes), the transmission setting enable flag is cleared and turned off (step S677).

  After executing the processing of step S677, the stored data is read from the transmission command buffer provided in the payout control buffer setting unit 144 corresponding to the value of the command transmission waiting counter (step S678), and the read data is read out. The serial communication data register provided in the serial communication circuit 218 is set (step S679). Further, the value of the command transmission waiting counter is updated by subtracting, for example, the number of stored data read in step S678 (step S680). Subsequently, a predetermined timer initial value is set as a transmission completion waiting initial value in the transmission operation control timer (step S681), and the payout side transmission process is terminated.

  If it is determined in step S674 that the transmission is in a waiting state (step S674; Yes), whether or not the transmission completion flag provided in the payout control flag setting unit 141 is on is determined. For example, the CPU 214 determines (step S682). When the transmission completion flag is on in step S682 (step S682; Yes), the transmission completion flag is cleared and turned off (step S683), and the transmission operation control timer is initialized (step S684). The process proceeds to step S675 described above.

  When the transmission completion flag is OFF in step S682 (step S682; No), the value of the transmission operation control timer is updated by subtracting, for example, 1 (step S685). Then, for example, it is determined whether or not the transmission completion waiting time has elapsed by determining whether or not the payout communication control timer has timed out due to the update in step S685 (step S686). At this time, if the transmission completion waiting time has elapsed (step S686; Yes), it is determined that transmission of the payout notification command to the main board 11 could not be completed within the transmission completion waiting time, and the main board communication error flag is set. The on state is set (step S687). On the other hand, if the transmission completion waiting time has not elapsed in step S686 (step S686; No), the process in step S687 is skipped and the payout side transmission process is terminated.

  FIG. 71 is a flowchart showing an example of the payout-side error cancellation process executed in step S558 shown in FIG. When the payout-side error canceling process is started, in the payout control microcomputer 150, for example, the CPU 214 first turns on the detection signal from the error canceling switch 73 based on the execution result of the input / output process in step S551 shown in FIG. It is determined whether or not (step S691). At this time, if the detection signal from the error release switch 73 is in an OFF state (step S691; No), the payout side error release processing is ended as it is.

  On the other hand, when the detection signal from the error release switch 73 is on in step S691 (step S691; Yes), it is determined whether or not the main board communication error flag is on (step S692). When the main board communication error flag is on (step S692; Yes), the main board communication error flag is cleared and turned off (step S693). Subsequently, it is determined whether or not the serial communication error flag provided in the payout control flag setting unit 141 is on (step S694). At this time, if the serial communication error flag is on (step S694; Yes), the serial communication circuit 218 is initialized by executing a predetermined serial communication initial setting process (step S695). Here, the serial communication initial setting process executed in step S695 is the same as the serial communication initial setting process executed in step S26 shown in FIG. 30 or step S485 shown in FIG. Any suitable process may be used. When the process of step S695 is executed, the serial communication error flag provided in the payout control flag setting unit 141 is cleared and turned off (step S696).

  Further, when the main board communication error flag is off in step S692 (step S692; No), the serial communication error flag is off in step S694 (step S694; No), or the process of step S696 is performed. After the execution, it is determined whether any other error that can be canceled by operating the error cancellation switch 73 has occurred (step S697). As a specific example, in the process of step S697, whether or not predetermined error flags such as a ball biting error flag, a ball clogging error flag, and an empty error flag provided in the payout control flag setting unit 141 are on. If any one of the error flags is on, it is determined that an error that can be canceled by operating the error cancellation switch 73 has occurred.

  When it is determined in step S697 that a resolvable error has occurred (step S697; Yes), for example, the corresponding error flag is cleared or the drive control of the dispensing motor 51 is performed. Settings for canceling the error are performed (step S698). On the other hand, when it is determined in step S697 that no error that can be canceled has occurred (step S697; No), the process in step S698 is skipped, and the payout-side error cancellation process is terminated.

  Next, the operation in the effect control board 12 will be described. In the effect control board 12, the effect control microcomputer 120 is activated in response to the start of power supply from the power supply board 10 and the reset signal to the effect control microcomputer 120 becoming high level (off state). The effect control main process as shown in the flowchart of FIG. 72 is executed. When the effect control main process shown in FIG. 72 is started, the effect control microcomputer 120 first initializes the RAM 122, sets various initial values, and performs timer initialization to determine the execution control execution interval. Processing is executed (step S901). Thereafter, the effect control microcomputer 120 determines whether or not a timer interrupt has occurred, for example, by monitoring a timer interrupt flag (step S902). Until a timer interrupt occurs (step S902; No), the process enters a loop process that repeatedly executes the process of step S902. When a timer interrupt occurs (step S902; Yes), after clearing the timer interrupt flag to turn it off (step S903), the following effect control process is executed.

  Here, the timer interruption in the production control microcomputer 120 occurs, for example, every 2 milliseconds. That is, the effect control process is executed every 2 milliseconds, for example. In this embodiment, when a predetermined timer interrupt process is executed in response to the occurrence of a timer interrupt, the timer interrupt flag is set to the on state, and the specific effect control process is executed in the effect control main process. Is done. On the other hand, the effect control process may be executed in the timer interrupt process.

  In the effect control process, the effect control microcomputer 120 first executes an effect command analysis process for analyzing an effect control command received by the CPU 123 from the main board 11 via the relay board 18 (step S904). Subsequently, in the effect control microcomputer 120, for example, the CPU 123 executes effect control process processing (step S905). In the effect control process, various processes are selected and executed in accordance with control states of the image display device 5, speakers 8L and 8R, game effect lamps 9 and the like that are electric parts for effects. Thereafter, a random number update process for updating various random numbers counted in the effect control microcomputer 120 is executed (step S906). Furthermore, a notification process for controlling a notification operation based on a notification instruction by a production control command from the main board 11 is executed (step S907).

  FIG. 73 is a flowchart showing an example of the effect control process executed in step S905 shown in FIG. In the effect control process 120, in the effect control microcomputer 120, for example, the CPU 123 performs the following step S920 in accordance with the value of the effect control process flag provided in a predetermined area (such as an effect control flag setting area) of the RAM 122. Each process of S925 is executed.

  The variable display start command reception waiting process in step S920 is executed when the value of the effect control process flag is “0”. In the variable display start command reception waiting process, the effect control microcomputer 120 determines whether, for example, the CPU 123 has received a variable display start command transmitted from the main board 11. When the variable display start command has not been received, the variable display start command reception waiting process is terminated. On the other hand, when the variable display start command is received, the value of the effect control process flag is updated to “1”.

  The effect display control setting process in step S921 is executed when the value of the effect control process flag is “1”. This effect display control setting process corresponds to the fact that the special symbol is variably displayed in the special symbol game by the special symbol display device 4, and the effect by various displays including the variable display of the decorative symbol on the image display device 5. In order to perform the above, processing for setting the display operation of the image display device 5 is included. As a specific example, in the effect display control setting process in step S921, first, it is determined whether or not the variable display pattern designated by the variable display start command from the main board 11 is a big hit pattern, and is not a big hit pattern. Is determined, it is determined whether or not it is a reach loss pattern. When it is determined that the pattern is not the reach lose pattern, it is determined that the normal lose pattern is designated, and the normal lose symbol determination process for determining the fixed decorative symbol that is the normal lose combination is executed. Further, when the variable display pattern designated by the variable display start command is a reach lose pattern, a reach lose symbol determination process for determining a definite decorative symbol to be a reach lose combination is executed.

  Further, when the variable display pattern designated by the variable display start command is a big hit pattern, a big hit symbol determination process for determining a confirmed decorative symbol to be a big hit combination is executed. At this time, for example, the CPU 123 reads a display result notification command transmitted from the main board 11 to determine whether the gaming state is a probable big hit that becomes a high probability state or a normal big hit that does not become a high probability state. To do. Then, when it is determined that the probability variation is a big hit, for example, the same probability variation among the decorative symbols “1”, “3”, “5”, “7” or “9” as the probability variation symbol having an odd symbol number. The symbol is determined to be a definite decorative symbol that is derived and displayed on each of the “left”, “middle”, and “right” variable display units as a display result in the variable display of the decorative symbol on the image display device 5. On the other hand, when it is determined that it is a normal big hit, for example, the same normal among the decorative symbols “0”, “2”, “4”, “6” or “8” as a normal symbol having an even symbol number The symbol is determined to be a definite decorative symbol that is derived and displayed on each of the “left”, “middle”, and “right” variable display units as a display result in the variable display of the decorative symbol on the image display device 5.

  After determining the final decorative symbol by executing these processes, in the effect display control setting process, the symbol display control pattern corresponding to the variable display pattern designated by the variable display start command is determined, and the symbol display control pattern is determined. For example, a drawing command corresponding to is sent to the VDP, and settings for starting the variable display of decorative symbols are performed. At this time, a timer setting for measuring the variable display time of the decorative symbols is also performed corresponding to the symbol display control pattern. Thereafter, the value of the effect control process flag is updated to “2”, and the effect display control setting process ends.

  The decorative symbol variable display process in step S922 is executed when the value of the effect control process flag is “2”. In this decorative symbol variable display processing, for example, the reading position in the symbol display control pattern is switched in accordance with the elapsed time since the decorative symbol variable display was started, and drawing corresponding to the display control data read from the reading position is performed. The display operation in the image display device 5 is controlled by sending a command to the VDP. Then, when the timing to end the variable display of the decorative symbols is reached, the big hit start command reception waiting time is set and the value of the effect control process flag is updated to “3”.

  The decorative symbol stop process in step S923 is executed when the value of the effect control process flag is “3”. In this decorative symbol stop process, it is determined whether or not the jackpot start command transmitted from the main board 11 has been received. When the big hit start command reception waiting time has elapsed without receiving the big hit start command, it is determined that the decorative symbol variable display result is lost, and the value of the effect control process flag is updated to “0”. Further, when it is determined that the jackpot start command has been received in the decorative symbol stop process, it is determined that the variable symbol display result is a big bonus and the value of the effect control process flag is updated to “4”. To do.

  The big hit effect process in step S924 is executed when the value of the effect control process flag is “4”. In the jackpot effect process, the display operation in the image display device 5 is controlled to perform control to display an image corresponding to the jackpot gaming state. Then, it is determined whether or not a big hit end command has been received from the main board 11, and when it is determined that it has been received, the value of the effect control process flag is updated to “5”.

  The big hit end effect process in step S925 is executed when the value of the effect control process flag is “5”. The jackpot end effect process includes a process of performing control for executing an effect display for notifying that the jackpot game state has ended on the image display device 5. Thereafter, when the various effect displays are finished, the value of the effect control process flag is updated to “0”.

  74 and 75 are flowcharts showing an example of the notification process executed in step S907 shown in FIG. When the notification process is started, the effect control microcomputer 120 first determines whether, for example, the CPU 123 has received a recovery notification command from the main board 11 (step S941 in FIG. 74). When a recovery notification command is received (step S941; Yes), settings are made to display on the image display device 5 an image that becomes a recovery screen as exemplified in FIG. 76A (step S942). On the other hand, when the recovery notification command is not received in step S941 (step S941; No), it is determined whether or not the initialization notification command from the main board 11 is received (step S943). At this time, if an initialization notification command has been received (step S943; Yes), an image that becomes an initialization screen as illustrated in FIG. Settings for displaying the symbol stop display image) on the image display device 5 are performed (step S944).

  In the production control microcomputer 120, for example, after the CPU 123 performs setting to display the recovery screen and the initialization screen, the display is deleted when a predetermined display period elapses. Also good. Alternatively, after the display of the recovery screen or the initialization screen is started, the display may be continuously performed until the variable display start command is received from the main board 11. When the display is erased when a predetermined display period elapses, a predetermined image serving as a demonstration screen may be displayed on the image display device 5 thereafter. Even when the display is erased when a predetermined display period elapses, when the variable display start command is received from the main board 11 before the display period elapses, the variable display start is performed. What is necessary is just to be able to start the variable display of the decorative design based on having received the command.

  When the initialization notification command is not received in step S943 (step S943; No), or after performing any of the processes of steps S942 and S944, whether or not a serial communication error is notified is determined. For example, the CPU 123 makes a determination by checking a predetermined notification flag (step S945). At this time, if the serial communication error is notified (step S945; Yes), it is determined whether a serial communication abnormality notification end command is received from the main board 11 (step S946). If the serial communication abnormality notification end command has not been received (step S946; No), the notification processing ends. On the other hand, when the serial communication abnormality notification end command is received in step S946 (step S946; Yes), the operation for notifying the occurrence of the serial communication abnormality such as the setting for initializing the display operation in the image display device 5 is ended. The setting for making this is performed (step S947).

  When it is determined in step S945 that the serial communication error is not notified (step S945; No), after executing the process of step S947, a serial communication abnormality notification start command from the main board 11 is issued. It is determined whether or not it has been received (step S948). Then, when the serial communication abnormality notification start command is received (step S948; Yes), a setting for causing the image display device 5 to display an image serving as a serial communication abnormality notification screen as illustrated in FIG. 76C is performed. (Step S949).

  When the serial communication abnormality notification start command is not received in step S948 (step S948; No), notification of abnormality occurrence (main-side payout abnormality notification) related to payout control on the main board 11 side (main side) is performed. For example, the CPU 123 determines whether or not the CPU 123 checks a predetermined notification flag (step S950). At this time, if the main-side payout abnormality notification has been performed (step S950; Yes), it is determined whether or not the main-side payout abnormality notification end command has been received from the main board 11 (step S951). At this time, if the main payout abnormality notification end command has not been received (step S951; No), the notification processing is ended. On the other hand, when the main-side payout abnormality notification end command is received in step S951 (step S951; Yes), for example, the main-side payout abnormality notification such as setting for initializing the display operation in the image display device 5 is ended. Setting is performed (step S952).

  When it is determined in step S950 that the main-side payout abnormality notification is not performed (step S950; No), after executing the process of step S952, the main-side payout abnormality notification start command from the main board 11 is executed. Is determined (step S953). Then, when a main-side payout abnormality notification start command is received (step S953; Yes), a setting for causing the image display device 5 to display an image serving as a main-side payout abnormality notification screen as illustrated in FIG. Is performed (step S954).

  When the main-side payout abnormality notification start command is not received in step S953 (step S953; No), notification of abnormality occurrence (payout-side abnormality notification) related to various controls on the payout control board 15 side (payout side) is performed. For example, the CPU 123 determines whether or not the CPU 123 checks a predetermined notification flag (step S955 in FIG. 75). At this time, if the payout side abnormality notification has been performed (step S955; Yes), it is determined whether or not a payout side abnormality notification end command has been received from the main board 11 (step S956). At this time, if the payout side abnormality notification end command is not received (step S956; No), the notification processing is ended. On the other hand, when a payout side abnormality notification end command is received in step S956 (step S956; Yes), for example, a setting for ending the payout side abnormality notification such as a setting for initializing the display operation in the image display device 5 is performed. This is performed (step S957).

  When it is determined in step S955 that the payout side abnormality notification is not performed (step S955; No), after executing the process of step S957, a payout side abnormality notification start command is received from the main board 11. It is determined whether it has been done (step S958). Then, when a payout side abnormality notification start command is received (step S958; Yes), a setting for causing the image display device 5 to display an image serving as a payout side abnormality notification screen as illustrated in FIG. (Step S959).

  When the payout side abnormality notification start command is not received in step S958 (step S958; No), it is determined whether notification of excessive prize balls or insufficient prize balls is performed (step S960). Then, when it is determined that the notification of excessive prize balls or insufficient prize balls is being made (step S960; Yes), for example, an elapsed time that is provided in a predetermined area of the RAM 122 or the like and ends the notification is measured. For example, the timer value in the notification timer is updated by, for example, subtracting 1 (step S961). Then, based on the value of the notification timer updated in step S961, it is determined whether or not the timing for ending notification of excessive prize balls or insufficient prize balls has been reached (step S962). At this time, if the timing to end the notification has not been reached (step S962; No), the notification processing is ended. On the other hand, if the timing to end the notification in step S962 has been reached (step S962; Yes), for example, notification of excessive prize balls or insufficient prize balls, such as a setting for initializing the display operation in the image display device 5, is ended. Is set (step S963).

  When it is determined in step S960 that there is no notification of excessive prize balls or insufficient prize balls (step S960; No), after executing the process of step S963, excessive prize balls from the main board 11 are used. It is determined whether a command has been received (step S964). When receiving an excessive prize ball command (step S964; Yes), the image display device 5 displays an image serving as an excessive prize ball notification screen as illustrated in FIG. Is set to start (step S965). At this time, the timer initial value indicating the notification time corresponding to the notification of excessive prize balls is set in the notification timer (step S966).

  Further, when the excessive prize ball command is not received in step S964 (step S964; No), it is determined whether or not a prize ball shortage command from the main board 11 is received (step S967). When the prize ball shortage command is received (step S967; Yes), the image display device 5 displays an image that becomes a prize ball shortage notification screen as illustrated in FIG. Is set to start (step S968). At this time, the timer initial value indicating the notification time corresponding to the notification of the shortage of prize balls is set in the notification timer (step S969). When no prize ball shortage command is received in step S967 (step S967; No), the notification process is terminated without executing the processes of steps S968 and S969.

  Next, a specific operation example of the random number circuit 103 provided in the game control microcomputer 100 will be described. FIG. 77 is a timing chart for explaining the operation of the random number circuit 103. An internal system clock CLK as shown in FIG. 77A is input to the clock input terminal of the clock signal output circuit 171 and the clock input terminal of the timer circuit 179 provided in the random number circuit 103. The internal system clock CLK may be generated by the clock circuit 101 provided in the game control microcomputer 100. As shown in FIG. 77 (A), the internal system clock CLK is a clock signal that rises from a low level to a high level at timings T11, T21,.

  The clock signal output circuit 171 divides the internal system clock CLK and rises from a low level to a high level at timings T11, T12,..., And falls from a high level to a low level at timings T21, T22,. A clock signal S1 shown in 77 (B) is generated. In the operation example shown in FIG. 77, for the sake of explanation, a case where the clock signal output circuit 171 generates the clock signal S1 by dividing the internal system clock CLK by two is shown. However, in practice, as a cycle for updating the 16-bit random number, either the cycle of the internal system clock CLK or a cycle 16 times the internal system clock CLK is set. Therefore, the clock signal output circuit 171 only needs to be able to switch between outputting the internal system clock CLK as it is as the clock signal S1 and outputting the signal obtained by dividing the internal system clock CLK by 16 as the clock signal S1. . The clock signal S1 output from the clock signal output circuit 171 is input to a random number generation circuit 173B and an inverting circuit 178 provided for generating a 16-bit random number.

  The random number generation circuit 173B updates the numerical data C2 in response to the rising edge of the clock signal S1 input to the clock input terminal, and outputs the numerical data C2 to the random number sequence change circuit 176B. The inversion circuit 178 inverts the signal level of the clock signal S1 output from the clock signal output circuit 171 to fall from a high level to a low level at timings T11, T12,..., And at timings T21, T22,. An inverted clock signal S2 as shown in FIG. 77C that rises from a low level to a high level is generated. The inverted clock signal S2 generated by the inverter circuit 178 is output from the inverter circuit 178 and input to the latch signal generator circuit 180.

  When the start winning signal SS shown in FIG. 77D is input to the timer circuit 179, when the elapsed time from the rising edge reaches a predetermined time (for example, 3 milliseconds), the output signal from the timer circuit 179 is low. Rise from level to high level. The output signal from the timer circuit 179 is input to the latch signal generation circuit 180, and is output as a latch signal SL as shown in FIG. 77 (E) in synchronization with the rising edge of the inverted clock signal S2. As a result, the random number generation circuit 173B updates the numerical data C1 at timings T11, T12,..., While the latch signal generation circuit 180 outputs a latch signal SL that rises at a timing T22 different from the timings T11, T12,. Can do. Here, the operation in which the random number sequence change circuit 176B changes the arrangement of the numerical data C2 output from the random number generation circuit 173B, and the numerical value data R2 that becomes the random value output from the random number sequence change circuit 176B by the maximum value comparison circuit 177B. Is performed within a period sufficiently shorter than the cycle of the internal system clock CLK by performing the operation of repeating the resetting until a value equal to or less than the maximum value is compared with the predetermined maximum value, from the maximum value comparison circuit 177B. In the random value register 181B, the numerical data R2 that is the updated random value is output within a sufficiently short elapsed time from the rising edge of the clock signal S1. Then, the latch signal SL rises from the low level to the high level in synchronization with the inverted clock signal S2, so that the numerical data R2 that becomes the updated random number value can be reliably and stably acquired.

  As described above, in the pachinko gaming machine 1 in the above embodiment, when the power supply is started, the gaming control microcomputer 100 is in the on state in step S7 shown in FIG. After determining whether or not, based on the setting in step S9, after waiting for a predetermined delay time in steps S10 and S11, it is possible to execute a game control process for controlling the progress of the game To do. The delay time here is set to be delayed from when the game control process can be executed until at least the execution of various payout control processes by the payout control microcomputer 150 is started. ing. Thereby, the game control microcomputer 100 and the payout control microcomputer 150 execute the initialization process for surely performing the setting at the time of initialization according to the operation on the clear switch 304 mounted on the power supply board 10. It is possible to prevent the control state from becoming inconsistent. In addition, since the execution of the game control process by the game control microcomputer 100 is started after the various processes for the payout control by the payout control microcomputer 150 are started, the payout control microcomputer 150 is used for the game control microcomputer. The payout control command from the computer 100 can be reliably received.

  In addition, similarly to the payout control microcomputer 150, the effect control microcomputer 120 mounted on the effect control board 12 does not execute delay processing when power supply to the pachinko gaming machine 1 is started. Therefore, the game control process is started after the control by the production control microcomputer 120 is started. Therefore, when the production control command (for example, the initialization notification command or the recovery notification command) is transmitted from the main board 11 to the production control board 12, the production control microcomputer 120 surely receives and receives the command. A notification process based on the command (for example, a process for causing the image display device 5 to display an image serving as a restoration screen shown in FIG. 76A or an initialization screen shown in FIG. 76B) can be executed.

  Further, in the game control microcomputer 100, for example, the CPU 104 confirms the state of the clear signal in step S7 before executing the delay processing based on the setting in step S9. It is possible to reduce the possibility that the control states cannot be matched.

  Also, a serial status register 204 (third to zeroth bits [bits 3-0] of the first register SIST1) indicating an error occurrence in the serial communication circuit 108 such as an overrun error, noise error, framing error, parity error, etc. And the setting of the error generation serial control register 205 (third to zeroth bits [bit 3-1] of the third register SICL3) indicating the setting of interrupt generation corresponding to the occurrence of an error in the serial communication circuit 108 When the error interrupt request is notified to the CPU 104, for example, the CPU 104 executes the processing of steps S41 and S42 shown in FIG. 37 to set the transmission operation unit 202 and the reception operation unit 201 included in the serial communication circuit 108 to an unused state. The serial communication circuit 108 You can immediately stop the Le communication operation. Thereby, it is possible to prevent erroneous information from being transmitted due to the occurrence of an abnormality in serial communication.

  In the game control microcomputer 100, for example, the CPU 104 transmits any one of the first to third payout number designation commands to the payout control board 15 according to the setting in any one of steps S308, S310, and S311 shown in FIG. Thereafter, when it is determined in step S335 shown in FIG. 46 that the winning ball ACK waiting time has elapsed, the payout number designation command is retransmitted by setting the retransmission flag to an ON state in step S336. Thereby, when it is determined that the payout number designation command is not received by the payout control microcomputer 150 mounted on the payout control board 15, the payout control is hindered by retransmitting the payout number designation command. In this way, the disadvantage of the player can be prevented. Further, when it is determined in step S275 shown in FIG. 48 that the re-transmission flag is on, if it is determined in step S277 that the payout abnormality notification flag is off, the main side payout abnormality is determined by the setting in step S278. A notification start command is transmitted to the effect control board 12. When it is determined in step S953 shown in FIG. 74 that the production control microcomputer 120 has received the main-side payout abnormality notification start command from the main board 11, the setting in step S954 causes the setting shown in FIG. The image display device 5 displays an image serving as a main-side payout abnormality notification screen as illustrated in FIG. Thereby, the abnormality of communication regarding payout control can be easily recognized outside the pachinko gaming machine 1.

  In the payout control microcomputer 150, for example, after the CPU 214 transmits the prize ball ACK command to the main board 11 by the setting in step S634 shown in FIG. 59, it is determined in step S643 that the feedback waiting time has elapsed. In step S644, the main board communication error flag is set to ON. When the main board communication error flag is turned on in this way, the process of step S721 shown in FIG. 62 is executed, so that the process after step S722 is not executed and the payout control normal process ends, and FIG. When the process of step S801 shown in FIG. 5 is executed, the award ball payout number calculation process is terminated without executing the process of step S802 and subsequent steps. For this reason, when it is determined that the ACK feedback command from the main board 11 has not been received, the value of the prize ball non-payout counter becomes a value other than “0”, and the game balls that become unpaid prize balls Even if it shows that there exists, it will be controlled to the state which stops payout control. Thereby, reliable payout control is executed, and it is possible to prevent excessively paying out game balls as prize balls when, for example, an abnormality due to a communication error or an illegal act on a communication line occurs.

  Further, in the payout control microcomputer 150, for example, when the CPU 124 sets the main board communication error flag to the ON state in step S644 shown in FIG. 59, the processing in step S601 shown in FIG. The payout side reception process is terminated without executing the processes after S602. For this reason, when it is determined that the ACK feedback command from the main board 11 has not been received, control is performed to stop receiving the payout number designation command transmitted from the main board 11. Thereby, reliable payout control is executed, and it is possible to prevent excessively paying out game balls as prize balls when, for example, an abnormality due to a communication error or an illegal act on a communication line occurs.

  In the payout control microcomputer 150, for example, when the CPU 214 executes a payout side error canceling process as shown in FIG. 71 to operate the error canceling switch 73 and output an error canceling signal, various error flags are displayed. The state in which the payout control is prohibited can be canceled by clearing and setting the state to the off state. Thereby, for example, after a game store clerk performs an inspection for abnormality, the game can be continued while maintaining the control state before the inspection.

  When power supply to the pachinko gaming machine 1 is started, in the gaming control microcomputer 100, for example, the CPU 104 executes an interrupt initial setting process as shown in FIG. 35 in step S27 shown in FIG. By reading the highest priority interrupt setting (KHPR) stored in the ROM 105 and setting the highest priority interrupt based on the read value, the priority of interrupt processing is changed from the default setting shown in FIG. can do. Thereafter, for example, when the CPU 104 executes the process of step S28 shown in FIG. 30, the game control microcomputer 100 is set in the interrupt permitted state. In the payout control microcomputer 150, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 214 executes a process similar to the process shown in FIG. 35 in step S519 shown in FIG. By reading the highest priority interrupt setting (KHPR) stored in the ROM 215 and setting the highest priority interrupt based on the read value, the priority order of the interrupt processing is changed from the default setting shown in FIG. Can be changed. Thereafter, for example, the CPU 214 executes the process of step S520 shown in FIG. 54, whereby the payout control microcomputer 150 is set in the interrupt permitted state. Thereby, after the execution of the interrupt process is permitted, the interrupt process can be surely executed according to the changed priority order. In addition, by changing the priority of interrupt processing from the initial setting before the execution of interrupt processing is permitted, a program that controls interrupt processing to be executed according to a predetermined priority every time various interrupts occur Since there is no need to execute, the degree of freedom in design can be increased.

  In the setting of the highest priority interrupt by executing the processing of step S142 shown in FIG. 35, for example, in response to the highest priority interrupt setting data as shown in FIG. The priority order with respect to the interrupt processing based on the interrupt request notified from the communication circuit 108 can be set. Thereby, after the execution of the interrupt process is permitted, the interrupt process can be surely executed according to the set priority order. In addition, by enabling the priority of interrupt processing to be arbitrarily set before execution of interrupt processing is permitted, a program that controls interrupt processing to be executed according to a predetermined priority every time various interrupts occur Since it is possible to preferentially execute any predetermined interrupt processing, the degree of freedom in design can be increased.

  In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, before the CPU 104 determines whether or not the clear signal is on in step S7 shown in FIG. It is determined whether or not the power-off signal output from the power supply monitoring circuit 303 mounted on the power supply substrate 10 has been turned off in the process of step S5 executed at step S5. Then, after the power-off signal is turned off, it is determined whether or not the clear signal is turned on in step S7. Further, when the supply of power to the pachinko gaming machine 1 is started, the payout control microcomputer 150 also determines, for example, whether or not the clear signal is on in step S508 shown in FIG. In the process of step S505 executed before, it is determined whether or not the power-off signal from the power supply board 10 has been turned off, and the process proceeds to step S508 after being turned off. Thus, by checking the state of the clear signal after the stability of the power supply voltage supplied from the power supply substrate 10 is confirmed, the output state of the clear signal (on state or off state) is ensured. For example, it can be detected that the clear signal is on even though the clear signal is off, or it can be detected that the clear signal is off even though the clear signal is on. It is possible to prevent erroneous detection such as.

  As shown in FIG. 4, the power supply monitoring circuit 303 is mounted on the power supply board 10. The power-off signal output from the power supply monitoring circuit 303 is input to the payout control board 15 and then transmitted from the payout control board 15 to the main board 11. Thereby, compared with the case where the wiring for transmitting a power-off signal is connected from the power supply board 10 to both the payout control board 15 and the main board 11, the wiring configuration can be simplified and the cost of the pachinko gaming machine 1 can be reduced. be able to. As shown in FIG. 6, the power supply board 10 and the payout control board 15 are installed in the gaming machine frame 3, while the main board 11 is installed in the gaming board 2. As a result, the wiring configuration for transmitting the power-off signal from the power supply substrate 10 can be simplified, and the wiring length can be shortened to make it less susceptible to noise.

  When the power supply to the pachinko gaming machine 1 is started, in the gaming control microcomputer 100, for example, the CPU 104 stores the first random number initial setting data (KRSS1) stored in the ROM 105 in step S24 shown in FIG. 4 and the third bit [bit 4-3] are read out, and the setting for generating random numbers in the random number circuit 103 is performed by executing the processing of step S25 based on the read value. Thereafter, the game control microcomputer 100 is set to the interrupt-permitted state, for example, by the CPU 104 executing the process of step S28. The processes executed in step S25 include a 12-bit random number initial setting process as shown in FIG. 32 and a 16-bit random number initial setting process as shown in FIG. In the 12-bit random number initial setting process shown in FIG. 32, the CPU 104 reads the seventh bit [bit 7] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S101, and the read value is “1”. , The start value for the first round for generating a 12-bit random number in the random number circuit 103 by executing the process of step S104 is a unique identification number assigned to each game control microcomputer 100. It is determined based on a certain ID number. In the 16-bit random number initial setting process shown in FIG. 33, the CPU 104 reads the fourth bit [bit 4] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S123, and the read value is “ When it is 1 ″, the unique identification given to each game control microcomputer 100 is the first round start value for generating a 16-bit random number in the random number circuit 103 by executing the processing of step S126. It is determined based on the ID number which is a number. Thereby, the initial value of the random number that is updated after the power supply is started can be made different in each of the plurality of pachinko gaming machines 1, and the special symbol display device using the random value generated in this way By determining whether or not the variable display result in a special game such as 4 is a big hit, it is possible to improve randomness of random numbers and prevent a big hit from being generated illegally.

  The random number circuit 103 provided in the game control microcomputer 100 is configured to include a plurality of circuits for generating random numbers having different numerical data update ranges, such as a 12-bit random number and a 16-bit random number. ing. In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 104 stores first random number initial setting data (KRSS1) stored in the ROM 105 in step S24 shown in FIG. 4 and 3rd bits [bits 4-3] are read out, and as a process in step S25 based on the read values, a 12-bit random number initial setting process shown in FIG. 32 and a 16-bit random number initial setting process shown in FIG. 33 are performed. Make it executable. Then, the 12-bit random number initial setting process shown in FIG. 32 is executed, so that the random number circuit 103 can generate a 12-bit random number. The 16-bit random number initial setting process shown in FIG. The circuit 103 can generate a 16-bit random number. On the other hand, when the 12-bit random number initial setting process is not executed as the process in step S25, the process for stopping the generation operation for the 12-bit random number in the random number circuit 103 is executed, and the 16-bit random number initial setting process is executed as the process in step S25. Is not executed, the processing of stopping the generation operation for the 16-bit random number in the random number circuit 103 is executed, thereby stopping the function of the circuit that generates a random number having a different update range from the set random number. it can. Thereby, the circuit corresponding to the random number used according to various determinations is set, for example, whether or not the variable display result in the special symbol game by the special symbol display device 4 is a big hit, and the determination is made. Can reduce the processing load required.

  In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 104 reads the 12-bit random number maximum value (KRMS) stored in the ROM 105 in step S107 shown in FIG. In step S108, it is determined whether or not the read value is within a range that can be set as the maximum value for a 12-bit random number. Then, when it is determined in step S108 that it is not within the settable range, a predetermined value within the range that can be set as the maximum value for 12-bit random numbers is reset in step S110. Also, for example, the CPU 104 reads the 16-bit random number maximum value (KRXS) stored in the ROM 105 in step S129 shown in FIG. 33, and whether or not the read value is within a range that can be set as the maximum value for 16-bit random numbers. Is determined in step S130. When it is determined in step S130 that it is not within the settable range, a predetermined value within the range that can be set as the maximum value for 16-bit random numbers is reset in step S132. Thereby, the use range of the random number value can be set in detail, the processing load required for the determination can be reduced, and the random number can be prevented from being updated in an extremely narrow range due to malfunction or fraud.

  In the random number circuit 103, for example, the random number generation circuit 173A provided for the 12-bit random number responds to the fact that the stored value update signal KT from the random number register 181A rises from the low level to the high level, and the numerical data C1 Update. On the other hand, the random number generation circuit 173B provided for the 16-bit random number updates the numerical data C2 in response to the rise of the clock signal S1 from the clock signal output circuit 171 from the low level to the high level. . The cycle of the clock signal S1 output from the clock signal output circuit 171 is set according to the setting in the second bit [bit 2] of the first random number initial setting data (KRSS1) stored in the ROM 105. By setting either the cycle of CLK or a cycle 16 times the internal system clock CLK, the cycle in which the random number generation circuit 173B updates the numerical data C2 can be set to any of a plurality of types of cycles. As described above, the random number circuit 103 can update the numerical data C1 used to generate a 12-bit random number and the numerical data C2 used to generate a 16-bit random number by any of a plurality of update methods. it can. In the game control microcomputer 100, for example, the CPU 104 reads the second bit [bit 2] of the first random number initial setting data (KRSS1) stored in the ROM 105 in step S121 shown in FIG. 33, and based on the read value. In step S122, operation setting in the clock signal output circuit 171 provided in the random number circuit 103 is performed. As a result, the randomness update method can be made different to increase the randomness of the random numbers.

  In the process of step S104 shown in FIG. 32 and the process of step S126 shown in FIG. 33, for example, an operation for performing a predetermined scramble process on a unique ID number assigned to each game control microcomputer 100, The calculated value can be set as a start value for generating a 12-bit random number or a 16-bit random number by executing the operations such as addition / subtraction / multiplication / division used. Thereby, the initial value of the random number that is updated after the power supply is started can be made different in each of the plurality of pachinko gaming machines 1, and the special symbol display device using the random value generated in this way By determining whether or not the variable display result in a special game such as 4 is a big hit, it is possible to improve randomness of random numbers and prevent a big hit from being generated illegally. In addition, since it becomes difficult to specify the start value from the unique identification number assigned to each game control microcomputer 100, it is possible to more reliably prevent the jackpot from being illegally generated. .

  In the gaming control microcomputer 100, when power supply to the pachinko gaming machine 1 is started, for example, the CPU 104 stores the second random number initial setting data (KRSS2) stored in the ROM 105 in step S105 shown in FIG. The 6th and 5th bits [bits 6-5] are read, and based on the read value, the selection operation is set in the selector 174A provided in the random number circuit 103 as a 12-bit random number selector in step S106. Accordingly, in the first method in which the permutation, which is the update order when the random number sequence changing circuit 176A updates the numerical data R1 for the 12-bit random number, is automatically changed after the second round, and after the second round. It can be changed by the second method that can be changed by the user program. Or it can also be set as the 3rd system which is not changed after the 2nd round. Further, for example, the CPU 104 reads the first and 0th bits [bits 1-0] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S127 shown in FIG. In step S128, the selection operation in the selector 174B provided in the random number circuit 103 as a bit random number selector is set. Accordingly, in the first method in which the permutation, which is the update order when the random number sequence changing circuit 176B updates the numerical data R2 for 16-bit random numbers, is automatically changed in the second and subsequent rounds, and in the second and subsequent rounds. It can be changed by the second method that can be changed by the user program. Or it can also be set as the 3rd system which is not changed after the 2nd round. Then, when the second system that can be changed by the user program is set in the second round and thereafter, for example, the CPU 104 sets “0” to the 0th bit [bit 0] of the ARSC 175A in step S234 shown in FIG. Or, by setting “1” to the 0th bit [bit 0] of BRSC 175B in step S239 shown in FIG. 43, the numerical permutation change data is set. In the random number circuit 103, for example, when the second method is selected by the selector 174A, the numerical value permutation change data set in the ARSC 175A is read by the random number sequence change circuit 176A, and the numerical data output from the random number generation circuit 173A In response to the value of the column C1 reaching a predetermined final value, the update rule for determining the permutation of the numerical data C1 is changed. For example, when the second method is selected by the selector 174B, the numerical permutation change data set in the BRSC 175B is read by the random number sequence change circuit 176B, and the numerical data sequence C2 output from the random number generation circuit 173B is read. In response to the value reaching a predetermined final value, the update rule that determines the permutation of the numerical data C2 is changed. Thereby, when the numerical data C1 and the numerical data C2 are updated from a predetermined initial value to a predetermined final value, the permutation can be changed variously to increase randomness of random numbers.

  In the gaming control microcomputer 100, for example, the CPU 104 reads the first and 0th bits [bits 1-0] of the first random number initial setting data (KRSS1) stored in the ROM 105 in step S202 shown in FIG. When any one of the processes of steps S204, S208, and S211 is performed based on the read value, the random number circuit 103 is set to change the start value in the numerical data C1 used to generate a 12-bit random number. Further, for example, the CPU 104 reads out the third and second bits [bit 3-2] of the second random number initial setting data (KRSS2) stored in the ROM 105 in step S214 shown in FIG. 42, and performs steps based on the read value. When one of the processes of S216, S220, and S223 is executed, the random number circuit 103 is set to change the start value in the numerical data C2 used for generating a 16-bit random number. In the random number circuit 103, when the random number generation circuit 173A provided for the 12-bit random number updates the numerical data up to a predetermined final value, the random number circuit RIJ1 is output, while the random number generation circuit 173B provided for the 16-bit random number. When the numerical data is updated to a predetermined final value, a random number round-trip signal RIJ2 is output. Then, when the random number generation circuit 173A outputs the random number round circuit RIJ1, for example, the initial value setting circuit 172A sets the start value set by the CPU 104 in the random number generation circuit 173A, while the random number generation circuit 173B receives the random number round circuit RIJ2. When the data is output, for example, the initial value setting circuit 172B sets the start value set by the CPU 104 in the random number generation circuit 173B, whereby the start value for generating a 12-bit random number or a 16-bit random number can be changed. As a result, when the numerical data C1 and the numerical data C2 are updated from a predetermined initial value to a predetermined final value, the start value that is the initial value in the next cycle is changed to increase the randomness of the random number. it can.

  The start port switch 22 detects that a game ball has won a start winning port, and outputs a start winning signal indicating that a start condition for executing the special symbol game by the special symbol display device 4 is satisfied. In the random number circuit 103, the start winning signal output from the start port switch 22 is input to the timer circuit 179, and the output signal from the timer circuit 179 is input to the latch signal generation circuit 180, whereby the start winning signal is generated. The latch signal SL can be output in response to the output. The timer circuit 179 measures the input time of the start winning signal SS, and when the measured time reaches a preset time (3 milliseconds), the output signal is raised from the low level to the high level. The latch signal generation circuit 180 outputs the output signal from the timer circuit 179 as the latch signal SL in synchronization with the inverted clock signal S2 output from the inverter circuit 178. For this reason, the pachinko gaming machine 1 can prevent the latch signal generation circuit 180 from erroneously outputting the latch signal SL to the random value register 181B due to the influence of noise or the like. In addition, since the timer circuit 179 is set to “3 milliseconds” shorter than the execution period “4 milliseconds” of the two timer interruption processes, the random number value read by the CPU 104 from the random value register 181B this time is set. Can be prevented from becoming the same value as the previously read random number value.

  In the random number circuit 103, for example, from the predetermined initial value to the predetermined final value in a predetermined range in which the numerical data C2 can be updated based on the input of the clock signal S1 input from the clock signal output circuit 171 by the random number generation circuit 173B. The data is updated cyclically according to a predetermined order (for example, an order of “1 → 2 →... → 65535”). On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 according to the input of the start winning signal SS as the latch signal SL in synchronization with the inverted clock signal S2 output by the inverter circuit 178. Output. Thereby, acquisition of a random number value can be performed reliably and stably.

  In the game control microcomputer 100, for example, when the CPU 104 determines in step S321 shown in FIG. 46 that the prize ball ACK reception flag is on, the command transmission count counter is incremented by 1 in step S325. On the other hand, when it is determined in step S261 shown in FIG. 48 that the detection signal from the all winning ball detection switch 29 is ON, the value of the command transmission number counter is decremented by 1 in step S262. Based on the value of the command transmission number counter, the difference between the number of times one of the first to third payout number designation commands is transmitted and the number of game balls detected according to the detection signal from the all winning ball detection switch 29 is calculated. Identified as the number of winnings. Then, when the process of step S270 shown in FIG. 48 is executed and it is determined that the difference in the number of winnings has reached the excessive ball reference value which is one of the abnormality determination values, the process of step S271 is executed and the excessive number of winning balls is executed. A notification command is transmitted to the effect control board 12. 48, when it is determined that the winning number difference has reached the winning ball shortage reference value, which is one of the abnormality determination values, by executing the processing of step S273, the processing of step S273 is executed. A notification command is transmitted to the effect control board 12. On the side of the production control board 12, when it is determined that the process of step S964 shown in FIG. 75 is executed and the excessive ball notification command is received, the process of step S965 is executed to indicate that excessive prize balls have occurred. Notification. When it is determined that the prize ball shortage notification command is received by executing the process of step S967 shown in FIG. 75, the process of step S968 is executed to notify that the prize ball shortage has occurred. Accordingly, it is possible to detect that an abnormality has occurred in the number of game balls to be paid out as prize balls without directly counting the number of game balls to be paid out as prize balls. In addition, since the number of game balls won in the winning opening is smaller than the number of game balls paid out as prize balls, the amount of data stored can be reduced. Further, it is possible to specify the difference between the number of payout number designation command transmissions and the number of game balls detected by the all winning ball detection switch 29 as a winning number difference by simply updating the count value in one command transmission number counter. Therefore, it is possible to determine whether an abnormality has occurred in the number of game balls to be paid out as prize balls while suppressing an increase in control burden. In addition, since it is only necessary to store the count value in one command transmission number counter, the data storage amount can be reduced as compared with the case where the count values in a plurality of counters are used.

  The game control microcomputer 100 includes the serial communication circuit 108 and the payout control microcomputer 150 includes the serial communication circuit 218, so that bidirectional serial communication can be performed. Then, between the game control microcomputer 100 and the payout control microcomputer 150, for example, as shown in FIG. 8A, a payout control command in which the first byte of the two-byte structure is reversed to the second byte, A payout notification command is generated and transmitted / received. In the game control microcomputer 100, for example, the CPU 104 calculates the exclusive OR of the first byte and the second byte of the received command in step S405 shown in FIG. It is determined whether or not the payout notification command transmitted from the mounted payout control board 15 has been correctly received. On the other hand, in the payout control microcomputer 150, for example, the CPU 214 calculates the exclusive OR of the first byte and the second byte of the received command in step S605 shown in FIG. It is determined whether the payout control command transmitted from the mounted main board 11 has been correctly received. Thereby, the management of commands transmitted and received between the main board 11 and the payout control board 15 becomes easy and reliable, and it is possible to easily and reliably detect an error during command transmission and reception and receive an erroneous command. The game control microcomputer 100 and the payout control microcomputer 150 can be easily matched.

  For example, if the CPU 104 provided in the game control microcomputer 100 determines that the payout notification command has not been correctly received in step S405 shown in FIG. 50, the payout communication error detection flag is turned on in step S406. Therefore, if the payout abnormality notification flag is off in step S277 shown in FIG. 48, a main-side payout abnormality notification start command is sent from the main board 11 to the effect control board 12 based on the setting in step S278. Will be sent. In response to the main-side payout abnormality notification start command, the effect control board 12 executes the process of step S954 shown in FIG. 74, thereby causing a main-side payout abnormality notification screen as illustrated in FIG. Is displayed on the image display device 5. On the other hand, when the CPU 214 provided in the payout control microcomputer 150 determines that the payout control command has not been correctly received in step S605 shown in FIG. 58, the main board communication error flag is set to the on state in step S606. Therefore, a payout error notification command is transmitted from the payout control board 15 to the main board 11 based on the setting in step S673 shown in FIG. Then, in response to the receipt of the payout error notification flag, the main board 11 sets the payout error notification flag to the on state in step S410 shown in FIG. 50, so in step S285 shown in FIG. Based on the setting, a payout side abnormality notification start command is transmitted from the main board 11 to the effect control board 12. In response to the payout-side abnormality notification start command, the effect control board 12 executes the process of step S959 shown in FIG. 75, thereby forming a payout-side abnormality notification screen as illustrated in FIG. Is displayed on the image display device 5. Thereby, when the payout control command and the payout notification command are not correctly transmitted / received, this can be easily recognized outside the pachinko gaming machine 1. In the payout control command and the payout notification command, for example, as shown in FIG. 8A, the first byte of each byte (seventh bit [bit 7]) is used as a header, and the header is made different so that the first byte is changed. Since the second and second bytes can be distinguished, the first and second bytes can be transmitted and received without mistakes.

  As shown in FIG. 4, the clear switch 304 is mounted on the power supply substrate 10. The clear signal output from the clear switch 304 is input to the main board 11 and then transmitted from the main board 11 to the payout control board 15. Thereby, compared with the case where the wiring for transmitting a clear signal is connected from the power supply board 10 to both the main board 11 and the payout control board 15, the wiring configuration can be simplified and the cost of the pachinko gaming machine 1 can be reduced. In addition, the wiring length can be shortened to make it less susceptible to noise.

  In the embodiment described above, the clock signal S1 output from the clock signal output circuit 171 included in the random number circuit 103 is input to the inversion circuit 178, and the inversion circuit 178 inverts the signal level of the clock signal S1. By inputting the generated inverted clock signal S2 to the latch signal generating circuit 180, the latch signal generating circuit 180 synchronizes the output signal from the timer circuit 179 with the inverted clock signal S2 and outputs it as the latch signal SL. It is configured. On the other hand, a delayed clock signal generated by delaying the clock signal S1 output from the clock signal output circuit 171 by a period different from an integer multiple of the period of the clock signal S1 is generated as a latch signal generation circuit 180. You may make it input into. FIG. 78 is a block diagram illustrating an example of a configuration in which the delayed clock signal is input to the latch signal generation circuit 180.

  In the configuration shown in FIG. 78, the delay circuit 182 delays the clock signal S1 output from the clock signal output circuit 171 by a period that is different from a period that is an integral multiple of the period of the clock signal S1, thereby delaying the delayed clock signal S3. Is generated. The delay circuit 182 outputs the generated delayed clock signal S3 to the latch signal generation circuit 180. The latch signal generation circuit 180 generates the latch signal SL by outputting the output signal from the timer circuit 179 in synchronization with the rising edge of the delayed clock signal S3 output from the delay circuit 182.

  FIG. 79 is a timing chart for explaining the operation of random number circuit 103 having the configuration shown in FIG. An internal system clock CLK as shown in FIG. 79A is input to the clock input terminal of the clock signal output circuit 171 and the clock input terminal of the timer circuit 179 provided in the random number circuit 103. The internal system clock CLK may be generated by the clock circuit 101 provided in the game control microcomputer 100.

  The clock signal output circuit 171 divides the internal system clock CLK and generates a clock signal S1 shown in FIG. 79B that rises from a low level to a high level at timings T31, T32,. Here, the period of the clock signal S1 output from the clock signal output circuit 171 is T. 79 shows a case where the clock signal output circuit 171 generates the clock signal S1 by dividing the internal system clock CLK by two for the sake of explanation. However, in practice, as a cycle for updating the 16-bit random number, either the cycle of the internal system clock CLK or a cycle 16 times the internal system clock CLK is set. Therefore, the clock signal output circuit 171 only needs to be able to switch between outputting the internal system clock CLK as it is as the clock signal S1 and outputting the signal obtained by dividing the internal system clock CLK by 16 as the clock signal S1. . The clock signal S1 output from the clock signal output circuit 171 is input to a random number generation circuit 173B and a delay circuit 182 provided for generating a 16-bit random number.

  The random number generation circuit 173B updates the numerical data C2 in response to the rising edge of the clock signal S1 input to the clock input terminal, and outputs the numerical data C2 to the random number sequence change circuit 176B. The delay circuit 182 delays the clock signal S1 output from the clock signal output circuit 171 by ΔT (≠ nT: n is an integer) and, for example, a period T rising from a low level to a high level at timings T41, T42,. The delayed clock signal S3 shown in FIG. 79C is generated. The delayed clock signal S3 generated by the delay circuit 182 is output to the latch signal generation circuit 180.

  When the start winning signal SS shown in FIG. 79D is input to the timer circuit 179, when the elapsed time from the rising edge reaches a predetermined time (for example, 3 milliseconds), the output signal from the timer circuit 179 is low. Rise from level to high level. The output signal from the timer circuit 179 is input to the latch signal generation circuit 180, and is output as a latch signal SL as shown in FIG. 79 (E) in synchronization with the rising edge of the delayed clock signal S3. As a result, the random number generation circuit 173B updates the numerical data C1 at timings T31, T32,..., While the latch signal generation circuit 180 outputs a latch signal SL that rises at a timing T43 different from the timings T31, T32,. Can do.

  According to the above configuration, in the random number circuit 103, for example, the random number generation circuit 173B is predetermined within a predetermined range in which the numerical data C2 can be updated based on the input of the clock signal S1 input from the clock signal output circuit 171. Are updated cyclically according to a predetermined order (for example, an order of “1 → 2 →... → 65535”) from the initial value to a predetermined final value. On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 according to the input of the start winning signal SS with the delay clock signal S3 output by the delay circuit 182 as the latch signal SL. Output. Thereby, acquisition of a random number value can be performed reliably and stably.

  The present invention is not limited to the above embodiment, and various modifications and applications are possible. For example, in the random number circuit 103 configured as shown in FIG. 11, the clock signal S1 output from the clock signal output circuit 171 is input to the random number generation circuit 173B and the inversion circuit 178, and the inversion circuit 178 has the signal level of the clock signal S1. Inverted clock signal S2 generated by inverting is input to latch signal generation circuit 180. In contrast, the clock signal S1 output from the clock signal output circuit 171 is input to the latch signal generation circuit 180 and a predetermined inversion circuit, and the inversion clock generated by the inversion circuit inverting the signal level of the clock signal S1. The signal may be input to the random number generation circuit 173B. In this case, the random number generation circuit 173B is predetermined from a predetermined initial value to a predetermined final value within a predetermined range in which the numerical data C2 can be updated based on the input of the inverted clock signal output from the inverting circuit. Update cyclically according to order. On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 in response to the input of the start winning signal SS in synchronization with the clock signal S1 output from the clock signal output circuit 171. Output as. Such a configuration also makes it possible to reliably and stably acquire a random value.

  For example, in the random number circuit 103 configured as shown in FIG. 78, the clock signal S1 output from the clock signal output circuit 171 is input to the random number generation circuit 173B and the delay circuit 182, and the delay circuit 182 receives the clock signal S1. The delayed clock signal S3 generated by the delay is input to the latch signal generation circuit 180. In contrast, the clock signal S1 output from the clock signal output circuit 171 is input to the latch signal generation circuit 180 and a predetermined delay circuit, and the delay clock signal generated by the delay circuit delaying the clock signal S1 is a random number. You may comprise so that it may input into the production | generation circuit 173B. In this case, the random number generation circuit 173B is predetermined from a predetermined initial value to a predetermined final value within a predetermined range in which the numerical data C2 can be updated based on the input of the delayed clock signal output from the delay circuit. Update cyclically according to order. On the other hand, the latch signal generation circuit 180 synchronizes the output signal from the timer circuit 179 in response to the input of the start winning signal SS in synchronization with the clock signal S1 output from the clock signal output circuit 171. Output as. Such a configuration also makes it possible to reliably and stably acquire a random value.

  In the above embodiment, the stored value update signal KT from the random value register 181A is input to the clock input terminal of the random number generation circuit 173A provided for the 12-bit random number, and the stored value update signal KT is changed from the low level to the high level. In the description, the numerical data C1 is updated in response to the rise. However, the present invention is not limited to this. For example, the numerical data C1 may be updated at a constant period by inputting a clock signal having a predetermined period to the clock input terminal of the random number generation circuit 173A. As an example, the clock signal S1 output from the clock signal output circuit 171 is also input to the random number generation circuit 173A, and has the same configuration as the inverting circuit 178, timer circuit 179, and latch signal generation circuit 180 provided for 16-bit random numbers. May be provided for a 12-bit random number. Further, a clock signal output from a clock signal output circuit provided separately from the clock signal output circuit 171 may be input to the random number generation circuit 173A. In this case, the clock signal output circuit that generates the clock signal input to the random number generation circuit 173A inputs the internal system clock CLK supplied from the clock circuit 101, similarly to the clock signal output circuit 171 in the above embodiment. Thus, a clock signal having the same cycle as the internal system clock CLK or a clock signal obtained by dividing the internal system clock CLK by 16 may be output. As a result, for the 12-bit random number, for example, the random number generation circuit 173A is predetermined from a predetermined initial value to a predetermined final value within a predetermined range in which the numerical data C1 can be updated based on the input of a predetermined clock signal. The latch signal generation circuit provided for the 12-bit random number is updated in accordance with the order of the external signals such as the start winning signal SS. The output signal from the timer circuit according to the input can be output as a latch signal in synchronization with the inverted clock signal output from the inverting circuit, and the 12-bit random number can be acquired reliably and stably. . In this case, similarly to the configuration for 16-bit random numbers, the inversion circuit for 12-bit random numbers may be replaced with a delay circuit, or an inversion circuit or the like between the clock signal output circuit and the random number generation circuit 173A may be used. A delay circuit may be provided. In addition, the configuration for generating the 12-bit random number in the above embodiment may have the same function as the configuration for generating the 16-bit random number, or the configuration for generating the 16-bit random number. May have the same function as the configuration for generating a 12-bit random number.

  In the above-described embodiment, the game control microcomputer 100 includes the serial communication circuit 108 and the payout control microcomputer 150 includes the serial communication circuit 218. The game control microcomputer 100 and the payout control microcomputer It has been described that both computers 150 perform serial communication. However, the present invention is not limited to this, and it is sufficient that at least one of the game control microcomputer 100 and the payout control microcomputer 150 has a configuration for performing serial communication. In the following, one of the game control microcomputer 100 and the payout control microcomputer 150 having a serial communication circuit is referred to as a first microcomputer, and the other microcomputer having no serial communication circuit is referred to as a second microcomputer. A microcomputer. In this case, the second microcomputer may include, for example, a serial-parallel conversion circuit (for example, a shift register) that converts data transmitted from the first microcomputer via a serial communication line into parallel data. Alternatively, the second microcomputer may sample the data transmitted from the first microcomputer at a predetermined period to obtain the data transmitted via the serial communication line.

  Communication data may be transmitted from the second microcomputer to the first microcomputer by parallel communication using a plurality of data communication lines. The first microcomputer may be provided with input ports corresponding to a plurality of data communication lines so as to acquire communication data transmitted by parallel communication. In this case, in the serial communication circuit included in the first microcomputer, only the transmission operation unit may be used, and the reception operation unit may be set to an unused state.

  In the above embodiment, the maximum value comparison circuits 177A and 177B compare the numerical data sequences R1 and R2 output from the random number sequence change circuits 176A and 176B with the predetermined maximum value, respectively, and the numerical data is less than the maximum value. By performing the operation of repeating the output of the reset signals MS1 and MS2 until a short time, a numerical value that becomes the updated random value within a sufficiently short elapsed time from the rising edge of the stored value update signal KT or the clock signal S1 In the above description, the data R1 and R2 are output. However, the present invention is not limited to this, and random number generation circuits 173A and 173B may be cleared (initialized) by output signals from maximum value comparison circuits 177A and 177B.

  For example, the maximum value comparison circuit 177A can refer to the maximum value and start value set for the 12-bit random number, and the random number sequence change circuit 176A uses the numerical data C1 output from the random number generation circuit 173A as the 12-bit random number. Are rearranged so as to be in a predetermined permutation within a range equal to or less than the maximum value set for use. Then, the maximum value comparison circuit 177A specifies the difference between the maximum value and the start value, and determines whether or not the number of updates of the numerical data sequence R1 output from the random number sequence change circuit 176A matches the difference. . At this time, when the number of updates of the numerical data string R1 reaches the difference between the maximum value and the start value, the value of the numerical data C1 output from the random number generation circuit 173A reaches the maximum value set for the 12-bit random number. Therefore, the maximum value comparison circuit 177A inputs a predetermined count clear signal to the random number generation circuit 173A, and clears (initializes) the numerical data C1 generated by the random number generation circuit 173A. Thereafter, the random number generation circuit 173A sequentially counts up from the minimum value of the numerical data C1 output after clearing, for example, when the final value 1 smaller than the start value is reached, for example, the random number round trip signal RIJ1. Output.

  Further, the maximum value comparison circuit 177B can refer to the maximum value and start value set for 16-bit random numbers, and the random number sequence change circuit 176B uses the 16-bit random number data C2 output from the random number generation circuit 173B. Are rearranged so as to be in a predetermined permutation within a range equal to or less than the maximum value set for use. Then, the maximum value comparison circuit 177B specifies the difference between the maximum value and the start value, and determines whether or not the number of updates of the numerical data sequence R2 output from the random number sequence change circuit 176B matches the difference. . At this time, when the number of updates of the numerical data string R1 reaches the difference between the maximum value and the start value, the value of the numerical data C2 output from the random number generation circuit 173B reaches the maximum value set for 16-bit random numbers. Therefore, the maximum value comparison circuit 177B inputs a predetermined count clear signal to the random number generation circuit 173B, and clears (initializes) the numerical data C2 generated by the random number generation circuit 173B. Thereafter, the random number generation circuit 173B sequentially counts up from the minimum value of the numerical data C2 output after clearing, for example, when the final value that is 1 smaller than the start value is reached, for example, Output.

  In such a configuration, the start value is set so that the start value for the 12-bit random number is less than or equal to the maximum value for the 12-bit random number, and the start value for the 16-bit random number is less than or equal to the maximum value for the 16-bit random number. And set the maximum value. Further, when the permutation is changed by any one of the random number sequence changing circuits 176A and 176B, numerical data sequences R1 and R2 including a value larger than the maximum value for 12-bit random numbers and the maximum value for 16-bit random numbers are output. Set not to be done.

  In the above embodiment, the power supply monitoring circuit 303 is mounted on the power supply board 10. However, the present invention is not limited to this. For example, even if the power supply monitoring circuit is mounted on the dispensing control board 15. Good. In this case, the payout control board 15 inputs at least part of the power supply voltage (for example, VSL and VCC) supplied from the power supply board 10 to the power supply monitoring circuit, and when a drop in the power supply voltage is detected, a power-off signal is generated. Configure to be on. The power cut-off signal output from the power supply monitoring circuit is input to a predetermined input port provided in the payout control microcomputer 150 and can be transmitted to the main board 11 via, for example, a predetermined output circuit. do it. According to such a configuration, it is not necessary to provide a wiring for transmitting a power-off signal from the power supply board 10 to the payout control board 15, so that the wiring configuration can be further simplified. In addition, since the overall length of the wiring for transmitting the power-off signal is shortened, the possibility of noise on the power-off signal can be reduced.

  In the above-described embodiment, the clear switch 304 is mounted on the power supply board 10. However, the present invention is not limited to this, and for example, the clear switch may be mounted on the main board 11. In this case, the clear signal output from the clear switch is input to a predetermined input port provided in the game control microcomputer 100 and can be transmitted to the payout control board 15 via, for example, a predetermined output circuit. That's fine. According to such a configuration, it is not necessary to provide a wiring for transmitting a clear signal from the power supply substrate 10 to the main substrate 11, and therefore the wiring configuration can be further simplified. In addition, since the overall length of the wiring for transmitting the clear signal is shortened, the possibility of noise on the clear signal can be reduced.

  In the above embodiment, the power supply monitoring circuit 303 mounted on the power supply board 10 has been described as outputting a reset signal. However, the present invention is not limited to this. For example, the reset is performed on each control board including the main board 11. A reset circuit that outputs a signal may be mounted. Alternatively, a reset circuit is mounted on any one (one or a plurality of control boards) of a plurality of control boards, and a reset signal output from the reset circuit is sent to another control board that is not mounted with a reset circuit. You may make it supply. When the reset circuit is mounted on each control board, the voltage value when the reset signal becomes high level may be made different depending on each reset circuit. For example, when the reset signal output from the reset circuit mounted on the main board 11 is at a high level, the voltage value when the reset signal output from a reset circuit mounted on another control board is at a high level. It may be set so that the timing at which the reset signal input to the game control microcomputer 100 is turned on is the latest so as to be higher than the voltage value of.

  In the above embodiment, when the supply of power to the pachinko gaming machine 1 is started, the clear signal is turned on in response to an operation such as pressing on the clear switch 304 mounted on the power supply board 10. In the above description, the game control microcomputer 100 and the payout control microcomputer 150 are set at initialization. However, the present invention is not limited to this, and when power supply to the pachinko gaming machine 1 is started, for example, an initialization command signal input from the outside of the pachinko gaming machine 1 is turned on. When a predetermined condition such as being present is established, the game control microcomputer 100 and the payout control microcomputer 150 may be set at initialization. As a specific example, the initialization command signal may be output from the hall management computer and input to the pachinko gaming machine 1, or detects an intruder or contact with the pachinko gaming machine 1. It may be output from a sensor or the like and input to the pachinko gaming machine 1.

  In the above-described embodiment, the DC power supply (DC30V) obtained by rectifying and smoothing the AC power supply (AC24V) is monitored as the power supply monitoring means for detecting the power supply interruption, and the monitored DC power supply becomes a predetermined voltage or less. However, the present invention is not limited to this, and the presence or absence of a full-wave rectified waveform during the conversion of the AC power supply (AC24V) to DC can be monitored to detect the waveform for a predetermined period. A power-off signal may be output when there is not. Further, the AC power supply may be directly monitored, and a power-off signal may be output when the AC waveform cannot be detected for a predetermined period. In other words, the target to be monitored is not limited to the voltage, but may be a full-wave rectified waveform or a half-wave rectified waveform, as long as it can detect that the power supplied to the gaming machine is decreasing.

  The power-off signal may be input to an input port of the game control microcomputer and the payout control microcomputer, and the power-off process may be executed when it is determined that the power-off signal is on. Alternatively, a power-off signal may be input to the NMI terminal and the power-off process may be executed by a non-maskable interrupt process. Also, a power-off signal is input to the NMI terminal, a power-off flag is set according to the input of the power-off signal, and the state of the power-off flag is monitored by timer interrupt processing or main processing. A power-off process may be executed.

  In the above embodiment, the checksum data is created and the backup flag is set in the power-off process, and those are checked when the power is turned on. A process for clearing the port and a process for monitoring whether the power state has been restored (a process for restoring at the momentary power failure) may be executed. Further, the order of these processes is not limited to the present embodiment.

  In the above embodiment, the game control counter setting unit 135 is provided with a total prize ball number counter and first to third payout number instruction counters. In the process of step S252 shown in FIG. A predetermined value is added to the value of the counter and any one of the first to third payout number instruction counters to be updated. Also, in step S324 shown in FIG. 46, one of the values of the first to third payout number instruction counters corresponding to the value of variable N is decremented by 1 and updated, while any of steps S327, S329, and S330 is updated. By executing such processing, a predetermined value corresponding to the value of the variable N is subtracted from the value of the total prize ball counter and updated. Thus, in the above embodiment, when the game control microcomputer 100 determines that the prize ball ACK command from the payout control board 15 has been received, the first to third payout number instruction counters. Update and update of the total prize ball counter. However, the present invention is not limited to this. For example, when a payout number designation command is transmitted, the first to third payout number instruction counters and the total prize ball number counter are updated. Good. In this case, the first to third payout number instruction counters are updated and the total prize is set before the setting for transmitting the payout number designation command is performed by any of the processes of steps S308, S310, and S311 shown in FIG. The ball number counter may be updated, or after performing the setting of transmitting a payout number designation command by executing any of the processes of steps S308, S310, and S311 shown in FIG. 45, the payout control is performed. Prior to determining whether or not the prize ball ACK command from the board 15 has been received, the first to third payout number instruction counters or the total prize ball number counter may be updated.

  Further, the game control counter setting unit 135 is not limited to the one having the total prize ball number counter and the first to third payout number instruction counters, and the number of game balls that the game control microcomputer 100 should pay out as a prize ball. Any data can be used as long as it can store data that can be specified. For example, the game control counter setting unit 135 is provided with the total prize ball number counter, but the first to third payout number instruction counters may not be provided. In this case, the number of game balls to be paid out is “1” based on the bit values of the third to 0th bits [bits 3-0] in the first and second bytes of the payout number designation command shown in FIG. ”To“ 16 ”can be specified. Then, the number of prize balls to be paid out is specified from the value of the total prize ball number counter, and a payout number designation command for instructing the specified number of prize balls as the number of payouts is sent from the main board 11 to the payout control board 15. What is necessary is just to make it transmit. At this time, when the value of the total prize ball number counter is larger than the maximum number of payouts (for example, “16”) that can be instructed by the payout number designation command, the maximum payout number is indicated. The payout number designation command may be transmitted, the value of the total prize ball number counter may be updated, and the payout number designation command may be further transmitted based on the updated total prize ball number counter value.

  Alternatively, the game control counter setting unit 135 is provided with the first to third payout number instruction counters, but the total prize ball number counter may not be provided. In this case, any value of the first to third payout number instruction counters may be updated corresponding to the switch in the on state in step S252 shown in FIG. 44A, and step S325 shown in FIG. After executing the process of step S331, the process may proceed to step S331.

  In the above embodiment, when it is determined in step S321 shown in FIG. 46 that the prize ball ACK command is received from the payout control board 15 because the prize ball ACK reception flag is ON, the process of step S325 is performed. The process is executed and the value of the command transmission counter is incremented by one. However, the present invention is not limited to this. For example, when a payout number designation command is transmitted, the value of the command transmission number counter may be incremented by one. In this case, the value of the command transmission number counter is incremented by 1 before setting for transmitting the payout number designation command by any of the processes of steps S308, S310, and S311 shown in FIG. In addition, after performing any of the processing of steps S308, S310, and S311 shown in FIG. 45 and performing setting for transmitting the payout number designation command, the prize ball ACK command from the payout control board 15 is received. Before the determination of whether or not, the value of the command transmission counter may be incremented by one. Thus, even when the value of the command transmission counter is incremented by 1 when the payout number designation command is transmitted, the number of game balls to be paid out as prize balls is not counted directly, and the game balls to be paid out as prize balls are counted directly. It is possible to detect that an abnormality has occurred in the number. In addition, since the number of game balls won in the winning opening is smaller than the number of game balls paid out as prize balls, the amount of data stored can be reduced. Further, it is possible to specify the difference between the number of payout number designation command transmissions and the number of game balls detected by the all winning ball detection switch 29 as a winning number difference by simply updating the count value in one command transmission number counter. Therefore, it is possible to determine whether an abnormality has occurred in the number of game balls to be paid out as prize balls while suppressing an increase in control burden. In addition, since it is only necessary to store the count value in one command transmission number counter, the data storage amount can be reduced as compared with the case where the count values in a plurality of counters are used. A counter for counting the number of transmissions of the first to third payout number designation commands and a counter for counting the number of game balls detected by the all winning ball detection switch 29 are provided separately. The difference between the values of the counters may be specified as a winning number difference.

  In the above embodiment, the switch process of step S72 and the special symbol process process of step S78 are executed in the game control timer interrupt process as shown in FIG. Here, for example, when the detection signal from the start port switch 22 is in the ON state in the switch process of step S72, the timer value in the start port switch timer is incremented by one. In the special symbol process in step S78, for example, in step S421 shown in FIG. 51, it is determined that the timer value in the start-up switch timer is a predetermined switch-on determination value (for example, “2”). Sometimes, the random number value is read from the random value register 181B included in the random number circuit 103 in the winning process of step S422. On the other hand, in the timer interrupt processing for game control, the start port switch timer is updated according to whether or not the detection signal from the start port switch 22 is on, and the timer value is set to a predetermined switch. When a predetermined start winning flag is set to the on state when the on determination value is reached, the random number value is read from the random number circuit 103 when the power-off signal is in the off state in step S29 shown in FIG. It may be performed in a loop process executed in step (b).

  In this case, in the game control timer interruption process, for example, only the processes of steps S71, S72, and S84 among the processes shown in FIG. 40 are executed. In the switch process of step S72, when the detection signal from the start port switch 22 is in the ON state, the timer value in the start port switch timer is updated to be incremented by one, while the detection from the start port switch 22 is performed. When the signal is off, the start port timer is cleared. When the timer value in the start port switch timer reaches the switch-on determination value, the start winning flag provided in the game control flag setting unit 133 is set to the on state. On the other hand, when the power-off signal is OFF in step S29 shown in FIG. 30, each process of steps S73 to S83 shown in FIG. 40 is executed, and then the process returns to the process of step S29. Here, in the special symbol process in step S78, the process for determining whether or not the start winning flag is on is executed as the process in step S421 shown in FIG. Then, when the start winning flag is on, the winning process in step S422 may be executed to read the random number value from the random number circuit 103 and store it in the special figure holding storage unit 131. Thereby, it is possible to prevent an increase in the processing amount of the CPU 104 included in the game control microcomputer 100 when a timer interrupt occurs, and to reduce the control burden when the timer interrupt occurs.

  In the above embodiment, when it is determined that the production control microcomputer 120 has received the serial communication abnormality notification start command in step S948 shown in FIG. 74, the serial communication abnormality notification as illustrated in FIG. After displaying the image to be the screen on the image display device 5, the display of the serial communication abnormality notification screen continues until it is determined in step S946 shown in FIG. 74 that the serial communication abnormality notification end command has been received. Done. Also, when it is determined in step S953 shown in FIG. 74 that the main-side payout abnormality notification start command has been received, an image that becomes a main-side payout abnormality notification screen as illustrated in FIG. After the display, the main side payout abnormality notification screen is continuously displayed until it is determined in step S951 shown in FIG. 74 that the main side payout abnormal end command has been received. When it is determined in step S958 shown in FIG. 75 that a payout-side abnormality notification start command has been received, an image that becomes a payout-side abnormality notification screen as illustrated in FIG. 76E is displayed on the image display device 5. Thereafter, the payout side abnormality notification screen is continuously displayed until it is determined in step S956 shown in FIG. 75 that the payout side abnormal end command has been received. However, the present invention is not limited to this. For example, as in the case of displaying the excessive number of winning ball notification screen illustrated in FIG. 76 (F) and the shortage of winning ball notification screen illustrated in FIG. 76 (G), When the timing for ending the notification is reached, the display of the serial communication abnormality notification screen, the main-side payout abnormality notification screen, the payout-side abnormality notification screen, or the like may be ended. In this case, since it is not necessary to transmit a command for instructing the end of abnormality notification from the main board 11 to the effect control board 12, the control burden on the game control microcomputer 100 can be reduced.

  In the above embodiment, it is determined whether or not the main board communication error flag is turned on in step S801 in the prize ball payout number calculation process shown in FIG. 64. finish. Also, in step S821 in the prize ball payout driving process shown in FIG. 65, it is determined whether or not the main board communication error flag is turned on. When it is turned on, the process proceeds to step S827 to play the game by the payout motor 51. The ball dispensing operation is stopped. On the other hand, in the ball lending / dispensing number calculation process shown in FIG. 67 and the ball lending / dispensing drive process shown in FIG. 68, it is not determined whether or not the main board communication error flag is on. However, the present invention is not limited to this. For example, when the ball lending / dispensing number calculation process shown in FIG. 67 is started, it is first determined whether or not the main board communication error flag is turned on. In some cases, the ball lending / dispensing number calculation processing may be terminated as it is. Further, when the ball lending / dispensing driving process shown in FIG. 68 is started, it is first determined whether or not the main board communication error flag is turned on. If it is turned on, the process proceeds to step S866 and the game by the dispensing motor 51 is performed. The ball payout operation may be stopped. Thus, when it is determined that the ACK feedback command from the main board 11 has not been received, the value of the ball lending unpaid counter becomes a value other than “0” and becomes a non-paid lending ball. Even if it indicates that there is, there is a control to stop the payout control. Thereby, reliable payout control is executed, and it is possible to prevent excessively paying out the game balls to be rented when, for example, an abnormality due to a communication error or an illegal act on the communication line occurs.

  In the above embodiment, the detection signal output from the start port switch 22 is input to the timer circuit 179 provided in the random number circuit 103 as the start winning signal SS. The timer circuit 179 measures the time during which the start winning signal SS is input. When the measured time reaches a predetermined time (for example, 3 milliseconds), the start winning signal SS is latched. Was output. However, the present invention is not limited to this. The detection signal from the start port switch 22 is input to the CPU 104, and the CPU 104 executes a game control timer interrupt process a predetermined number of times (for example, twice) (for example, The latch start winning signal SN may be sent to the latch signal generation circuit 180 when the detection signal from the start port switch 22 is continuously on for 4 milliseconds). In this case, the timer circuit 179 included in the random number circuit 103 as shown in FIG. 11 is not necessary. For example, the latch start winning signal SN output from the CPU 104 is input to the D input terminal included in the latch signal generation circuit 180. Then, the inverted clock signal S2 output from the inverter circuit 178 and the delayed clock signal S3 output from the delay circuit 182 may be input to the clock input terminal included in the latch signal generation circuit 180. The latch signal generation circuit 180 outputs the latch start winning signal SN input to the D input terminal in synchronization with the rising edge of the inverted clock signal S2 or the delayed clock signal S3 input to the clock input terminal. A latch signal SL is generated and output.

  In the above embodiment, the timer circuit 179 measures the input time of the start winning signal SS using the internal system clock CLK. However, the present invention is not limited to this, and the clock obtained by dividing the internal system clock CLK. A clock signal different from the signal or the internal system clock CLK generated by the clock circuit 101 may be used. For example, the timer circuit 179 may measure the input time of the start winning signal SS using the clock signal S1 output from the clock signal output circuit 171. Further, in the above embodiment, the timer circuit 179 is set to 3 milliseconds as the predetermined time, but is not limited to this, and is 4 milliseconds which is the execution time of two game control timer interrupt processes. Any time shorter than a second can be set.

  Furthermore, in the above embodiment, the CPU 104 determines that the start winning signal is continuously input over the period (4 milliseconds) in which the two game control timer interruption processes are executed, as shown in FIG. The winning process of step S422 shown is being executed. However, the present invention is not limited to this, and the number of executions of the above-described game control timer interrupt process is arbitrary. For example, the CPU 104 has a period during which three game control timer interrupt processes are executed ( The winning process may be executed on the basis that the start winning signal is continuously input for 6 milliseconds). In this case, the timer circuit 179 may be set to a time shorter than 6 milliseconds, which is the execution time of three game control timer interruption processes.

  In the above embodiment, among the special symbols composed of numbers such as “0” to “9”, the special symbol indicating “7” is the jackpot symbol, and the special symbol indicating other numerical values is the lost symbol. In the above description, it is assumed that whether or not the game state becomes a probable big hit that becomes a high probability state is determined separately from the special symbol. However, the present invention is not limited to this, and the probability variation big hit symbol that is a big hit symbol when the gaming state is a high probability state and the normal big hit when the gaming state does not become a high probability state. The normal big hit symbol which is a big hit symbol may be a different special symbol. For example, a special symbol indicating “3” may be a normal jackpot symbol, and a special symbol indicating “7” may be a probability variation jackpot symbol. In this case, among the commands 90XXh serving as the display result notification command, the command 9001h is a command for notifying that the confirmed special symbol in the special game is a special symbol indicating “3” as a normal jackpot symbol, 9002h may be a command for notifying that the confirmed special symbol in the special symbol game is a special symbol indicating “7” as the probability variation big hit symbol.

  In the above-described embodiment, the gaming machine can execute a variable display start condition (for example, a game ball wins a start winning opening provided in the normal variable winning ball apparatus 6) after a variable display execution condition is satisfied (for example, For example, a variable display device that variably displays a plurality of types of identification information (for example, special symbols) that can each be identified based on the establishment of the previous special symbol game and the end of jackpot gaming state by the special symbol display device 4 For example, a pachinko gaming machine equipped with a special symbol display device 4) that controls to a specific gaming state (for example, a big hit gaming state) advantageous to the player when the display result of variable display becomes a predetermined specific display result. there were.

  However, the present invention is not limited to this, and the gaming machine is disadvantageous for the player due to the detection of the start detection means (for example, the start ball detector) that detects the game medium in the start area provided in the game area. It has a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, an opening operation) that becomes a first state advantageous to the player from the second state, in a specific area provided in the variable winning device. A specific gaming state (for example, jackpot) that controls the variable winning device to the first state in a specific manner that is more advantageous for the player than the starting operation by detection of a specific detection means (for example, a specific ball detector) that detects the gaming medium It may be a pachinko gaming machine that generates a gaming state.

  In addition, the gaming machine of the present invention is in a state where a right is generated on condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special region (for example, a special device operation region). During the period in which the right is generated, the game ball is moved by the start detection means (for example, the operation ball detection switch or the start port switch) provided in the start area (for example, the start port in the start winning device or the start winning device). Based on the detection, it is possible to perform control to change the special variable winning device (for example, the big prize opening) from a disadvantageous state (for example, a closed state) to the player (for example, a closed state) for the player (for example, an open state). Possible pachinko machines may be used.

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4 ... Special symbol display device 5 ... Image display device 6 ... Normal variable winning ball device 7 ... Special variable winning ball device 8L, 8R ... Speaker 9 ... Game effect lamp DESCRIPTION OF SYMBOLS 10 ... Power supply board 11 ... Main board 12 ... Production control board 13 ... Sound control board 14 ... Lamp control board 15 ... Discharge control board 17 ... Launch control board 18 ... Relay board 21 ... Gate switch 22 ... Start-up switch 23 ... V prize Switch 24 ... Count switch 25A to 25D ... Winner opening switch 26 ... Full switch 27 ... Out of ball switch 29 ... All winning ball detection switch 30 ... Operation knob 31 ... Error release switch 40 ... Normal symbol display 41 ... Passing gate 42A ~ 42D ... winning opening 51 ... payout motor 61 ... firing motor 70 ... Card unit 71 ... Dispensing motor position sensor 72 ... Dispensing count switch 73 ... Error release switch 74 ... Error display LED
81 ... Solenoid 82 ... Solenoid 85, 86 ... Hole 87, 88 ... Gear 89 ... Cam 90 ... Ball passage 91-93 ... Case 100 ... Game control microcomputer 101, 211 ... Clock circuit 102, 212 ... Reset / interrupt controller 103 213 ... Random number circuits 104, 123, 214 ... CPU
105, 121, 215 ... ROM
106, 122, 216 ... RAM
107, 217 ... timer circuit 108, 218 ... serial communication circuit 109, 219 ... external bus interface 111, 161 ... switch circuit 112 ... solenoid circuit 120 ... production control microcomputer 124 ... I / O
DESCRIPTION OF SYMBOLS 130 ... Game control data holding area 131 ... Special figure holding | maintenance memory | storage part 132 ... Fixed special symbol memory | storage part 133 ... Game control flag setting part 134 ... Game control timer setting part 135 ... Game control counter setting part 136 ... Game control buffer setting part 140 ... Dispensing control data holding area 141 ... Dispensing control flag setting section 142 ... Dispensing control timer setting section 143 ... Dispensing control counter setting section 144 ... Dispensing control buffer setting section 150 ... Dispensing control microcomputer 171 ... Clock signal output circuit 172A 172B ... Initial value setting circuits 173A and 173B ... Random number generation circuits 174A and 174B ... Selectors 175A and 175B ... ARSC and BRSC
176A, 176B ... random number sequence change circuit 177A, 177B ... maximum value comparison circuit 178 ... inversion circuit 179 ... timer circuit 180 ... latch signal generation circuit 181A, 181B ... random number value register 182 ... delay circuit 191 ... payout reception command buffer 192 ... Sending command buffer 201 for payout ... Reception operation unit 202 ... Transmission operation unit 203 ... Serial communication data register 204 ... Serial status register 205 ... Serial control register 301 ... Transformer circuit 302 ... DC voltage generation circuit 303 ... Power supply monitoring circuit 304 ... Clear switch

Claims (1)

A variable display device that variably displays a plurality of types of identification information that can each be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and a game medium in the winning area in the game area This is a gaming machine that pays out a prize game medium as a prize based on the winning of a prize, and controls the game to a specific gaming state advantageous to the player when the display result of the variable display becomes a predetermined specific display result. And
Winning detection means for detecting that a game ball has won in the winning area and outputting a winning detection signal;
An initialization operation means for outputting an initialization request signal according to the operation;
A payout means for paying out the prize game medium;
A random number circuit for generating a random number, a winning detection signal from the winning detection means is input, a game control process for controlling the progress of the game is executed, and a payout control signal for controlling the payout means; A game control board equipped with a game control microcomputer for transmitting an effect control signal for controlling electric parts for effect provided in the machine;
A payout control board equipped with a payout control microcomputer for executing payout control processing for controlling the payout means in accordance with a payout control signal transmitted by the game control microcomputer;
An effect control board on which an effect control microcomputer for controlling the electric parts for effect according to the effect control signal transmitted by the game control microcomputer is mounted;
Power supply monitoring means for outputting a power failure signal when the state of power used in the gaming machine becomes a predetermined state;
The random number circuit includes:
Numerical value updating means for cyclically updating from a predetermined initial value to a predetermined final value in a predetermined range in which numerical data can be updated based on an input of a predetermined signal according to a predetermined order;
Random number storage means for storing numerical data updated by the numerical value update means as a random value,
The game control microcomputer is:
Game control storage means for storing data indicating the progress of the game and retaining the stored content for at least a predetermined period even when the power supply to the gaming machine is stopped;
A payout number signal transmitting means for sending a payout number signal indicating the number of prize game media to be paid out to the payout control microcomputer as the payout control signal in response to the input of the winning detection signal;
Game control side power supply stop time processing means for executing game control side power supply stop time processing for storing data indicating a game progress state in response to the power monitoring means outputting the power failure signal;
Initialization operation determination means for determining whether or not an initialization request signal is output from the initialization operation means when power supply to the gaming machine is started;
A delay processing means for executing a delay process for delaying the start of execution of the game control process until at least the execution of the payout control process is started after the determination by the initialization operation determination means;
The game stored in the game control storage means on condition that the initialization operation determination means determines that the initialization request signal has not been output after the delay processing by the delay processing means is executed. Game control side recovery processing means for executing a game control side recovery process for recovering the game progress state based on the data indicating the progress state of the game,
When the game control side recovery process is executed by the game control side recovery processing means, a recovery notification signal for notifying that the game control side recovery process has been executed is used as the effect control signal for the effect control. A recovery notification signal transmitting means for transmitting to the microcomputer;
Random number circuit setting means for setting the random number circuit to generate the random number after power supply to the gaming machine is started;
After the setting by the random number circuit setting means, a timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically,
Execution condition determination means for determining whether or not the variable display execution condition is satisfied during execution of the timer interrupt process;
Random value reading means for reading the random value stored by the random value storage means based on the execution condition determining means determining that the execution condition of the variable display is satisfied;
Display result for determining whether or not the display result in the variable display is the specific display result by determining whether or not the random value read by the random value reading means matches a predetermined determination value data Determining means,
The dispensing control microcomputer is:
A payout number signal receiving means for receiving a payout number signal transmitted by the payout number signal transmitting means;
Stores unpaid-out data indicating the number of unpaid premium game media that have not been paid out among the paid-out number of premium game media indicated by the payout-number signal received by the payout-number signal receiving means. A storage unit for payout control that retains the stored contents for at least a predetermined period even when power supply to the machine is stopped;
A prize game medium payout control means for driving the payout means to execute payout control for paying out the number of unpaid premium game media indicated by the unpaid-out number data;
A payout control side power supply stop time processing means for executing a payout control side power supply stop time process for storing the unpaid number data in response to the power supply monitoring means outputting the power failure signal,
When the power supply to the gaming machine is started, on the condition that the initialization request signal is not output from the initialization operation means, the unpaid number data stored in the payout control storage means A payout control side recovery processing means for executing payout control side recovery processing to restore the payout to a possible state based on
The effect control microcomputer, when receiving the recovery notification signal transmitted by the recovery notification signal transmission means, controls the effect electrical parts to notify that the game control side recovery process has been executed. Including a recovery notification means,
At least one of the game control microcomputer and the payout control microcomputer has a built-in serial communication circuit for performing serial communication with the other, and communication for controlling serial communication operation by the serial communication circuit A specific microcomputer including a control means;
The serial communication circuit includes interrupt request notification means for notifying an interrupt request according to an interrupt request condition established for the communication control means when any of a plurality of interrupt request conditions is established,
The interrupt request notified by the interrupt request notification means includes an error interrupt request for causing the communication control means to execute processing corresponding to the occurrence of an error when an error occurs in serial communication. ,
A gaming machine characterized by that.

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