JP2011058847A5 - - Google Patents

Download PDF

Info

Publication number
JP2011058847A5
JP2011058847A5 JP2009206124A JP2009206124A JP2011058847A5 JP 2011058847 A5 JP2011058847 A5 JP 2011058847A5 JP 2009206124 A JP2009206124 A JP 2009206124A JP 2009206124 A JP2009206124 A JP 2009206124A JP 2011058847 A5 JP2011058847 A5 JP 2011058847A5
Authority
JP
Japan
Prior art keywords
data holding
holding units
input data
value
output data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009206124A
Other languages
English (en)
Japanese (ja)
Other versions
JP2011058847A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2009206124A priority Critical patent/JP2011058847A/ja
Priority claimed from JP2009206124A external-priority patent/JP2011058847A/ja
Priority to US12/805,754 priority patent/US20110060952A1/en
Priority to CN2010102758896A priority patent/CN102013270A/zh
Publication of JP2011058847A publication Critical patent/JP2011058847A/ja
Publication of JP2011058847A5 publication Critical patent/JP2011058847A5/ja
Pending legal-status Critical Current

Links

JP2009206124A 2009-09-07 2009-09-07 半導体集積回路装置 Pending JP2011058847A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009206124A JP2011058847A (ja) 2009-09-07 2009-09-07 半導体集積回路装置
US12/805,754 US20110060952A1 (en) 2009-09-07 2010-08-18 Semiconductor integrated circuit
CN2010102758896A CN102013270A (zh) 2009-09-07 2010-09-07 半导体集成电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009206124A JP2011058847A (ja) 2009-09-07 2009-09-07 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JP2011058847A JP2011058847A (ja) 2011-03-24
JP2011058847A5 true JP2011058847A5 (cg-RX-API-DMAC7.html) 2012-04-05

Family

ID=43648587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009206124A Pending JP2011058847A (ja) 2009-09-07 2009-09-07 半導体集積回路装置

Country Status (3)

Country Link
US (1) US20110060952A1 (cg-RX-API-DMAC7.html)
JP (1) JP2011058847A (cg-RX-API-DMAC7.html)
CN (1) CN102013270A (cg-RX-API-DMAC7.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8045401B2 (en) * 2009-09-18 2011-10-25 Arm Limited Supporting scan functions within memories
US8972807B2 (en) * 2012-05-14 2015-03-03 Texas Instruments Incorporated Integrated circuits capable of generating test mode control signals for scan tests
CN105575438B (zh) * 2014-10-16 2020-11-06 恩智浦美国有限公司 用于测试存储器的方法及装置
JP6544958B2 (ja) * 2015-03-18 2019-07-17 ルネサスエレクトロニクス株式会社 半導体装置及び設計装置、スキャンフリップフロップ
JP6901682B2 (ja) * 2017-09-12 2021-07-14 富士通株式会社 記憶装置、演算処理装置及び記憶装置の制御方法
JP2019168316A (ja) * 2018-03-23 2019-10-03 株式会社東芝 半導体集積回路
US10847211B2 (en) * 2018-04-18 2020-11-24 Arm Limited Latch circuitry for memory applications
US12300338B2 (en) 2022-06-14 2025-05-13 Arm Limited Configurable scan chain architecture for multi-port memory
US11894845B1 (en) * 2022-08-30 2024-02-06 Globalfoundries U.S. Inc. Structure and method for delaying of data signal from pulse latch with lockup latch

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2865498B2 (ja) * 1992-08-31 1999-03-08 三菱電機株式会社 半導体集積回路装置
US6694465B1 (en) * 1994-12-16 2004-02-17 Texas Instruments Incorporated Low overhead input and output boundary scan cells
US6556494B2 (en) * 2001-03-14 2003-04-29 Micron Technology, Inc. High frequency range four bit prefetch output data path
US7155651B2 (en) * 2004-04-22 2006-12-26 Logicvision, Inc. Clock controller for at-speed testing of scan circuits
US7596732B2 (en) * 2005-06-30 2009-09-29 Texas Instruments Incorporated Digital storage element architecture comprising dual scan clocks and gated scan output
JP2007187458A (ja) * 2006-01-11 2007-07-26 Nec Electronics Corp スキャンフリップフロップ回路、及び、半導体集積回路装置
WO2007115227A2 (en) * 2006-03-30 2007-10-11 Silicon Image, Inc. Multi-port memory device having variable port speeds
KR101458381B1 (ko) * 2006-04-24 2014-11-07 샌디스크 테크놀로지스, 인코포레이티드 고성능 플래시 메모리 데이터 전송
US7486587B2 (en) * 2006-07-31 2009-02-03 Sandisk 3D Llc Dual data-dependent busses for coupling read/write circuits to a memory array
US7793180B1 (en) * 2006-09-19 2010-09-07 Marvell International Ltd. Scan architecture for full custom blocks
US7783946B2 (en) * 2007-11-14 2010-08-24 Oracle America, Inc. Scan based computation of a signature concurrently with functional operation

Similar Documents

Publication Publication Date Title
JP2011058847A5 (cg-RX-API-DMAC7.html)
JP2010170538A5 (ja) 表示装置
JP2014074713A5 (cg-RX-API-DMAC7.html)
JP2012142562A5 (ja) 半導体装置
JP2012256858A5 (ja) 半導体装置
JP2012113809A5 (ja) フラッシュメモリ装置のメモリセルを読み出す方法
JP2015531934A5 (cg-RX-API-DMAC7.html)
EP2614892A3 (en) Static random-access cell, active matrix device and array element circuit
JP2012134961A5 (ja) 回路
JP2011030171A5 (cg-RX-API-DMAC7.html)
JP2008146079A5 (cg-RX-API-DMAC7.html)
WO2010147770A3 (en) Use of emerging non-volatile memory elements with flash memory
JP2010267326A5 (cg-RX-API-DMAC7.html)
JP2016110684A5 (cg-RX-API-DMAC7.html)
JP2014209306A5 (cg-RX-API-DMAC7.html)
RU2016107392A (ru) Полупроводниковое запоминающее устройство
JP2015522800A5 (cg-RX-API-DMAC7.html)
JP2011070761A5 (cg-RX-API-DMAC7.html)
JP2013251888A5 (cg-RX-API-DMAC7.html)
JP2010044850A5 (cg-RX-API-DMAC7.html)
JP2011027877A5 (ja) 信号線駆動回路
JP2010178117A5 (cg-RX-API-DMAC7.html)
JP2014207434A5 (cg-RX-API-DMAC7.html)
ATE470936T1 (de) Digitaler datenpuffer
JP2013527541A5 (cg-RX-API-DMAC7.html)