JP2011044544A - Solid-state image pickup element, method of manufacturing solid-state image pickup element, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup element which can improve the transfer characteristics between an embedded photo diode and a surface diode, and a floating diffusion, while maintaining sensitivity. <P>SOLUTION: The solid-state image pickup element includes a surface photo diode 5 and the floating diffusion 7, on a front surface side of a semiconductor substrate 3. The embedded photo diode 9 is arranged in a semiconductor substrate 3 part, at a position deeper than the surface photodiode 5 and floating diffusion 7. A vertical transfer gate G is arranged, by embedding a gate electrode 15 via a gate insulating film 13, in a hole part 3 formed from between the surface photodiode 5 and a floating diffusion 7 to the embedded photo diode 9. Particularly, curvatures of upper corner parts A5, A7 and lower corner parts B5, B7 of the hole part 3a are smaller on the floating diffusion 7 side than a surface photodiode 5 side. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device including a vertical transistor, a manufacturing method thereof, and an electronic apparatus including the solid-state imaging device.

  In a solid-state imaging device including a photodiode and a transfer gate for reading the charge of the photodiode and a floating diffusion, various configurations for improving sensitivity have been proposed. For example, as in Patent Document 1 below, a configuration has been proposed in which a hole is provided adjacent to the floating diffusion on the surface side of the substrate, and a transfer gate is embedded in the hole to form a vertical transistor configuration. In this case, an area occupied by the photodiode per unit pixel can be increased by adopting a back-illuminated configuration in which an embedded photodiode is provided on the back side of the substrate. Further, with respect to such a back-illuminated configuration, a light receiving sensitivity can be further improved by providing a surface photodiode on the substrate surface opposite to the floating diffusion sandwiching the transfer gate.

  In such a solid-state imaging device having a vertical transistor configuration, the corner portion of the hole portion is a starting point of electric field concentration, and thus has a disadvantage that the withstand voltage characteristic is inferior. In the vertical transistor, a channel region is provided on the inner wall of the hole. However, the inner wall of the hole has many interface states due to etching damage at the time of forming the hole, which causes deterioration of transfer characteristics.

  Therefore, for example, by performing an annealing process or the like, it is necessary to control the shape of the corner of the hole to round the corner or to improve the surface roughness of the inner wall of the hole. As such hole shape control, application of technology used in power semiconductor trench control can be considered. For example, as shown in Non-Patent Document 1 below, silicon migration technology using hydrogen or inert gas annealing, The technology by Etching (CDE) is known.

Japanese Patent Laying-Open No. 2005-223084

Hitoshi Kuribayashi and Ryosuke Shimizu. “Hydrogen pressure Dependence of trench corner rounding during hydrogen annealing”. “J.Vac.Sci.Technol.A22 (4)”, American Vacuum Society, Jul / Aug 2004, p.1406-p.1409

  However, when the shape control technology for the corner of the hole as described above is applied to the manufacture of a solid-state imaging device including both the embedded photodiode and the surface photodiode, the upper corner of the hole extends over the entire circumference. Isotropically rounded. For this reason, although deterioration in transfer characteristics between the embedded photodiode and the floating diffusion is improved by shape control, the surface photodiode formation region is reduced and sensitivity is lowered.

  Therefore, the present invention provides a solid-state imaging device capable of improving transfer characteristics between the embedded photodiode and the floating diffusion while maintaining sensitivity, and a method for manufacturing the same, and further provides the solid-state imaging device. An object of the present invention is to provide an electronic device with high imaging performance and excellent reliability.

  In order to achieve such an object, the solid-state imaging device of the present invention includes a surface photodiode and a floating diffusion on the surface side of the substrate, and includes a buried photodiode at a deeper position. In addition, a vertical transfer gate is provided in which a gate electrode is embedded through a gate insulating film in a hole reaching the embedded photodiode from between the surface photodiode and the floating diffusion. In particular, the curvature of the upper and lower corners of the hole is characterized by being smaller on the floating diffusion side than on the surface photodiode side. Moreover, this invention is also a manufacturing method of such a solid-state image sensor, and an electronic device using the same.

  In the solid-state imaging device having such a configuration, the hole portion provided with the vertical transfer gate has a reduced curvature at the corner portion on the floating diffusion side, so that deterioration of breakdown voltage due to electric field concentration is prevented, and transfer characteristics are reduced. Improvement is achieved. In addition, since the curvature of the corner portion on the surface photodiode side in the hole portion is maintained large, a formation region of the surface photodiode can be secured.

  As described above, according to the present invention, in a solid-state imaging device having a surface photodiode and an embedded photodiode, the area between the embedded photodiode and the floating diffusion is maintained while securing the formation region of the surface photodiode and maintaining the sensitivity. The transfer characteristics can be improved. This also makes it possible to improve the imaging performance and reliability in electronic equipment using this solid-state imaging device.

It is a figure which shows the structure of the solid-state image sensor of 1st Embodiment. It is process drawing (the 1) which shows the manufacturing method of the solid-state image sensor of 2nd Embodiment. It is process drawing (the 2) which shows the manufacturing method of the solid-state image sensor of 2nd Embodiment. It is a block diagram of the electronic device using the solid-state image sensor of 3rd Embodiment.

Hereinafter, embodiments of the present invention will be described in the following order based on the drawings.
1. First Embodiment (Configuration Example of Solid-State Image Sensor)
2. Second Embodiment (Method for Manufacturing Solid-State Image Sensor)
3. Third Embodiment (Example of Electronic Device Using Solid-State Image Sensor)

<< 1. First Embodiment >>
FIG. 1 shows a cross-sectional view and a plan view of a main part for one pixel of the solid-state imaging device of the first embodiment. The principal part sectional view corresponds to the AA ′ section in the plan view.

  A solid-state imaging device 1 shown in these drawings is provided on a semiconductor substrate 3 and includes a surface photodiode 5 and a floating diffusion 7 on the surface side of the semiconductor substrate 3. Further, an embedded photodiode 9 is provided at a position deeper than the surface photodiode 5 and the floating diffusion 7 in the semiconductor substrate 3. A vertical transfer gate G reaching the embedded photodiode 9 is provided between the surface photodiode 5 and the floating diffusion 7. Hereinafter, a detailed configuration of each component will be described.

  First, the semiconductor substrate 3 is made of, for example, low-concentration p-type single crystal silicon.

  The surface photodiode 5 has a configuration in which, for example, a high-concentration n + region 5 a and a lower-concentration n-type region 5 b are sequentially provided from the surface side of the semiconductor substrate 3. A p-type hole accumulation region may be further provided on the surface of the n + region 5a to form an HAD structure.

  The floating diffusion 7 is made of, for example, a high-concentration n + region, and is provided at a distance from the surface photodiode 5.

  The embedded photodiode 9 has a configuration in which, for example, a high-concentration n + region 9a and a lower-concentration n-type region 9b are sequentially provided from the surface side. It is assumed that the embedded photodiode 9 is provided in the pixel at a position overlapping the surface photodiode 5 and in a wide range exceeding this position.

  The transfer gate G has a vertical structure in which a gate electrode 15 is embedded in a hole 3 a provided on the surface side of the semiconductor substrate 3 via a gate insulating film 13.

  Of these holes, the hole 3a is formed between the surface photodiode 5 and the floating diffusion 7 and at the center of the active region 19 separated by a groove-type element isolation 17 (shown only in a plan view) formed in the semiconductor substrate 3. Is provided. The hole 3 a is provided in a state reaching the embedded photodiode 9. In particular, the hole 3a has different shapes on the surface photodiode 5 side and the floating diffusion 7 side. Here, the surface photodiode 5 side is a side disposed close to the surface photodiode 5, and includes at least side walls provided substantially parallel to the surface photodiode 5, upper and lower corner portions thereof, and a bottom portion continuous thereto. Suppose that Similarly, the floating diffusion 7 side is a side disposed close to the floating diffusion 7, and is at least a side wall provided substantially parallel to the floating diffusion 7, its upper and lower corners, and a bottom continuous with the side wall. And

  Here, it is important that the hole 3a is configured such that the curvature of the upper corner A and the lower corner B is smaller on the floating diffusion 7 side than on the surface photodiode 5 side. That is, on the surface photodiode 5 side, the upper corner portion A5 and the lower corner portion B5 of the hole 3a have a large curvature, and are bent sharply from the surface of the semiconductor substrate 3 to the side wall of the hole 3a. The curvature radius of the upper corner portion A5 is, for example, 5 nm or less. On the other hand, on the floating diffusion 7 side, the upper corner portion A7 and the lower corner portion B7 of the hole 3a have a small curvature, and gradually bend from the surface of the semiconductor substrate 3 to the side wall of the hole 3a substantially perpendicular thereto. ing. Also, the hole 3a is gradually bent from the side wall to the bottom surface. The curvature radius of the upper corner A7 is, for example, 5 nm or more.

  As an example, on the floating diffusion 7 side, the upper corner portion A 7 and the lower corner portion B 7 of the hole 3 a may be configured with a facet surface of 45 ° with respect to the surface of the semiconductor substrate 3. On the floating diffusion 7 side, the upper corner portion A7 and the lower corner portion B7 of the hole 3a may be curved.

  Further, in the hole portion 3a, the side wall portion disposed on the groove type element isolation 17 side leaves the surface of the semiconductor substrate 3 between the groove type element isolation 17 and the hole portion 3a.

  Further, the surface roughness of the side wall of the hole 3a is smaller on the floating diffusion 7 side than on the surface photodiode 5 side. That is, on the floating diffusion 7 side, the surface roughness on the side wall of the hole 3a is smaller than that on the surface photodiode 5 side, and the side wall shape is smooth.

  A p-type channel region 11 extending from the buried photodiode 9 to the surface photodiode 5 and the floating diffusion 7 is provided on the side wall of the hole 3 a and the portion along the surface of the semiconductor substrate 3. .

  The gate insulating film 13 is provided so as to cover the inner wall of the hole 3a and the periphery of the semiconductor substrate 3. The film thickness of the gate insulating film 13 varies less in the side wall portion of the floating diffusion 7 than in the side wall portion of the surface photodiode 5 in the inner wall of the hole 3a. The film thickness variation is smaller than [maximum value / minimum value] = 1.8, preferably [maximum value / minimum value] = 1.2 to 1.4 on the floating diffusion 7 side. .

  The gate electrode 15 is embedded in the hole 3 a via the gate insulating film 13, and is extended on the semiconductor substrate 3 at the periphery of the hole 15, between the surface photodiode 5 and the hole 3 a, and in the floating diffusion 7. And the channel region 11 between the hole 3a. However, the channel region 11 on the surface of the semiconductor substrate 3 between the surface photodiode 5 and the hole 3 a and between the floating diffusion 7 and the hole 3 a does not have to be completely covered with the gate electrode 15. Further, the impurity concentration of the channel region 11 on the surface of the semiconductor substrate 3 is appropriately adjusted.

  The solid-state imaging device 1 configured as described above has a vertical transistor configuration including a vertical transfer gate 15. In this solid-state imaging device 1, by applying a voltage to the transfer gate electrode 15, the p-type channel region 11 is inverted to the n-type.

  Thereby, the electric charge accumulated in the surface photodiode 5 is transferred to the floating diffusion 7 via the channel region 11 on the surface of the semiconductor substrate 3. On the other hand, the charges accumulated in the embedded photodiode 9 are transferred to the floating diffusion 7 via the channel region 11 on the side wall of the hole 3 a and the channel region 11 on the surface of the semiconductor substrate 3.

  In the solid-state imaging device 1, the back surface side of the semiconductor substrate 3 on which the embedded photodiode 9 is disposed may be used as the light receiving surface. As a result, the arrangement area of the embedded photodiode 9 can be maximized and sensitivity can be improved without being affected by the floating diffusion 7 or the vertical transfer gate G.

  In the solid-state imaging device 1 having the above-described configuration, the hole 3 a provided with the vertical transfer gate G is an upper corner on the floating diffusion 7 side that is a transport path of charges accumulated in the embedded photodiode 9. The curvatures of A7 and lower corner B7 are small. For this reason, deterioration of the breakdown voltage due to electric field concentration is prevented. The inner wall of the hole 3a on the floating diffusion 7 side is a path for transporting charges accumulated in the embedded photodiode 9, and the surface roughness of this portion and the film thickness variation of the gate insulating film 13 are different from those of the surface photodiode. Smaller than 5 side. From the above, the transfer characteristics between the embedded photodiode 9 and the floating diffusion 7 are improved. In addition, since the charge accumulated in the surface photodiode 5 uses the surface of the semiconductor substrate 3 as a transport path, the transfer characteristic is maintained well without being affected by the shape and surface state of the hole 3a.

  Moreover, the curvature of the upper corner portion A7 on the surface photodiode 5 side in the hole 3a is maintained large. For this reason, the formation region of the surface photodiode 5 can be secured, and the sensitivity can be improved.

  As a result, in the solid-state imaging device 1 having the surface photodiode 5 and the embedded photodiode 9, it is possible to achieve both improvement in charge transfer characteristics and improvement in sensitivity.

≪2. Second Embodiment >>
Next, the manufacturing method of the solid-state imaging device of the first embodiment will be described based on the manufacturing process diagrams of FIGS.

  First, as shown in FIG. 2A, after groove type element isolation (not shown) is formed on the surface side of the semiconductor substrate 3 made of p-type single crystal silicon, the semiconductor substrate 3 is formed by ion implantation. Each region is sequentially formed by introducing impurities. For example, first, an n-type region 9 b and a shallower n + region 9 a are formed in a deep position of the semiconductor substrate 3 to form the buried photodiode 9. Next, an n-type region 5b and an n + region 5a shallower than the n-type region 5a are formed on the surface side of the semiconductor substrate 1 so as to overlap with the embedded photodiode 9, thereby forming the surface photodiode 5. Further, a floating diffusion 7 composed of an n + region is formed at a position separated from the surface photodiode 5 on the surface side of the semiconductor substrate 1.

  Next, as shown in FIG. 2B, an inorganic mask 21 made of a silicon-based insulating film such as silicon oxide or silicon nitride is formed on the semiconductor substrate 3. Here, for example, a silicon-based insulating film is formed on the semiconductor substrate 3 by chemical vapor deposition (CVD), and a resist pattern is formed thereon by photolithography, and this is used as a mask. The silicon insulating film is etched. Thereby, the inorganic mask 21 is formed.

  Next, by etching the semiconductor substrate 3 from above the inorganic mask 21, a hole 3 a reaching the embedded photodiode 9 is formed between the surface photodiode 5 and the floating diffusion 7. At this time, by performing anisotropic dry etching, the hole 3a having a depth (for example, about 1.0 μm) enough to reach the embedded photodiode 9 is formed with a constant opening diameter.

Next, as shown in FIG. 2 (3), a sacrificial oxide film 23 is formed on the inner wall of the hole 3a. The sacrificial oxide film 23 is formed by applying a method that has little effect on the plane orientation and has an effect of rounding the shapes of the upper corner portion A and the lower corner portion B of the hole 3a. As such a method, for example, a radical oxidation process using hydrogen (H ₂ ) or oxygen (O ₂ ) as a source gas is applied.

  Thereafter, as shown in FIG. 2 (4), boron (B) is formed on the surface of the semiconductor substrate 3 and the portion along the inner wall of the hole 3a by ion implantation through the sacrificial oxide film 23 and the inorganic mask 21. A channel region 11 is formed by introducing a p-type impurity such as. This channel region 11 serves as a buried channel of the transfer gate formed in the hole 3 a, and is sufficient for the impurity concentration of the surface photodiode 5, floating diffusion 7, and embedded photodiode 9 that are already formed. The concentration is low. Therefore, the p-type channel region 11 is formed in a state where it is joined to the embedded photodiode 9, the surface photodiode 5 and the floating diffusion 7. The channel region 11 is formed to a depth of about several tens of nanometers.

  Next, as shown in FIG. 3A, a resist pattern 25 is formed on the semiconductor substrate 3. The resist pattern 25 has a shape that continuously covers at least the surface photodiode 5 and the side wall and bottom of the hole 3a on the surface photodiode 5 side. The resist pattern 25 has a shape that continuously exposes at least the floating diffusion 7 and the side wall and the bottom of the hole 3a on the floating diffusion 7 side. Further, the groove-type element isolation side is covered with a resist pattern 25 as necessary when the gap between the hole 3a and the groove-type element isolation is narrow.

  In this state, the sacrificial oxide film 23 exposed from the resist pattern 25 is removed by etching using a dilute hydrofluoric acid aqueous solution. When the inorganic mask 21 is made of silicon oxide, the inorganic mask 21 exposed from the resist pattern 25 is simultaneously etched away. On the other hand, when the inorganic mask is made of silicon nitride, the inorganic mask 21 exposed from the resist pattern 25 is removed by etching using a hot phosphoric acid solution. After the etching is completed, the resist pattern 25 is removed.

  Next, as shown in FIG. 3B, the sacrificial oxide film 23 and the inorganic mask 21 are used as protective films, and shape control is performed so that the corners A7 and B7 of the hole 3a exposed from these are rounded. . Here, the shape control is performed by adopting any of the following steps 1) to 3).

1) Method by annealing treatment Annealing treatment is performed in a gas containing hydrogen (H ₂ ), argon (Ar), and helium (He). Thereby, silicon is migrated only at the exposed portion of the semiconductor substrate 3. An example of annealing conditions is as follows.
Substrate temperature: 800-1100 ° C
Processing atmosphere pressure: 5 to 760 Torr
Processing time: 30 seconds to 5 minutes

  In the above annealing process, silicon migrates only in the exposed portion of the semiconductor substrate 3 that is not covered with the protective film made of the sacrificial oxide film 23 and the inorganic mask 21. Thereby, the corners A7 and B7 of the hole 3a are rounded on the floating diffusion 7 side, and the curvature is reduced. If the semiconductor substrate 3 has a (100) plane of single crystal silicon as the main surface, the corners A7 and B7 of the hole 3a are silicon inclined at 45 ° with respect to the surface of the semiconductor substrate 3. The facet plane is composed of (110) plane and (100) plane. The facet surface is 45 ° with respect to the surface of the semiconductor substrate 3.

  On the other hand, on the surface photodiode 5 side covered with the sacrificial oxide film 23 and the inorganic mask 21, the corners A7 and B7 of the hole 3a are kept substantially vertical.

  In addition, the side wall of the hole 3a is in a state of being damaged by etching during the formation of the hole 3a, but the exposed portion of the side wall of the hole 3a is reduced in the interface state due to silicon migration and has a surface roughness. Get smaller. Thereby, the shape of the side wall of the hole 3a is controlled so that the surface roughness is smaller on the floating diffusion 7 side than on the surface photodiode 5 side.

2) Method by chemical dry etching Isotropic dry etching (CDE) containing tetrafluoromethane (CF ₄ ) and oxygen (O ₂ ) is performed. As a result, the semiconductor substrate 3 is isotropically etched only in the exposed portion of the semiconductor substrate 3 that is not covered with the sacrificial oxide film 23 and the inorganic mask 21, and the corners A7 and B7 of the hole 3a on the floating diffusion 7 side are rounded. It is done. Further, the exposed portion of the side wall of the hole 3a is reduced in the interface state by etching and the surface roughness is reduced. As a result, the surface roughness of the side wall of the hole 3a is smaller on the floating diffusion 7 side than on the surface photodiode 5 side.

3) Method by wet etching Wet etching is performed with a chemical solution containing hydrofluoric acid (HF) and ethylene glycol (C ₂ H ₆ O ₂ ). As a result, as in 2), the corners A7 and B7 of the hole 3a on the floating diffusion 7 side are rounded, and the side wall of the hole 3a has a smaller surface roughness on the floating diffusion 7 side than on the surface photodiode 5 side. Become.

  After performing shape forming by any of the above methods, the protective film made of the sacrificial oxide film 23 and the inorganic mask 21 is removed by dilute hydrofluoric acid treatment or hot phosphoric acid treatment.

  Next, as shown in FIG. 3C, a gate insulating film 13 is formed on the semiconductor substrate 3 including the inner wall of the hole 3a. The gate insulating film 13 is formed with a film thickness of 5 to 10 nm. The formation of the gate insulating film 13 is preferably applied with a radical oxidation process having low substrate surface orientation dependency and effective in rounding corners and reducing roughness.

For forming the gate insulating film 13 by radical oxidation, for example, a silicon oxide film is formed by heat treatment at 800 ° C. to 1100 ° C. using hydrogen (H ₂ ) or oxygen (O ₂ ) as a source gas. Alternatively, a silicon oxide film may be formed by plasma oxidation at room temperature to 400 ° C. using hydrogen (H ₂ ) or oxygen (O ₂ ) as a source gas.

  The gate insulating film 13 obtained as described above has a variation in film thickness depending on the surface roughness of the base. For this reason, in the inner wall of the hole 3a, the surface roughness is smaller on the floating diffusion 7 side than on the surface photodiode 5 side. For this reason, the gate insulating film 13 having a smaller film thickness variation on the floating diffusion 7 side than the surface photodiode 5 side is formed on the inner wall of the hole 3a. The film thickness variation is smaller than [maximum value / minimum value] = 1.8, preferably [maximum value / minimum value] = 1.2 to 1.4 on the floating diffusion 7 side. .

  The gate insulating film 13 as described above is applied to all circuits in the pixel portion. In radical oxidation, since there is no fluctuation in film formation speed due to impurities in the semiconductor substrate 3, insulating films having the same film thickness are formed in all pixel circuit portions having different impurity concentrations.

Next, as shown in FIG. 3 (4), an electrode material film 15 a is formed on the semiconductor substrate 3 in a state of filling the hole 3 a through the gate insulating film 13. The electrode material film 15a is made of, for example, polysilicon or amorphous silicon. The electrode material film 15a made of these materials is formed by chemical vapor deposition (CVD) using silane (SiH ₄ ), phosphine (PH ₃ ), and hydrogen (H ₂ ) as source gases. Formed by.

  Thereafter, as shown in FIG. 1, by patterning the electrode material film 15a, the gate electrode 15 having a shape covering the hole 3a and the periphery thereof is formed in the gate width direction between the surface photodiode 5 and the floating diffusion 7. Form.

  As described above, the solid-state imaging device 1 having the floating diffusion 7 and the vertical transfer gate G together with the surface photodiode 5 and the embedded photodiode 9 can be obtained.

  According to such a manufacturing method, as described with reference to FIG. 3B, the corners A7, B7 of the hole 3a, which serve as a charge transfer path between the embedded photodiode 9 and the floating diffusion 7, and The shape of the inner wall portion is controlled to improve the transfer characteristics. At this time, the corners A5 and B5 of the hole 3a on the surface photodiode 5 side are kept in a state where the hole 3a is formed by etching, so that the formation area of the surface photodiode 5 can be secured.

  Therefore, it is possible to obtain the solid-state imaging device 1 that has achieved both the improvement in transfer efficiency and the improvement in sensitivity.

≪3. Third Embodiment >>
FIG. 4 shows a configuration diagram of an electronic apparatus provided with the above-described solid-state imaging device as a third embodiment of the present invention.

  The electronic device 200 illustrated in FIG. 4 includes an imaging region 210 in which solid-state imaging elements are arrayed in the imaging unit 201. A condensing optical unit 202 that forms an image is provided on the condensing side of the image pickup unit 201, and the image pickup unit 201 has a drive circuit that drives the image pickup unit 201 and a signal photoelectrically converted in the image pickup region 210. A signal processing unit 203 having a signal processing circuit or the like for processing is connected. The image signal processed by the signal processing unit 203 can be stored by an image storage unit (not shown). In such an electronic device 200, the solid-state imaging device 1 described in the above embodiment can be arranged in the imaging region 210.

  Since the electronic device 200 of the present invention uses the solid-state imaging device 1 described in the first embodiment and the second embodiment, it is possible to improve the imaging performance and reliability in the imaging unit 201.

  In addition, the electronic device 200 may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. May be. The electronic device 200 here is a general device having an imaging function, such as a digital camera, a personal computer, a video camera, a television, and a portable terminal device represented by a mobile phone. “Imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  DESCRIPTION OF SYMBOLS 1 ... Solid-state image sensor, 3 ... Semiconductor substrate, 3a ... Hole, 5 ... Surface photodiode, 7 ... Floating diffusion, 9 ... Embedded photodiode, 11 ... Channel area | region, 13 ... Gate insulating film, 15 ... Gate electrode, DESCRIPTION OF SYMBOLS 21 ... Inorganic mask (protective film), 23 ... Sacrificial oxide film (protective film), A5, A7 ... Upper corner part, B5, B7 ... Lower corner part, G ... Transfer gate, 200 ... Electronic device

Claims (8)

A surface photodiode provided on the surface side of the semiconductor substrate;
A floating diffusion provided on the surface side of the semiconductor substrate;
An embedded photodiode provided in the semiconductor substrate portion at a position deeper than the surface photodiode and the floating diffusion;
A transfer gate formed by embedding a gate electrode through a gate insulating film in a hole provided to reach the embedded photodiode from between the surface photodiode and the floating diffusion;
The curvature of the upper and lower corners of the hole is smaller on the floating diffusion side than on the surface photodiode side. The solid-state imaging device according to claim 1, wherein the surface roughness of the side wall of the hole is smaller on the floating diffusion side than on the surface photodiode side. 3. The solid-state imaging device according to claim 1, wherein a variation in film thickness of the gate insulating film is smaller on the floating diffusion side than on the surface photodiode side. The solid-state imaging device according to claim 1, wherein an upper corner portion and a lower corner portion of the hole portion on the floating diffusion side are configured with a facet surface of 45 ° with respect to the surface of the semiconductor substrate. 5. The transfer gate according to claim 1, wherein the transfer gate extends on a semiconductor substrate beside the hole and covers a channel region between the hole, the surface photodiode, and the floating diffusion. Solid-state image sensor. The solid-state imaging device according to claim 1, wherein a back surface of the semiconductor substrate is used as a light receiving surface. Forming a surface photodiode and a floating diffusion on the surface side of the semiconductor substrate, and forming an embedded photodiode at a position overlapping the surface photodiode in the semiconductor substrate;
Forming a hole reaching the formation planned region of the buried photodiode between the surface photodiode and the floating diffusion formation planned region on the surface side of the semiconductor substrate;
Forming a protective film that covers from the surface photodiode to the inner wall facing the photodiode in the hole and exposing the floating diffusion to the inner wall facing the floating diffusion in the hole;
Performing a process of reducing the curvature of the exposed portion of the corner in the hole using the protective film as a mask;
A step of forming a vertical transfer gate provided with a gate electrode through a gate insulating film in a state in which the protective film is removed and the hole is embedded, after performing the process of reducing the curvature Manufacturing method. A surface photodiode provided on the surface side of the semiconductor substrate;
A floating diffusion provided on the surface side of the semiconductor substrate;
An embedded photodiode provided in the semiconductor substrate portion at a position deeper than the surface photodiode and the floating diffusion;
A solid-state imaging device having a transfer gate formed by embedding a gate electrode through a gate insulating film in a hole provided between the surface photodiode and the floating diffusion so as to reach the embedded photodiode. And
An electronic device in which the curvature of the upper and lower corners of the hole is smaller on the floating diffusion side than on the surface photodiode side.

Images