JP2011014751A - Solid-state image sensor, transistor, method of manufacturing the transistor, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image sensor having vertical transistors superior in characteristics by forming a channel region with self-alignment.SOLUTION: The solid-state image sensor 1 includes: a channel region 15 comprising a semiconductor layer that is grown on an inner wall of a hole 13 provided in a semiconductor substrate 3; a gate insulating film 17 covering the channel region 15; a read-out gate electrode 19tg provided in the hole 13 through the gate insulating film 17; and photo-diodes PD1 and PD2 provided on the semiconductor substrate 3, from which electric charges are read out by switching on or off the read-out gate electrode 19tg.

Description

  The present invention relates to a solid-state imaging device having a vertical transistor, a vertical transistor and a method for manufacturing the same, and an electronic apparatus using the same.

  In a solid-state imaging device including a photodiode and a transistor that reads out electric charges photoelectrically converted by the photodiode, the transistor is made vertical for the purpose of reducing the area occupied by the element and increasing the light receiving area of the photodiode. A configuration is proposed.

  In the manufacture of a vertical transistor, an impurity region is formed on the inner wall of a hole formed in a semiconductor substrate by ion implantation, and then a gate insulating film is formed so as to cover the inner wall of the hole. A gate electrode is formed in a state of filling (see Patent Document 1 below).

Japanese Patent Laying-Open No. 2005-223084 (see FIG. 5 and paragraph 0039)

  However, in such a manufacturing procedure as described above, it is difficult to introduce impurities into a deep position of the hole, and an impurity region cannot be formed with good shape accuracy along the inner wall of the hole. For this reason, it is difficult to form a channel region with good shape accuracy and concentration profile along the inner wall of the hole. Therefore, a vertical transistor having stable characteristics cannot be obtained, which is a factor that hinders realization of a solid-state imaging device using the vertical transistor.

  Therefore, the present invention provides a vertical transistor having good characteristics by forming a channel region by self-alignment, and a solid-state imaging device in which miniaturization is achieved by providing this transistor. With the goal.

  In order to achieve such an object, the solid-state imaging device of the present invention has a channel region in which a semiconductor layer is grown on the inner wall of a hole provided in a semiconductor substrate. A gate electrode is provided in the hole through a gate insulating film covering the channel region. Further, the semiconductor substrate is provided with a photodiode from which charges are read by turning on and off the gate electrode.

  The present invention is also a vertical transistor having the above structure and a method for manufacturing the same. The manufacturing method of the vertical transistor is performed by the following procedure. First, in the first step, a hole is formed in the semiconductor substrate, and in the next second step, a channel region made of a semiconductor layer selectively epitaxially grown on the inner wall of the hole is formed. Thereafter, in the third step, a gate insulating film is formed so as to cover the channel region, and in the fourth step, a gate electrode is formed.

  Furthermore, the present invention is also an electronic device provided with the solid-state imaging device.

  Since the transistor having the above structure uses a semiconductor layer grown on the inner wall of the hole of the semiconductor substrate as a channel region, the channel region is provided in a self-aligned manner with respect to the inner wall of the hole.

  As described above, according to the present invention, since the channel region can be formed with high accuracy by self-alignment with respect to the inner wall of the hole, a vertical transistor having excellent characteristics can be obtained. In addition, by using such a vertical transistor with good characteristics together with a photodiode, it is possible to achieve miniaturization of the solid-state imaging device and miniaturization of an electronic device including the solid-state imaging device.

It is a figure which shows the structure of the solid-state image sensor of 1st Embodiment. It is a figure which shows the characterizing part of the vertical transistor provided in the solid-state image sensor of 1st Embodiment. It is process drawing (the 1) which shows the manufacturing method of the solid-state image sensor of 1st Embodiment. It is process drawing (the 2) which shows the manufacturing method of the solid-state image sensor of 1st Embodiment. It is process drawing (the 3) which shows the manufacturing method of the solid-state image sensor of 1st Embodiment. It is process drawing (the 4) which shows the manufacturing method of the solid-state image sensor of 1st Embodiment. It is process drawing (the 5) which shows the manufacturing method of the solid-state image sensor of 1st Embodiment. It is a figure which shows the structure of the solid-state image sensor of 2nd Embodiment. It is a figure which shows the characteristic part in the manufacturing method of the solid-state image sensor of 2nd Embodiment. It is a block diagram of the electronic device using the solid-state image sensor of 1st Embodiment.

Hereinafter, embodiments of the present invention will be described in the following order based on the drawings.
1. First Embodiment (First Example of Configuration of Solid-State Image Sensor Using Vertical Transistor)
2. Second Embodiment (Second Example of Configuration of Solid-State Image Sensor Using Vertical Transistor)
3. Third Embodiment (Example of Electronic Device Using Solid-State Image Sensor)
In the first embodiment and the second embodiment, the configuration of the solid-state imaging device will be described, and then the manufacturing method of the solid-state imaging device will be described.

<< 1. First Embodiment >>
<Configuration of solid-state image sensor>
FIG. 1 shows a cross-sectional view of the main part of one pixel and a plan view of four pixels of the solid-state imaging device according to the first embodiment. The principal part sectional view corresponds to the AA ′ section in the plan view.

  The solid-state imaging device 1 shown in these drawings includes a vertical transistor Tr and a floating diffusion FD in addition to two photodiodes PD1 and PD2 in each pixel, and is configured as follows.

  That is, the semiconductor substrate 3 has, for example, a (100) plane of single crystal silicon as a main surface and is made of n-type single crystal silicon. On the main surface side of the semiconductor substrate 3, for example, a trench type isolation (shallow trench isolation: hereinafter referred to as STI) 5 is provided for separating two pixels as a set and separating the peripheral elements. It has been. STI 5 shows only a plan view.

  Among these, each pixel is provided with a sensor region 3a in which the photodiodes PD1 and PD2 are disposed, and a floating diffusion region 3b having a floating diffusion FD. A read gate electrode 19tg having a buried structure is provided between each sensor region 3a and the floating diffusion region 3b to constitute a vertical transistor Tr. Here, one floating diffusion region 3b is shared by the sensor regions 3a of two pixels, and one readout gate electrode 19tg is shared by the sensor regions 3a of two pixels of different combinations.

  Here, in the sensor region 3a (refer to the cross-sectional view), a surface photodiode PD1 made of an n + type region is provided on the surface side, and a buried photodiode PD2 made of an n + type region is provided at a deeper position. A p-type region 7 is provided in the surface layer of the semiconductor substrate 3 above the surface photodiode PD1 to form a HAD sensor structure. The p-type region 7 may be in contact with the n + -type region constituting the surface photodiode PD1 or may be provided with an interval.

  Further, p-type isolation regions 9 and 11 adjacent to each other in the depth direction are provided in the photodiodes PD1 and PD2 each including the n + -type region. In particular, it is assumed that the p-type isolation region 11 adjacent in the depth direction of the embedded photodiode PD2 is continuously provided as a common region for all pixels.

  On the other hand, the floating diffusion region 3b is provided with a floating diffusion FD composed of an n + type region on the surface side. A p-type isolation region 23 is provided at a position deeper than the floating diffusion FD.

  In addition, the vertical transistor Tr uses the photodiodes PD1 and PD2 in the sensor region 3a and the floating diffusion FD in the floating diffusion region 3b as source and drain. The vertical transistor Tr includes a p-type channel region 15 along the inner wall of the hole 13 provided in the semiconductor substrate 3. The channel region 15 is characterized by being composed of a semiconductor layer epitaxially grown on the inner wall of the hole 13. Such a channel region 15 may be disposed at a distance from the surface photodiode PD1 and the floating diffusion FD, or may be disposed in a joined state. Further, it is preferably arranged in a bonded state with respect to the embedded photodiode PD2.

  A gate insulating film 17 is provided on the semiconductor substrate 3 so as to cover the channel region 15 and the semiconductor substrate 3 as described above, and a read gate electrode 19tg is formed in the hole 13 through the gate insulating film 17. Embedded. The read gate electrode 19tg is patterned so as to cover the channel region 15 and cover the channel region 15 and the surface photodiode PD1, and further cover the channel region 15 and the floating diffusion FD above the semiconductor substrate 3. Suppose that An insulating side wall 21 may be provided on the side wall of each read gate electrode 19tg.

  Here, FIG. 2 shows an enlarged view of the vertical transistor Tr portion. As shown in this figure, the channel region 15 made of a semiconductor layer epitaxially grown on the inner wall of the hole 13 is characterized in that the inner wall B forms an octagonal column. Here, the semiconductor substrate 3 has a (100) plane of single crystal silicon as a main surface, and the inner wall is an octagonal prism composed of the (100) plane and (110) plane of single crystal silicon. The channel region 15 has a second feature that the upper end surface C is a facet surface inclined in the depth direction at the center of the hole portion 13.

  In the vertical transistor Tr configured as described above, the p-type channel region 15 is inverted to the n-type by applying a voltage to the read gate electrode 19tg. Further, the surface layer D of the n-type semiconductor substrate 3 immediately below the read gate electrode 19tg is an n + type having a high n-type concentration.

  As a result, the charges accumulated in the n + type surface photodiode PD1 are the surface layer D of the n + type semiconductor substrate 3, the channel region 15 inverted to the n type, and the surface layer of the semiconductor substrate 3 of the n + type. It is read to the floating diffusion FD via D. Further, the charges accumulated in the n + type buried photodiode PD2 are read out to the floating diffusion FD through the channel region 15 inverted to the n type and the surface layer D of the n + type semiconductor substrate 3.

  In the peripheral region of each pixel portion configured as described above, a reset gate 19rg and an n + type reset drain RD provided in a self-alignment manner using the reset gate rg as a mask are provided. In other peripheral regions, an amplifier gate 19ag and an n + type source region AS provided by self-alignment using the amplifier gate 19ag as a mask are provided.

  The reset gate 19rg and the amplifier gate 19ag are configured in the same layer as the read gate electrode 19tg. However, holes need not be formed below the reset gate 19rg and the amplifier gate 19ag.

  On the semiconductor substrate 3 on which the above gate electrodes 19tg, 19rg, and 19ag are formed, an interlayer insulating film 29 is provided via a passivation film 27 (see a sectional view). In the interlayer insulating film 29 and the passivation film 27, connection holes 29a reaching the gate electrodes 19tg, 19rg, 19ag, the floating diffusion FD, the n + type reset drain RD, and the source region AS are provided.

  A wiring 31 is provided on the interlayer insulating film 29. The wiring 31 is provided in a state where the floating diffusion FD and the reset drain RD are connected via the connection hole 29a, and the other reset drain RD and the source region AS are connected.

<Method for Manufacturing Solid-State Imaging Device>
Next, the manufacturing method of the solid-state imaging device of the first embodiment will be described based on the manufacturing process diagrams of FIGS. 3 to 7 are a cross-sectional view of a main part of the solid-state imaging device and a plan view of four pixels, and the cross-sectional view of the main part corresponds to the AA ′ cross section in the plan view.

  First, as shown in FIG. 3, a pixel region in which a vertical transistor and a photodiode are provided by forming STI 5 (illustrated only in a plan view) on one main surface side of a semiconductor substrate 3 made of n-type single crystal silicon. And the surrounding area are separated.

  Next, impurities are introduced into the semiconductor substrate 3 to form each region sequentially. For example, first, the p-type isolation region 11 is formed in the entire region where the pixels are provided. Next, an embedded photodiode PD2 composed of an n + type region is formed in the sensor region 3a, and a p type isolation region 9, a surface photodiode PD1 composed of an n + type region, and a p type region 7 constituting the HAD sensor structure are formed. Form in order. Further, a p-type isolation region 23 is formed in the floating diffusion region 3b, and then a floating diffusion FD composed of an n + type region is formed.

  Each of the n-type region and the p-type region is formed by ion implantation from above the mask pattern and activation of impurities by subsequent heat treatment through a thin silicon oxide film not shown here.

  Next, as shown in the sectional view and the plan view of FIG. 4, a mask pattern 41 made of an inorganic material such as silicon oxide or silicon nitride is formed on the semiconductor substrate 3 on which the photodiode PD or the like is formed. The mask pattern 41 includes a hole 41a that opens between the photodiodes PD1 and PD2 and the floating diffusion FD. The mask pattern 41 is formed by forming a resist pattern (not shown) on the inorganic material film, and forming a hole 41a formed by anisotropic etching of the inorganic material film using the resist pattern as a mask. It is done by providing. The resist pattern is removed after anisotropic etching.

  Thereafter, as shown in the sectional view and the plan view of FIG. 4, the semiconductor substrate 3 is etched from above the mask pattern 41 to form the hole 13. The hole 13 is in contact with the embedded photodiode PD2, exposes the isolation region 11 at the bottom, has an opening diameter of 0.3 to 0.8 μm (for example, 0.5 μm), and a depth of 0.6 to 1.5 μm. (1.15 m as an example).

For this etching, anisotropic dry etching is applied, for example, under the following conditions.
Etching atmosphere pressure: 125 (mTorr)
Bias power: 450 (W)
Etching gas and flow rate:
HBr = 230 (sccm)
NF ₃ = 35 (sccm)
O ₂ = 17 (sccm)

The above is an example of the etching conditions, and the etching conditions for forming the hole 13 can be performed within the following condition range.
Etching atmosphere pressure: 20 to 200 (mTorr)
Bias power: 200 to 1000 (W)
Etching gas and flow rate:
HBr = 20 to 400 (sccm)
NF ₃ = 0 to 50 (sccm)
O ₂ = 5 to 50 (sccm)

  After the hole 13 is formed by the above etching, a cleaning process is performed to remove etching deposits and natural oxide films generated during the etching. Since it is necessary to completely remove the etching deposit and the natural oxide film, it is desirable to perform a cleaning process using hydrofluoric acid.

  Next, as shown in FIG. 5, a channel region 15 made of a semiconductor layer is formed on the inner wall of the hole 13 that is the exposed surface of the semiconductor substrate 3 by selective epitaxial growth. At this time, the channel region 15 is formed by epitaxially growing p-type silicon by using a gas containing p-type impurities in the film forming gas.

  As shown in FIG. 2, the channel region 15 formed here has a thickness of about 0.05 to 0.2 μm (as an example, 0.15 μm) on the side wall of the hole 13. The opening diameter is narrowed. For example, if the original hole 13 has an opening diameter of 0.5 μm and a depth of 1.15 μm, and the film thickness of the channel region 15 is 0.15 μm, the hole 13 has an opening diameter of 0.2 μm and a depth of 1.00 μm. Thus, the aspect ratio is 5.

Such selective epitaxial growth of the channel region 15 is performed under the following conditions, for example.
Growth atmosphere pressure: 50 (Torr)
Growth atmosphere temperature: 700 ° C
Growth gas and flow rate SiH ₂ Cl ₂ = 80 (sccm)
B ₂ H ₆ (B ₂ H ₆ concentration: 100 ppm / H ₂ ) = 0.1 (sccm)
HCl = 15 (sccm)
H ₂ = 20 (slm)

The above is an example of selective epitaxial growth conditions, and the selective epitaxial growth conditions for forming the channel region 15 made of a p-type semiconductor layer can be performed within the following condition range.
Growth atmosphere pressure: 20-80 (Torr)
Growth atmosphere temperature: 650-750 ° C.
Growth gas and flow rate SiH ₂ Cl ₂ = 40 to 120 (sccm)
B ₂ H ₆ (B ₂ H ₆ concentration: 100 ppm / H ₂ ) = 0.01 to 1 (sccm)
HCl = 5 to 125 (sccm)
H ₂ = 10~30 (sccm)

As another example of conditions for selective epitaxial growth of the channel region 15, SiH ₄ may be used as a film forming gas serving as a silicon supply source. Since SiH ₄ has no Cl group for etching silicon, it can be expected to accelerate the selective epitaxial growth rate.

Such selective epitaxial growth of the channel region 15 is performed under the following conditions, for example.
Growth atmosphere pressure: 50 (Torr)
Growth atmosphere temperature: 700 ° C
Growth gas and flow rate SiH ₄ = 40 (sccm)
B ₂ H ₆ (B ₂ H ₆ concentration: 100 ppm / H ₂ ) = 0.1 (sccm)
HCl = 30 (sccm)
H ₂ = 20 (slm)

The above is an example of selective epitaxial growth conditions, and the selective epitaxial growth conditions for forming the channel region 15 made of a p-type semiconductor layer can be performed within the following condition range.
Growth atmosphere pressure: 20-80 (Torr)
Growth atmosphere temperature: 650-750 ° C.
Growth gas and flow rate SiH ₄ = 20-60 (sccm)
B ₂ H ₆ (B ₂ H ₆ concentration: 100 ppm / H ₂ ) = 0.01 to 1 (sccm)
HCl = 10-50 (sccm)
H ₂ = 10~30 (sccm)

  In the selective epitaxial growth as described above, flow of silicon atoms due to heat occurs. As a result, on the inner wall of the hole 13 formed in the semiconductor substrate 3 whose main surface is the (100) plane of single crystal silicon, a semiconductor layer whose surface is constituted only by the (110) plane and the (100) plane of silicon. (Channel region 15) is formed. As a result, the inner side wall constituted by the channel region 15 becomes an octagonal prism constituted by the (100) plane and the (110) plane of single crystal silicon. The channel region 15 is a facet surface whose upper end surface is inclined in the depth direction at the center of the hole 13.

  Moreover, the plasma damage of the inner wall of the hole 13 caused by the dry etching when forming the hole 13 is recovered by the flow of the silicon atoms described above.

  After the selective epitaxial growth as described above, the insulating film 41 shown only in the sectional view is removed. At this time, when the insulating film 41 is made of silicon nitride, wet etching using phosphoric acid is performed. When the insulating film 41 is made of silicon oxide, wet etching using hydrofluoric acid is performed.

  Next, as shown in FIG. 6, a gate insulating film 17 made of silicon oxide is formed on the semiconductor substrate 3 so as to cover the inner wall of the channel region 15. The thickness of the gate insulating film 17 is about 3.0 nm to 10.0 nm (for example, 6.0 nm). The gate insulating film 17 may be formed by a thermal oxidation method or a plasma oxidation method (In Situ Steam Generation: ISSG).

  Thereafter, gate electrodes 19tg, 19rg, and 19ag are formed. At this time, first, a semiconductor material film such as polysilicon or phosphorus-doped amorphous silicon (PDAS), a metal material film, or the like is formed with a film thickness that fills the inside of the hole 13, and this is patterned to form each gate electrode 19tg, 19 rg and 19 ag are formed. Further, in particular, the read gate electrode 19tg covers the channel region 15 above the semiconductor substrate 3, and covers the channel region 15 and the surface photodiode PD1, and further covers the channel region 15 and the floating diffusion FD. Patterned.

  Next, although not shown here, a low concentration LDD region is formed by introducing an n-type impurity using the reset gate electrode 19rg and the amplifier gate electrode 19ag as a mask, and the reset gate electrode 19rg and the amplifier gate electrode 19ag. An insulating sidewall is formed on the sidewall. By this step, the side wall 21 is also formed on the side wall of the read gate electrode 19tg.

  Next, as shown in FIG. 7, a reset drain RD and a source region AS made of an n + type region are formed beside the reset gate electrode 19rg and the amplifier gate electrode 19ag. At this time, a pixel pattern provided with the photodiodes PD1 and PD2 and the floating diffusion FD is covered with a resist pattern not shown here. Then, an n-type impurity is introduced using the resist pattern, the reset gate electrode 19rg, the amplifier gate electrode 19ag, and the sidewall as a mask. As a result, the n + type reset drain RD and the source region AS are formed by self-alignment with the gate electrodes 19tg, 19rg, 19ag.

  Thereafter, as shown in FIG. 1, an interlayer insulating film 29 is formed on the semiconductor substrate 3 via a passivation film 27. Next, connection holes 29a reaching the gate electrodes 19tg, 19rg, 19ag, the floating diffusion FD, the reset drain RD, and the source region AS are formed in the interlayer insulating film 29 and the passivation film 27. Next, the wiring 31 is formed in a state where the floating diffusion FD and the reset drain RD are connected via the connection hole 29a, and the other reset drain RD and the source region AS are connected.

  After the above, if necessary, an upper insulating film and an upper wiring are formed to form a multilayer wiring structure. Finally, a protective insulating film is formed on the multilayer wiring structure, and a color filter and an on-chip lens are formed thereon. Thus, the target surface irradiation type CMOS solid-state imaging device 1 is obtained.

  In the first embodiment described above, the semiconductor layer grown on the inner wall of the hole 13 of the semiconductor substrate 3 is used as the channel region 15. For this reason, the channel region 15 of the vertical transistor Tr is formed in a self-aligned manner with good accuracy with respect to the inner wall of the hole portion 13, and the characteristics of the vertical transistor Tr can be improved. Therefore, by providing the vertical transistor Tr in the pixel portion, it is possible to achieve miniaturization of the solid-state imaging device 1.

≪2. Second Embodiment >>
<Configuration of solid-state image sensor>
FIG. 8 is a cross-sectional view of a main part for one pixel of the solid-state imaging device of the second embodiment. In addition, this principal part sectional drawing is corresponded in the AA 'cross section in the top view of FIG.

  The solid-state imaging device 1 'shown in this figure is different from the solid-state imaging device of the first embodiment in the configuration of the vertical transistor Tr', and the other parts are the same.

  That is, the vertical transistor Tr ′ provided in the solid-state imaging device 1 ′ of FIG. 8 includes the p-type channel region 15 through the n-type region 50 along the inner wall of the hole 13 provided in the semiconductor substrate 3. This is different from the first embodiment.

  The n-type region 50 is composed of a semiconductor layer epitaxially grown on the inner wall of the hole 13, and is configured as an n-type region having a concentration similar to that of the semiconductor substrate 3. Such an n-type region 50 may be disposed at a distance from the surface photodiode PD1 and the floating diffusion FD, or may be disposed in a joined state. On the other hand, it is preferable that the buried photodiode PD2 is disposed in a bonded state. The p-type channel region 15 provided via the n-type region 50 is made of a semiconductor layer epitaxially grown continuously from the n-type region 50.

  The n-type region 50 and the channel region 15 epitaxially grown on the inner wall of the hole 13 as described above are octagonal columns whose inner walls are composed of (100) plane and (110) plane of single crystal silicon. However, this is the same as in the first embodiment. Further, the n-type region 50 and the channel region 15 that are epitaxially grown continuously on the inner wall of the hole 13 have facet surfaces whose upper end surfaces are inclined in the depth direction at the center of the hole 13.

  In the vertical transistor Tr ′ configured as described above, when a voltage is applied to the read gate electrode 19tg, the p-type channel region 15 is inverted to the n-type, and electrons are also collected in the n-type region 50 so that n + Become a mold. Further, the surface layer D of the n-type semiconductor substrate 3 immediately below the read gate electrode 19tg is an n + type having a high n-type concentration.

  As a result, the charges accumulated in the n + type surface photodiode PD1 are the surface layer of the n + type semiconductor substrate 3, the n type region 50 having a high n type concentration, and the channel region 15 inverted to the n type. The n-type region 50 having a high n-type concentration and the surface layer D of the n + -type semiconductor substrate 3 are read out to the floating diffusion FD. Further, the charges accumulated in the n + type embedded photodiode PD2 are the n type region 50 having a high n type concentration, the channel region 15 inverted to the n type, and the surface of the semiconductor substrate 3 having the n + type. Read out to the floating diffusion FD via layer D.

<Method for Manufacturing Solid-State Imaging Device>
Next, the manufacturing method of the solid-state image sensor of 2nd Embodiment is demonstrated. In addition, description of the process similar to 1st Embodiment is abbreviate | omitted.

  First, in the same manner as described with reference to FIGS. 3 and 4 in the first embodiment, after providing the STI 5 on the surface side of the semiconductor substrate 3, impurities are introduced into the semiconductor substrate 3, and the photodiodes PD1, PD2, The floating diffusion FD and other regions are formed. Thereafter, the process until the hole 13 is formed between the photodiodes PD1 and PD2 and the floating diffusion FD is performed. The hole 13 is formed with an opening diameter of 0.3 to 0.8 μm (as an example, 0.5 μm) and a depth of 0.6 to 1.5 μm (as an example, 1.15 m).

  Next, as shown in FIG. 9, an n-type region 50 made of a semiconductor layer is formed on the inner wall of the hole 13 that is the exposed surface of the semiconductor substrate 3 by selective epitaxial growth. At this time, n-type silicon is epitaxially grown by using a gas containing n-type impurities in the film forming gas. The n-type region 50 formed here has a thickness of about 0.05 to 0.2 μm (for example, 0.10 μm) on the side wall of the hole 13.

  Subsequently, a channel region 15 made of a semiconductor layer is formed by selective epitaxial growth. At this time, the channel region 15 is formed by epitaxially growing p-type silicon by using a gas containing p-type impurities in the film forming gas. The channel region 15 formed here is about 0.02 to 0.15 μm (as an example, 0.05 μm) on the side wall of the hole.

  Thus, for example, if the original hole 13 has an opening diameter of 0.5 μm and a depth of 1.15 μm, and the total film thickness of the n-type region 50 and the channel region 15 is 0.15 μm, the hole 13 is The opening diameter is 0.2 μm, the depth is 1.00 μm, and the aspect ratio is 5.

Such selective epitaxial growth of the n-type region is performed, for example, under the following conditions.
Growth atmosphere pressure: 50 (Torr)
Growth atmosphere temperature: 700 ° C
Growth gas and flow rate SiH ₂ Cl ₂ = 80 (sccm)
PH ₃ (PH ₃ concentration: 50 ppm / H ₂ ) = 0.1 (sccm)
HCl = 15 (sccm)
H ₂ = 20 (slm)

  The selective epitaxial growth of the channel region 15 is performed by applying the same conditions as in the first embodiment.

  In such selective epitaxial growth, flow of silicon atoms due to heat occurs. As a result, on the inner wall of the hole 13 formed in the semiconductor substrate 3 whose main surface is the (100) plane of single crystal silicon, a semiconductor layer whose surface is constituted only by the (110) plane and the (100) plane of silicon. (Channel region 15) is formed. As a result, the inner side wall constituted by the channel region 15 becomes an octagonal prism constituted by the (100) plane and the (110) plane of single crystal silicon. The channel region 15 is a facet surface whose upper end surface is inclined in the depth direction at the center of the hole 13.

  Moreover, the plasma damage of the inner wall of the hole 13 caused by the dry etching when forming the hole 13 is recovered by the flow of the silicon atoms described above.

  After the selective epitaxial growth as described above, the insulating film 41 shown only in the sectional view is removed. At this time, when the insulating film 41 is made of silicon nitride, wet etching using phosphoric acid is performed. When the insulating film 41 is made of silicon oxide, wet etching using hydrofluoric acid is performed.

  After selective epitaxial growth of the channel region 15 as described above, as shown in FIG. 8, gate electrodes 19tg and 19rg including the gate insulating film 17 and the read gate electrode 19tg are performed in the same process as in the first embodiment. , 19ag. In particular, the read gate electrode 19tg covers the n-type region 50 and the channel region 15 above the semiconductor substrate 3, and is located between the channel region 15 and the surface photodiode PD1, and between the channel region 15 and the floating diffusion diffusion FD. Patterned to cover the gap.

  Next, a low-concentration LDD region (not shown) is formed on the side of the reset gate electrode 19rg and the amplifier gate electrode 19ag, and an insulating sidewall is formed on the side wall. By this step, the side wall 21 is also formed on the side wall of the read gate electrode 19tg. After that, an n-type reset drain RD and a source AS are formed beside the reset gate electrode 19rg and the amplifier gate electrode 19ag.

  After the above, an interlayer insulating film 29 is formed above the semiconductor substrate 3 via the passivation film 27. Subsequently, a connection hole 29a is formed in the interlayer insulating film 29 and the passivation film 27, and a wiring 31 for connecting the floating diffusion FD, the n-type reset drain RD, and the source AS is formed thereon.

  After that, if necessary, an upper insulating film and an upper wiring are formed to form a multilayer wiring structure. Finally, a protective insulating film is formed on the multilayer wiring structure, and a color filter and an on-chip lens are formed thereon. Thus, the target surface irradiation type CMOS solid-state imaging device 1 ′ is obtained.

  Even in the second embodiment described above, the n-type region 50 and the p-type channel region 15 are formed by epitaxial growth on the inner wall of the hole 13 of the semiconductor substrate 3. For this reason, the n-type region 50 and the channel region 15 are formed with high accuracy with self-alignment with respect to the inner wall of the hole 13, and the characteristics of the vertical transistor Tr can be improved. Therefore, by providing the vertical transistor Tr in the pixel portion, it is possible to achieve miniaturization of the solid-state imaging device 1 ′.

≪3. Third Embodiment >>
FIG. 10 shows a configuration diagram of an electronic apparatus provided with the above-described solid-state imaging device as a third embodiment of the present invention.

  An electronic device 200 illustrated in FIG. 10 includes an imaging region 210 in which solid-state imaging elements are arrayed in the imaging unit 201. A condensing optical unit 202 that forms an image is provided on the condensing side of the image pickup unit 201, and the image pickup unit 201 has a drive circuit that drives the image pickup unit 201 and a signal photoelectrically converted in the image pickup region 210. A signal processing unit 203 having a signal processing circuit or the like for processing is connected. The image signal processed by the signal processing unit 203 can be stored by an image storage unit (not shown). In such an electronic apparatus 200, the solid-state imaging device 1 (1 ') described in the above embodiment can be arranged and formed in the imaging region 210.

  Since the electronic device 200 of the present invention uses the solid-state imaging device 1 (1 ') of the present invention, there is an advantage that an excellent image can be obtained.

  In addition, the electronic device 200 may be formed as a single chip, or may be in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. May be. The electronic device 200 here is a general device having an imaging function, such as a digital camera, a personal computer, a video camera, a television, and a portable terminal device represented by a mobile phone. “Imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  DESCRIPTION OF SYMBOLS 1,1 '... Solid-state image sensor, 3 ... Semiconductor substrate, 13 ... Hole part, 15 ... Channel area | region, 17 ... Gate insulating film, 19tg ... Read-out gate electrode, 41 ... Mask pattern, 50 ... N-type area | region (1st conductivity) Type semiconductor layer), FD ... floating diffusion (impurity region), PD ... photodiode, Tr ... vertical transistor, 200 ... electronic device

Claims (9)

A channel region composed of a semiconductor layer grown on the inner wall of the hole provided in the semiconductor substrate;
A gate insulating film covering the channel region;
A gate electrode provided in the hole through the gate insulating film;
A solid-state imaging device, comprising: a photodiode provided on the semiconductor substrate, the charge being read by turning on and off the gate electrode. The solid-state imaging device according to claim 1, wherein an inner wall of the channel region forms an octagonal prism. The semiconductor substrate has a (100) surface of single crystal silicon as a main surface,
3. The solid-state imaging device according to claim 1, wherein an inner wall of the channel region includes a (100) plane and a (110) plane of single crystal silicon. The solid-state imaging device according to claim 1, wherein an upper end surface of the channel region is inclined in a depth direction toward a center of the hole. 5. The solid-state imaging device according to claim 1, wherein the channel region of the second conductivity type is provided via a first conductivity type semiconductor layer grown on the inner wall of the hole. A channel region composed of a semiconductor layer grown on the inner wall of the hole provided in the semiconductor substrate;
A gate insulating film covering the channel region;
And a gate electrode provided in the hole through the gate insulating film. A first step of forming a hole in a semiconductor substrate;
A second step of forming a channel region comprising a semiconductor layer selectively epitaxially grown on the inner wall of the hole;
A third step of forming a gate insulating film so as to cover the channel region;
And a fourth step of forming a gate electrode in the hole through the gate insulating film. In the first step, a mask pattern is formed on the semiconductor substrate, the hole is formed by etching from the mask pattern,
The method for manufacturing a transistor according to claim 7, wherein in the second step, the semiconductor layer is selectively epitaxially grown on the inner wall of the hole exposed from the mask pattern. A channel region composed of a semiconductor layer grown on the inner wall of the hole provided in the semiconductor substrate;
A gate insulating film covering the channel region;
A gate electrode provided in the hole through the gate insulating film;
An electronic apparatus comprising a solid-state imaging device having a photodiode provided on the semiconductor substrate and from which charges are read by turning on and off the gate electrode.

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