JP2011039905A - 情報処理装置 - Google Patents

情報処理装置 Download PDF

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Publication number
JP2011039905A
JP2011039905A JP2009188221A JP2009188221A JP2011039905A JP 2011039905 A JP2011039905 A JP 2011039905A JP 2009188221 A JP2009188221 A JP 2009188221A JP 2009188221 A JP2009188221 A JP 2009188221A JP 2011039905 A JP2011039905 A JP 2011039905A
Authority
JP
Japan
Prior art keywords
bus
information processing
transfer source
control device
bus control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2009188221A
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English (en)
Japanese (ja)
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JP2011039905A5 (enExample
Inventor
Hiroyuki Murata
博幸 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2009188221A priority Critical patent/JP2011039905A/ja
Priority to PCT/JP2010/000635 priority patent/WO2011021312A1/ja
Publication of JP2011039905A publication Critical patent/JP2011039905A/ja
Priority to US13/367,960 priority patent/US20120137039A1/en
Publication of JP2011039905A5 publication Critical patent/JP2011039905A5/ja
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
JP2009188221A 2009-08-17 2009-08-17 情報処理装置 Withdrawn JP2011039905A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009188221A JP2011039905A (ja) 2009-08-17 2009-08-17 情報処理装置
PCT/JP2010/000635 WO2011021312A1 (ja) 2009-08-17 2010-02-03 情報処理装置
US13/367,960 US20120137039A1 (en) 2009-08-17 2012-02-07 Information processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009188221A JP2011039905A (ja) 2009-08-17 2009-08-17 情報処理装置

Publications (2)

Publication Number Publication Date
JP2011039905A true JP2011039905A (ja) 2011-02-24
JP2011039905A5 JP2011039905A5 (enExample) 2012-07-19

Family

ID=43606774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009188221A Withdrawn JP2011039905A (ja) 2009-08-17 2009-08-17 情報処理装置

Country Status (3)

Country Link
US (1) US20120137039A1 (enExample)
JP (1) JP2011039905A (enExample)
WO (1) WO2011021312A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102012699B1 (ko) 2013-01-25 2019-08-21 삼성전자 주식회사 다중 버스 시스템 및 이를 포함하는 반도체 시스템

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04135268A (ja) * 1990-08-03 1992-05-08 Mitsubishi Electric Corp マルチｃｐｕシステム
JPH07235772A (ja) * 1994-02-25 1995-09-05 Fujitsu Ltd 薄膜多層回路基板およびその製造方法
US5754803A (en) * 1996-06-27 1998-05-19 Interdigital Technology Corporation Parallel packetized intermodule arbitrated high speed control and data bus
US6804527B2 (en) * 2001-01-19 2004-10-12 Raze Technologies, Inc. System for coordination of TDD transmission bursts within and between cells in a wireless access system and method of operation
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US7051135B2 (en) * 2002-11-22 2006-05-23 Ess Technology, Inc. Hierarchical bus arbitration
US7254658B2 (en) * 2004-06-08 2007-08-07 Arm Limited Write transaction interleaving
US7350002B2 (en) * 2004-12-09 2008-03-25 Agere Systems, Inc. Round-robin bus protocol
JP2007241918A (ja) * 2006-03-13 2007-09-20 Fujitsu Ltd プロセッサ装置
KR20080074545A (ko) * 2007-02-09 2008-08-13 삼성전자주식회사 버스 시스템 및 그 제어 방법
JP2009003633A (ja) * 2007-06-20 2009-01-08 Panasonic Corp 情報処理装置
US7886096B2 (en) * 2008-08-08 2011-02-08 Texas Instruments Incorporated Throughput measurement of a total number of data bits communicated during a communication period

Also Published As

Publication number Publication date
US20120137039A1 (en) 2012-05-31
WO2011021312A1 (ja) 2011-02-24

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