WO2011021312A1 - 情報処理装置 - Google Patents

情報処理装置 Download PDF

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Publication number
WO2011021312A1
WO2011021312A1 PCT/JP2010/000635 JP2010000635W WO2011021312A1 WO 2011021312 A1 WO2011021312 A1 WO 2011021312A1 JP 2010000635 W JP2010000635 W JP 2010000635W WO 2011021312 A1 WO2011021312 A1 WO 2011021312A1
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WO
WIPO (PCT)
Prior art keywords
bus
information processing
transfer source
control device
bus control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2010/000635
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English (en)
French (fr)
Japanese (ja)
Inventor
村田博幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
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Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of WO2011021312A1 publication Critical patent/WO2011021312A1/ja
Priority to US13/367,960 priority Critical patent/US20120137039A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Definitions

  • the present invention relates to an information processing apparatus, and more particularly to a technique for reducing bus traffic of an on-chip bus.
  • the time-sharing control mechanism is mounted on the on-chip bus, or a buffer is provided in the on-chip bus, thereby reducing bus traffic in the entire on-chip bus.
  • Data based on a conventional on-chip bus configuration is stored in an on-chip memory or SDRAM (Synchronous Dynamic Random Access Memory) depending on access frequency and data attributes.
  • SDRAM Serial Dynamic Random Access Memory
  • the present invention has been made in view of this point, and an object thereof is to reduce the number of accesses to the memory on the on-chip bus.
  • the present invention has taken the following measures. That is, as an information processing device for transmitting and receiving data via a hierarchical bus between a plurality of transfer source bus control devices and a plurality of transfer destination bus control devices, an information holding circuit installed for each of the plurality of transfer source bus control devices, A dedicated bus that can connect multiple information holding circuits to each other, and a bus selection that is installed for each transfer source bus controller and selects either a dedicated bus or a hierarchical bus as the connection destination of each transfer source bus controller And a circuit.
  • the other transfer source bus control device becomes the transfer destination bus control device. No need to access As a result, the number of accesses to the transfer destination bus control device can be reduced in the entire information processing apparatus.
  • the number of accesses to the transfer destination bus control device can be reduced in the entire information processing apparatus. Therefore, it is possible to improve the efficiency of continuous information processing between the transfer source bus control devices, improve the transfer efficiency of the on-chip bus, and reduce the area of the on-chip bus.
  • FIG. 1 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the first embodiment.
  • FIG. 2 shows a control information format issued by the transfer source bus control device according to the first embodiment.
  • FIG. 3 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the second embodiment.
  • FIG. 4 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the third embodiment.
  • FIG. 5 shows an address management directory information format according to the third embodiment.
  • FIG. 6 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the fourth embodiment.
  • FIG. 7 shows an external access address monitor information format according to the fourth embodiment.
  • FIG. 8 is a block diagram illustrating a schematic configuration of an information processing apparatus according to the fifth embodiment.
  • FIG. 9 is a block diagram illustrating a schematic configuration of an information processing system according to the sixth embodiment.
  • FIG. 10 shows a control information format issued by the transfer source cluster control apparatus according to the sixth embodiment.
  • FIG. 11 is a block diagram showing a cluster configuration according to the sixth embodiment.
  • FIG. 1 is a block diagram illustrating a schematic configuration of an information processing apparatus 100 according to the first embodiment.
  • FIG. 2 shows a control information format issued from the transfer source bus control devices 1 to 3.
  • the information processing apparatus 100 transmits and receives data between the plurality of transfer source bus control apparatuses 1 to 3 and the plurality of transfer destination bus control apparatuses 4 to 6.
  • the information processing apparatus 100 includes an information holding circuit 7 to 9 installed for each of a plurality of transfer source bus control devices 1 to 3, a ring bus 10 that can connect the information holding circuits 7 to 9 to each other, and a plurality of transfer sources.
  • a hierarchical bus 11 that can connect the bus control devices 1 to 3 and a plurality of transfer destination bus control devices 4 to 6, and either the ring bus 10 or the hierarchical bus 11 is output by an output signal of the transfer source bus control devices 1 to 3.
  • Bus selection circuits 12 to 14 to be selected.
  • the operation of the information processing apparatus 100 configured as described above will be described below. First, it is assumed that information processing is continuously performed from the transfer source bus control device 1 to the transfer source bus control device 2 and then to the transfer source bus control device 3.
  • the transfer source bus control device 1 sets the transfer destination bus control device 4 in the address information of the control information and outputs it. Thereby, the bus selection circuit 12 selects connection to the hierarchical bus 11.
  • the transfer source bus control device 1 acquires data from the transfer destination bus control device 4 and performs information processing.
  • the address information of the control destination information is the address of the transfer destination bus control device 5
  • the first information processing destination is the address of the transfer source bus control device 2
  • the second information processing destination is the address of the transfer source bus control device 3.
  • processing completion data is set in the transfer information, and transfer to the transfer destination bus control device 5 is started.
  • the bus selection circuit 12 selects connection to the hierarchical bus in order to start data transfer from the transfer source bus control device 1 to the transfer destination bus control device 5, but the first information Since the addresses are set for the processing destination and the second information processing destination, the bus selection circuit 12 preferentially selects the connection to the ring bus 10, and the transfer source bus control device 1 performs the transfer that is the first information processing destination. Data transfer is performed to the information holding circuit 8 of the original bus control device 2.
  • the bus selection circuits 13 and 14 preferentially select the ring bus 10 when data continuously processed by the transfer source bus control devices 1 to 3 exists on the ring bus 10.
  • the bus selection circuit 13 receives data from the ring bus 10 and stores it in the information holding circuit 8 when there is no data output request from the transfer source bus control device 2.
  • the transfer source bus control device 2 can acquire data without accessing the transfer destination bus control device 5 because the data holding circuit 8 has data necessary for processing. Upon completion of the information processing, the transfer source bus control device 2 sets the address of the transfer destination bus control device 6 in the address information of the control information and the information processing completion data in the transfer information, and sets the second information processing destination of the control information to the first information processing destination. Transfer to one information processing destination and start transfer to the transfer destination bus control device 6. However, since the transfer source bus control device 2 sets the address of the transfer source bus control device 3 as the first information processing destination, the transfer source bus control device 2 transfers the data to the information holding circuit 9 of the transfer source bus control device 3 that is the first information processing destination. carry out.
  • the bus selection circuit 14 receives data from the ring bus 10 and stores it in the information holding circuit 9 when there is no data output request from the transfer source bus control device 3. Since the transfer source bus control device 3 has the data necessary for processing in the information holding circuit 9, it can acquire the data without accessing the transfer destination bus control device 6.
  • FIG. 3 is a block diagram illustrating a schematic configuration of the information processing apparatus 101 according to the second embodiment.
  • the information processing apparatus 101 uses the control information format of FIG. 2 as in the first embodiment. Only the differences from the first embodiment will be described below.
  • the information processing apparatus 101 includes notification buses 18 to 20 that notify the corresponding transfer source bus control apparatuses 1 to 3 that data exists in the information holding circuits 7 to 9.
  • the transfer source bus control device 1 When the information processing is completed in the transfer source bus control device 1, data transfer is performed to the information holding circuit 8 of the transfer source bus control device 2 which is the first information processing destination. As soon as the data transfer to the information holding circuit 8 is completed, the transfer source bus control device 2 is notified via the notification bus 19 that data exists in the information holding circuit 8. Since the transfer source bus control device 2 has data necessary for processing in the information holding circuit 8, it can acquire data without accessing the transfer destination bus control device 5.
  • the transfer source bus control device 2 completes the information processing
  • the second information processing destination of the control information is moved up to the first information processing destination, and the data is transferred to the information holding circuit 9 of the transfer source bus control device 3.
  • the transfer source bus control device 3 is notified via the notification bus 20 that the data exists in the information holding circuit 9. Since the transfer source bus control device 3 has the data necessary for processing in the information holding circuit 9, it can acquire the data without accessing the transfer destination bus control device 6.
  • FIG. 4 is a block diagram illustrating a schematic configuration of the information processing apparatus 102 according to the third embodiment.
  • the information processing apparatus 102 uses the control information format shown in FIGS.
  • FIGS. Hereinafter, only differences from the second embodiment will be described.
  • the information processing apparatus 102 includes an address management directory 21 that monitors data passing between the transfer source bus control apparatuses 1 to 3 and the bus selection circuits 12 to 14.
  • the transfer source bus control device 3 acquires data from the transfer destination bus control device 4 and the transfer source bus control device 1 acquires data from the transfer destination bus control device 4.
  • the transfer source bus control device 3 acquires data from the transfer destination bus control device 4 into the information holding circuit 9 via the hierarchical bus 11.
  • the address management directory 21 manages information that the data is acquired from the transfer destination bus control device 4 in the information holding circuit 9 according to the control information format of FIG. Subsequently, when the transfer source bus control device 1 acquires data from the transfer destination bus control device 4, the address management directory 21 detects that the data requested by the transfer source bus control device 1 is in the information holding circuit 9. The address management directory 21 changes the access destination of the transfer source bus control device 1 from the transfer destination bus control device 4 to the information holding circuit 9, so that the first information processing destination is the information holding circuit according to the control information format of FIG. Change to 9. As a result, the bus selection circuit 12 and the bus selection circuit 14 select the connection to the ring bus 10, and the transfer source bus control device 1 receives data from the information holding circuit 9 of the transfer source bus control device 3 that is the first information processing destination. To get.
  • FIG. 6 is a block diagram illustrating a schematic configuration of the information processing apparatus 103 according to the fourth embodiment.
  • the information processing apparatus 103 uses the control information format shown in FIGS.
  • FIGS. Hereinafter, only differences from the second embodiment will be described.
  • the information processing apparatus 103 includes an external access address monitor 22 that monitors access destination information of the transfer source bus control apparatuses 1 to 3.
  • the bus selection circuits 27 to 29 select either the ring bus 10 or the hierarchical bus 11 based on the output signals of the transfer source bus control devices 1 to 3 and the selection circuit control signals 24 to 26 that are the output signals of the external access address monitor 22. To do.
  • the external access address monitor 22 displays information that the transfer source bus control device 3 is acquiring data from the transfer destination bus control device 4 in FIG. Register according to the control information format. Subsequently, when the transfer source bus control device 1 and the transfer source bus control device 2 acquire data from the transfer destination bus control device 4, the external access address monitor 22 detects that the transfer source bus control device 3 is acquiring data. Then, the access to the transfer destination bus control device 4 of the transfer source bus control device 1 and the transfer source bus control device 2 is set in a standby state.
  • External access address monitor 22 outputs selection circuit control signals 24-26.
  • the bus selection circuit 27 selects connection to the ring bus 10
  • the bus selection circuit 28 selects connection to the ring bus 10
  • the bus selection circuit 29 selects connection to the hierarchical bus 11.
  • the transfer source bus control device 3 acquires data from the transfer destination bus control device 4 and completes the information processing.
  • the bus selection circuit 29 selects connection to the ring bus 10 according to the output signal of the transfer source bus control device 3.
  • the transfer source bus control device 1 and the transfer source bus control device 2 acquire data from the information holding circuit 9 of the transfer source bus control device 3 via the ring bus 10.
  • the transfer source bus control device 1 and the transfer source bus control device 2 may directly acquire data from the ring bus 10.
  • the transfer source bus control device 3 is acquiring data from the transfer destination bus control device 4, and the transfer destination bus control of the transfer source bus control device 1 and the transfer source bus control device 2 is performed. It is assumed that access to the device 4 is registered as being in a standby state.
  • the bus selection circuit 27 when receiving the selection circuit control signal 24, the bus selection circuit 27 connects an input port for receiving data from the ring bus 10 and an input / output port for transmitting / receiving control information to / from the external access address monitor 22.
  • the bus selection circuit 28 connects an input port from the ring bus 10 and an input / output port with the external access address monitor 22.
  • the bus selection circuit 29 Upon receiving the selection circuit control signal 26, the bus selection circuit 29 outputs data to the input port for receiving data from the hierarchical bus 11 and the ring bus 10 in accordance with the control information registered in the external access address monitor 22. Are connected to the external access address monitor 22 and an input / output port for transmitting and receiving control information.
  • FIG. 8 is a block diagram illustrating a schematic configuration of the information processing apparatus 104 according to the fifth embodiment.
  • the information processing apparatus 104 uses the control information format shown in FIGS.
  • the information processing apparatus 104 uses the second embodiment, the third embodiment, and the fourth embodiment together. For example, when the transfer source bus control devices 1 to 3 transfer data based on the control information managed in the address management directory 21, the ring bus 10 is used. On the other hand, when transferring data based on the control information registered in the external access address monitor 22, the ring bus 10A is used. By performing the combined use of information processing, it is possible to implement without reducing the effect obtained in each embodiment, so that the on-chip bus transfer efficiency and SoC system performance are improved, and the power consumption of the on-chip bus is reduced. be able to. There may be one ring bus.
  • FIG. 9 is a block diagram illustrating a schematic configuration of an information processing system 105 according to the sixth embodiment.
  • the information processing system 105 uses the control information format shown in FIG.
  • the information processing apparatus 104 in FIG. 8 is used as the transfer source cluster control apparatus 33 shown in FIG.
  • a plurality of transfer source cluster control devices 33 to 35 and a plurality of transfer destination bus control devices 4A to 6A transmit and receive data via the hierarchical bus 11A.
  • the information processing system 105 includes a cluster information holding circuit 36 installed for each transfer source cluster control device 33 to 35, a ring bus 10A capable of connecting a plurality of cluster information holding circuits 36, and a transfer source cluster control device 33.
  • Bus selection circuits 12A to 14A for selecting either the ring bus 10B or the hierarchical bus 11A according to the output signals of .about.35.
  • a mesh bus may be used instead of the ring buses 10, 10A, 10B.
  • the information processing apparatus can reduce the number of accesses to a memory, a peripheral device, and the like, and thus is useful for personal computers and the like that are required to improve on-chip bus transfer efficiency and SoC system performance and to reduce power consumption It is.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
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PCT/JP2010/000635 2009-08-17 2010-02-03 情報処理装置 Ceased WO2011021312A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/367,960 US20120137039A1 (en) 2009-08-17 2012-02-07 Information processing apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009188221A JP2011039905A (ja) 2009-08-17 2009-08-17 情報処理装置
JP2009-188221 2009-08-17

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/367,960 Continuation US20120137039A1 (en) 2009-08-17 2012-02-07 Information processing apparatus

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KR102012699B1 (ko) 2013-01-25 2019-08-21 삼성전자 주식회사 다중 버스 시스템 및 이를 포함하는 반도체 시스템

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPH04135268A (ja) * 1990-08-03 1992-05-08 Mitsubishi Electric Corp マルチｃｐｕシステム
JPH11513158A (ja) * 1996-06-27 1999-11-09 インターデジタル・テクノロジー・コーポレーション 並列パケット化されたモジュール間調停高速制御およびデータバス
JP2009003633A (ja) * 2007-06-20 2009-01-08 Panasonic Corp 情報処理装置

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JPH07235772A (ja) * 1994-02-25 1995-09-05 Fujitsu Ltd 薄膜多層回路基板およびその製造方法
US6804527B2 (en) * 2001-01-19 2004-10-12 Raze Technologies, Inc. System for coordination of TDD transmission bursts within and between cells in a wireless access system and method of operation
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US7051135B2 (en) * 2002-11-22 2006-05-23 Ess Technology, Inc. Hierarchical bus arbitration
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US7350002B2 (en) * 2004-12-09 2008-03-25 Agere Systems, Inc. Round-robin bus protocol
JP2007241918A (ja) * 2006-03-13 2007-09-20 Fujitsu Ltd プロセッサ装置
KR20080074545A (ko) * 2007-02-09 2008-08-13 삼성전자주식회사 버스 시스템 및 그 제어 방법
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04135268A (ja) * 1990-08-03 1992-05-08 Mitsubishi Electric Corp マルチｃｐｕシステム
JPH11513158A (ja) * 1996-06-27 1999-11-09 インターデジタル・テクノロジー・コーポレーション 並列パケット化されたモジュール間調停高速制御およびデータバス
JP2009003633A (ja) * 2007-06-20 2009-01-08 Panasonic Corp 情報処理装置

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US20120137039A1 (en) 2012-05-31

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