JP2010534374A5 - - Google Patents
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- JP2010534374A5 JP2010534374A5 JP2010518222A JP2010518222A JP2010534374A5 JP 2010534374 A5 JP2010534374 A5 JP 2010534374A5 JP 2010518222 A JP2010518222 A JP 2010518222A JP 2010518222 A JP2010518222 A JP 2010518222A JP 2010534374 A5 JP2010534374 A5 JP 2010534374A5
- Authority
- JP
- Japan
- Prior art keywords
- processing system
- decomposition
- data processing
- level circuit
- transformation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US95143607P | 2007-07-23 | 2007-07-23 | |
| US60/951,436 | 2007-07-23 | ||
| US12/177,867 US8819608B2 (en) | 2007-07-23 | 2008-07-22 | Architectural physical synthesis |
| US12/177,867 | 2008-07-22 | ||
| PCT/US2008/008998 WO2009014731A2 (en) | 2007-07-23 | 2008-07-23 | Architectural physical synthesis |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010534374A JP2010534374A (ja) | 2010-11-04 |
| JP2010534374A5 true JP2010534374A5 (enExample) | 2012-11-29 |
| JP5706689B2 JP5706689B2 (ja) | 2015-04-22 |
Family
ID=40139171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010518222A Active JP5706689B2 (ja) | 2007-07-23 | 2008-07-23 | アーキテクチャー上の物理的合成 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US8819608B2 (enExample) |
| EP (1) | EP2171623A2 (enExample) |
| JP (1) | JP5706689B2 (enExample) |
| CN (1) | CN101821737A (enExample) |
| WO (1) | WO2009014731A2 (enExample) |
Families Citing this family (50)
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| US8595674B2 (en) * | 2007-07-23 | 2013-11-26 | Synopsys, Inc. | Architectural physical synthesis |
| JP5239597B2 (ja) * | 2008-07-31 | 2013-07-17 | ソニー株式会社 | データ処理装置およびその方法、並びにプログラム |
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| US9576092B2 (en) * | 2009-02-24 | 2017-02-21 | Mentor Graphics Corporation | Synthesis using multiple synthesis engine configurations |
| US8656332B2 (en) * | 2009-02-26 | 2014-02-18 | International Business Machines Corporation | Automated critical area allocation in a physical synthesized hierarchical design |
| US8255847B1 (en) * | 2009-10-01 | 2012-08-28 | Altera Corporation | Method and apparatus for automatic hierarchical design partitioning |
| US10185594B2 (en) * | 2009-10-29 | 2019-01-22 | International Business Machines Corporation | System and method for resource identification |
| US8261220B2 (en) * | 2009-11-30 | 2012-09-04 | Synopsys, Inc. | Path preserving design partitioning with redundancy |
| US8276107B2 (en) * | 2010-10-18 | 2012-09-25 | Algotochip Corporation | Integrated data model based framework for driving design convergence from architecture optimization to physical design closure |
| US8336017B2 (en) * | 2011-01-19 | 2012-12-18 | Algotochip Corporation | Architecture optimizer |
| US9381013B2 (en) * | 2011-11-10 | 2016-07-05 | Biomet Sports Medicine, Llc | Method for coupling soft tissue to a bone |
| US9524363B2 (en) * | 2012-05-31 | 2016-12-20 | Globalfoundries Inc. | Element placement in circuit design based on preferred location |
| CN102768506B (zh) * | 2012-07-18 | 2015-01-07 | 复旦大学 | 带时序约束的fpga时序驱动布局方法 |
| US9836567B2 (en) | 2012-09-14 | 2017-12-05 | Nxp Usa, Inc. | Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit |
| US8914759B2 (en) * | 2012-12-31 | 2014-12-16 | Synopsys, Inc. | Abstract creation |
| US9087168B2 (en) * | 2013-06-19 | 2015-07-21 | International Business Machines Corporation | Optimizing operating range of an electronic circuit |
| CN104376138B (zh) * | 2013-08-15 | 2017-11-21 | 龙芯中科技术有限公司 | 集成电路芯片的时序确定方法和装置 |
| US20150178436A1 (en) * | 2013-12-20 | 2015-06-25 | Lattice Semiconductor Corporation | Clock assignments for programmable logic device |
| US10783292B1 (en) | 2015-05-21 | 2020-09-22 | Pulsic Limited | Automated analog layout |
| CN105005638B (zh) * | 2015-06-04 | 2018-06-26 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | 一种基于线性延时模型的高层次综合调度方法 |
| US9613173B1 (en) * | 2015-10-01 | 2017-04-04 | Xilinx, Inc. | Interactive multi-step physical synthesis |
| US9852254B2 (en) * | 2015-11-10 | 2017-12-26 | Arteris, Inc. | Automatic architecture placement guidance |
| US9852259B2 (en) | 2016-01-21 | 2017-12-26 | Globalfoundries Inc. | Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks |
| US9495501B1 (en) | 2016-01-29 | 2016-11-15 | International Business Machines Corporation | Large cluster persistence during placement optimization of integrated circuit designs |
| US10120970B2 (en) | 2016-06-14 | 2018-11-06 | International Business Machines Corporation | Global routing framework of integrated circuit based on localized routing optimization |
| US10586005B1 (en) | 2018-03-21 | 2020-03-10 | Xilinx, Inc. | Incremental synthesis for changes to a circuit design |
| CN109670268B (zh) * | 2018-12-29 | 2022-11-25 | 京微齐力(北京)科技有限公司 | 一种多个ip与efpga端口连接方法 |
| KR20220017993A (ko) | 2019-06-10 | 2022-02-14 | 바텔리 메모리얼 인스티튜트 | 플랫 넷리스트로부터 동작 디자인 복구 |
| CN110765710B (zh) * | 2019-10-22 | 2021-11-30 | 清华大学 | 基于非易失器件的通用逻辑综合方法及装置 |
| CN111027267B (zh) * | 2019-11-13 | 2021-01-19 | 广东高云半导体科技股份有限公司 | Fpga逻辑综合中加法器优化的实现方法及装置、系统 |
| CN111143274B (zh) * | 2019-11-13 | 2022-07-12 | 广东高云半导体科技股份有限公司 | 以逻辑综合结果为导向的层级结构优化方法及装置、系统 |
| US10891413B1 (en) * | 2019-12-05 | 2021-01-12 | Xilinx, Inc. | Incremental initialization by parent and child placer processes in processing a circuit design |
| US11657203B2 (en) | 2019-12-27 | 2023-05-23 | Arteris, Inc. | Multi-phase topology synthesis of a network-on-chip (NoC) |
| US10990724B1 (en) | 2019-12-27 | 2021-04-27 | Arteris, Inc. | System and method for incremental topology synthesis of a network-on-chip |
| US11665776B2 (en) | 2019-12-27 | 2023-05-30 | Arteris, Inc. | System and method for synthesis of a network-on-chip for deadlock-free transformation |
| US11558259B2 (en) | 2019-12-27 | 2023-01-17 | Arteris, Inc. | System and method for generating and using physical roadmaps in network synthesis |
| CN111198523A (zh) * | 2019-12-27 | 2020-05-26 | 广东高云半导体科技股份有限公司 | 基于结果导向的逻辑推理控制方法及装置、系统 |
| US11121933B2 (en) | 2019-12-27 | 2021-09-14 | Arteris, Inc. | Physically aware topology synthesis of a network |
| US11418448B2 (en) | 2020-04-09 | 2022-08-16 | Arteris, Inc. | System and method for synthesis of a network-on-chip to determine optimal path with load balancing |
| CN113642280B (zh) * | 2020-04-27 | 2024-06-14 | 中国科学院上海微系统与信息技术研究所 | 超导集成电路的布局方法 |
| CN112270148A (zh) * | 2020-10-16 | 2021-01-26 | 山东云海国创云计算装备产业创新中心有限公司 | 一种门级网表生成方法及相关装置 |
| US11601357B2 (en) | 2020-12-22 | 2023-03-07 | Arteris, Inc. | System and method for generation of quality metrics for optimization tasks in topology synthesis of a network |
| US11281827B1 (en) | 2020-12-26 | 2022-03-22 | Arteris, Inc. | Optimization of parameters for synthesis of a topology using a discriminant function module |
| US11449655B2 (en) | 2020-12-30 | 2022-09-20 | Arteris, Inc. | Synthesis of a network-on-chip (NoC) using performance constraints and objectives |
| US12289384B2 (en) | 2021-02-12 | 2025-04-29 | Arteris, Inc. | System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC) |
| US11956127B2 (en) | 2021-03-10 | 2024-04-09 | Arteris, Inc. | Incremental topology modification of a network-on-chip |
| US12184499B2 (en) | 2021-09-29 | 2024-12-31 | Arteris, Inc. | System and method for editing a network-on-chip (NOC) |
| US12438829B2 (en) | 2021-09-29 | 2025-10-07 | Arteris, Inc. | System and method for deadlock detection in network-on-chip (NoC) having external dependencies |
| US12067335B2 (en) | 2022-04-11 | 2024-08-20 | Arteris, Inc. | Automatic configuration of pipeline modules in an electronics system |
| CN115952759B (zh) * | 2023-02-20 | 2025-10-24 | 京微齐力(北京)科技股份有限公司 | Fpga布局方法、装置、电子设备和存储介质 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01142922A (ja) | 1987-11-30 | 1989-06-05 | Omron Tateisi Electron Co | プリンタ用アダプタ |
| JPH0659686B2 (ja) | 1990-10-29 | 1994-08-10 | ダイアホイルヘキスト株式会社 | コンデンサー用二軸配向ポリエステルフィルム |
| JPH05342290A (ja) | 1992-06-08 | 1993-12-24 | Nec Corp | 要素配置方法および装置 |
| JPH06266801A (ja) | 1993-03-15 | 1994-09-22 | Nec Corp | フロアプランを考慮した論理合成方法 |
| JP3424997B2 (ja) | 1995-01-31 | 2003-07-07 | 富士通株式会社 | 回路設計装置 |
| US5712793A (en) | 1995-11-20 | 1998-01-27 | Lsi Logic Corporation | Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization |
| JP2954894B2 (ja) | 1996-12-13 | 1999-09-27 | 株式会社半導体理工学研究センター | 集積回路設計方法、集積回路設計のためのデータベース装置および集積回路設計支援装置 |
| JPH1185819A (ja) | 1997-09-02 | 1999-03-30 | Matsushita Electric Ind Co Ltd | 部品配置装置 |
| US6249902B1 (en) | 1998-01-09 | 2001-06-19 | Silicon Perspective Corporation | Design hierarchy-based placement |
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| US6519754B1 (en) | 1999-05-17 | 2003-02-11 | Synplicity, Inc. | Methods and apparatuses for designing integrated circuits |
| JP2001142922A (ja) | 1999-11-15 | 2001-05-25 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置の設計方法 |
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| US7047163B1 (en) * | 2000-03-13 | 2006-05-16 | International Business Machines Corporation | Method and apparatus for applying fine-grained transforms during placement synthesis interaction |
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| JP2002123563A (ja) * | 2000-10-13 | 2002-04-26 | Nec Corp | コンパイル方法および合成装置ならびに記録媒体 |
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| CN1539114A (zh) | 2001-06-08 | 2004-10-20 | �������Զ�������ƹ�˾ | 用于在分层集成电路设计系统中产生模块的设计约束的方法 |
| CN1656486A (zh) | 2002-05-23 | 2005-08-17 | 皇家飞利浦电子股份有限公司 | 集成电路设计方法 |
| US7827510B1 (en) * | 2002-06-07 | 2010-11-02 | Synopsys, Inc. | Enhanced hardware debugging with embedded FPGAS in a hardware description language |
| US6925628B2 (en) | 2002-10-22 | 2005-08-02 | Matsushita Electric Industrial Co., Ltd. | High-level synthesis method |
| JP2004164627A (ja) | 2002-10-22 | 2004-06-10 | Matsushita Electric Ind Co Ltd | 高位合成方法 |
| JP3811133B2 (ja) * | 2003-03-03 | 2006-08-16 | 三菱電機株式会社 | 半導体集積回路設計方法および設計支援装置 |
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| CN100347710C (zh) | 2005-05-13 | 2007-11-07 | 清华大学 | 多端线网插入缓冲器优化时延的标准单元总体布线方法 |
| WO2007002799A1 (en) | 2005-06-29 | 2007-01-04 | Lightspeed Logic, Inc. | Methods and systems for placement |
| GB0516634D0 (en) | 2005-08-12 | 2005-09-21 | Univ Sussex | Electronic circuit design |
| CN100362520C (zh) | 2005-09-09 | 2008-01-16 | 深圳市海思半导体有限公司 | 一种专用集成电路综合系统及方法 |
| US7451416B2 (en) | 2006-03-17 | 2008-11-11 | International Business Machines Corporation | Method and system for designing an electronic circuit |
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| US8595674B2 (en) | 2007-07-23 | 2013-11-26 | Synopsys, Inc. | Architectural physical synthesis |
-
2008
- 2008-07-22 US US12/177,867 patent/US8819608B2/en active Active
- 2008-07-23 JP JP2010518222A patent/JP5706689B2/ja active Active
- 2008-07-23 CN CN200880100011A patent/CN101821737A/zh active Pending
- 2008-07-23 EP EP08794712A patent/EP2171623A2/en not_active Withdrawn
- 2008-07-23 WO PCT/US2008/008998 patent/WO2009014731A2/en not_active Ceased
-
2013
- 2013-10-25 US US14/064,067 patent/US8966415B2/en active Active
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