CN101821737A - 构架物理综合 - Google Patents

构架物理综合 Download PDF

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Publication number
CN101821737A
CN101821737A CN200880100011A CN200880100011A CN101821737A CN 101821737 A CN101821737 A CN 101821737A CN 200880100011 A CN200880100011 A CN 200880100011A CN 200880100011 A CN200880100011 A CN 200880100011A CN 101821737 A CN101821737 A CN 101821737A
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layout
design
resource
integrated circuit
medium
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Chinese (zh)
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K·S·麦克尔文
B·勒莫尼耶
B·哈尔平
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Synopsys Inc
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Synopsys Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN200880100011A 2007-07-23 2008-07-23 构架物理综合 Pending CN101821737A (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US95143607P 2007-07-23 2007-07-23
US60/951,436 2007-07-23
US12/177,867 US8819608B2 (en) 2007-07-23 2008-07-22 Architectural physical synthesis
US12/177,867 2008-07-22
PCT/US2008/008998 WO2009014731A2 (en) 2007-07-23 2008-07-23 Architectural physical synthesis

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CN101821737A true CN101821737A (zh) 2010-09-01

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CN200880100011A Pending CN101821737A (zh) 2007-07-23 2008-07-23 构架物理综合

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US (2) US8819608B2 (enExample)
EP (1) EP2171623A2 (enExample)
JP (1) JP5706689B2 (enExample)
CN (1) CN101821737A (enExample)
WO (1) WO2009014731A2 (enExample)

Cited By (12)

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CN102768506A (zh) * 2012-07-18 2012-11-07 复旦大学 带时序约束的fpga时序驱动布局方法
CN103262081A (zh) * 2010-10-18 2013-08-21 艾尔葛托奇普股份有限公司 用于驱动从架构优化到物理设计闭合的设计收敛的基于集成数据模型的框架
CN103329132A (zh) * 2011-01-19 2013-09-25 艾尔葛托奇普股份有限公司 架构优化器
CN104376138A (zh) * 2013-08-15 2015-02-25 龙芯中科技术有限公司 集成电路芯片的时序确定方法和装置
CN109670268A (zh) * 2018-12-29 2019-04-23 京微齐力(北京)科技有限公司 一种多个ip与efpga端口连接方法
CN110765710A (zh) * 2019-10-22 2020-02-07 清华大学 基于非易失器件的通用逻辑综合方法及装置
CN111027267A (zh) * 2019-11-13 2020-04-17 广东高云半导体科技股份有限公司 Fpga逻辑综合中加法器优化的实现方法及装置、系统
CN111143274A (zh) * 2019-11-13 2020-05-12 广东高云半导体科技股份有限公司 以逻辑综合结果为导向的层级结构优化方法及装置、系统
CN111198523A (zh) * 2019-12-27 2020-05-26 广东高云半导体科技股份有限公司 基于结果导向的逻辑推理控制方法及装置、系统
CN112270148A (zh) * 2020-10-16 2021-01-26 山东云海国创云计算装备产业创新中心有限公司 一种门级网表生成方法及相关装置
CN113642280A (zh) * 2020-04-27 2021-11-12 中国科学院上海微系统与信息技术研究所 超导集成电路的布局方法
CN115952759A (zh) * 2023-02-20 2023-04-11 京微齐力(北京)科技股份有限公司 Fpga布局方法、装置、电子设备和存储介质

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US10891413B1 (en) * 2019-12-05 2021-01-12 Xilinx, Inc. Incremental initialization by parent and child placer processes in processing a circuit design
US11657203B2 (en) 2019-12-27 2023-05-23 Arteris, Inc. Multi-phase topology synthesis of a network-on-chip (NoC)
US11558259B2 (en) 2019-12-27 2023-01-17 Arteris, Inc. System and method for generating and using physical roadmaps in network synthesis
US11665776B2 (en) 2019-12-27 2023-05-30 Arteris, Inc. System and method for synthesis of a network-on-chip for deadlock-free transformation
US11121933B2 (en) 2019-12-27 2021-09-14 Arteris, Inc. Physically aware topology synthesis of a network
US10990724B1 (en) 2019-12-27 2021-04-27 Arteris, Inc. System and method for incremental topology synthesis of a network-on-chip
US11418448B2 (en) 2020-04-09 2022-08-16 Arteris, Inc. System and method for synthesis of a network-on-chip to determine optimal path with load balancing
US11601357B2 (en) 2020-12-22 2023-03-07 Arteris, Inc. System and method for generation of quality metrics for optimization tasks in topology synthesis of a network
US11281827B1 (en) 2020-12-26 2022-03-22 Arteris, Inc. Optimization of parameters for synthesis of a topology using a discriminant function module
US11449655B2 (en) 2020-12-30 2022-09-20 Arteris, Inc. Synthesis of a network-on-chip (NoC) using performance constraints and objectives
US12289384B2 (en) 2021-02-12 2025-04-29 Arteris, Inc. System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)
US11956127B2 (en) 2021-03-10 2024-04-09 Arteris, Inc. Incremental topology modification of a network-on-chip
US12184499B2 (en) 2021-09-29 2024-12-31 Arteris, Inc. System and method for editing a network-on-chip (NOC)
US12438829B2 (en) 2021-09-29 2025-10-07 Arteris, Inc. System and method for deadlock detection in network-on-chip (NoC) having external dependencies
US12067335B2 (en) 2022-04-11 2024-08-20 Arteris, Inc. Automatic configuration of pipeline modules in an electronics system

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103262081A (zh) * 2010-10-18 2013-08-21 艾尔葛托奇普股份有限公司 用于驱动从架构优化到物理设计闭合的设计收敛的基于集成数据模型的框架
CN103329132A (zh) * 2011-01-19 2013-09-25 艾尔葛托奇普股份有限公司 架构优化器
CN102768506B (zh) * 2012-07-18 2015-01-07 复旦大学 带时序约束的fpga时序驱动布局方法
CN102768506A (zh) * 2012-07-18 2012-11-07 复旦大学 带时序约束的fpga时序驱动布局方法
CN104376138A (zh) * 2013-08-15 2015-02-25 龙芯中科技术有限公司 集成电路芯片的时序确定方法和装置
CN104376138B (zh) * 2013-08-15 2017-11-21 龙芯中科技术有限公司 集成电路芯片的时序确定方法和装置
CN109670268A (zh) * 2018-12-29 2019-04-23 京微齐力(北京)科技有限公司 一种多个ip与efpga端口连接方法
CN109670268B (zh) * 2018-12-29 2022-11-25 京微齐力(北京)科技有限公司 一种多个ip与efpga端口连接方法
CN110765710B (zh) * 2019-10-22 2021-11-30 清华大学 基于非易失器件的通用逻辑综合方法及装置
CN110765710A (zh) * 2019-10-22 2020-02-07 清华大学 基于非易失器件的通用逻辑综合方法及装置
CN111027267A (zh) * 2019-11-13 2020-04-17 广东高云半导体科技股份有限公司 Fpga逻辑综合中加法器优化的实现方法及装置、系统
CN111143274A (zh) * 2019-11-13 2020-05-12 广东高云半导体科技股份有限公司 以逻辑综合结果为导向的层级结构优化方法及装置、系统
CN111198523A (zh) * 2019-12-27 2020-05-26 广东高云半导体科技股份有限公司 基于结果导向的逻辑推理控制方法及装置、系统
CN113642280A (zh) * 2020-04-27 2021-11-12 中国科学院上海微系统与信息技术研究所 超导集成电路的布局方法
CN112270148A (zh) * 2020-10-16 2021-01-26 山东云海国创云计算装备产业创新中心有限公司 一种门级网表生成方法及相关装置
CN115952759A (zh) * 2023-02-20 2023-04-11 京微齐力(北京)科技股份有限公司 Fpga布局方法、装置、电子设备和存储介质
CN115952759B (zh) * 2023-02-20 2025-10-24 京微齐力(北京)科技股份有限公司 Fpga布局方法、装置、电子设备和存储介质

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US20090031277A1 (en) 2009-01-29
US8966415B2 (en) 2015-02-24
WO2009014731A2 (en) 2009-01-29
US20140053120A1 (en) 2014-02-20
US8819608B2 (en) 2014-08-26
WO2009014731A9 (en) 2009-04-09
JP5706689B2 (ja) 2015-04-22
EP2171623A2 (en) 2010-04-07
JP2010534374A (ja) 2010-11-04

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Application publication date: 20100901