JP2010521816A - Integrated MIS photoelectric device using continuous film - Google Patents

Abstract

An integrated photoelectric device having a metal-insulator-semiconductor (MIS) photodiode includes one or more substantially continuous layers of semiconductor material and a substantially continuous layer of dielectric material. Composed.

Description

This application is based on a continuation-in-part of US application Ser. No. 10 / 882,603, filed Jul. 1, 2004, entitled “Integrated MIS Photoelectric Device Using Continuous Films”.
The present invention relates to an image sensor, and more particularly to an image sensor having a pixel circuit mounted with a metal / insulator semiconductor (MIS) photodiode.

  Image sensors used for wide area X-ray imaging often use pixel circuits in which mesa-isolated MIS photodiodes are used as photosensitive devices. (It is formed by etching away some of the active material so that the mesa-isolated device leaves a “mesa” -like active material.) Other common photoelectric devices are mesa-isolated pins It is a photodiode. Another conventional photoelectric device is a p-i-n photodiode consisting of a substantially continuous film. However, such conventional photoelectric devices have drawbacks. Both mesa-isolated MIS and p-i-n photodiodes typically produce only weak image signals. A p-i-n photodiode consisting of a substantially continuous film exhibits significant crosstalk between adjacent pixel circuits.

  As shown in FIG. 1, a conventional embodiment 10a of a pixel circuit implemented with mesa-isolated MIS photodiodes and thin film transistors (TFTs) is typically integrated as shown. Starting from the substrate 12, various layers of dielectric (insulator), semiconductor and semiconductor material are formed (deposited). For example, a patterned conductive material (eg, metal) on the top surface of the substrate 12 forms the bottom electrode of the MIS photodiode 14a and the gate terminal 32 of the TFT 16. Next, a patterned layer of dielectric material forms the dielectric 26a of the MIS photodiode 14a and the gate dielectric 34 of the TFT 16. Further, patterned intrinsic amorphous silicon (ia-Si) forms one of the semiconductor layers 24a (light absorption layer) of the MIS photodiode 14a and the channel 36 of the TFT 16. Further, the patterned n + amorphous silicon forms the remaining semiconductor layer, ohmic contact 22a, and more effectively ohmic contacts 38 for the top electrode of MIS photodiode 14a, the drain of TFT 16, and the source terminal. In addition, other patterned conductive layers (eg, metal) form the drains 42 and sources 44, the data lines 46, and the bias lines 30 of the TFT 16. Finally, a protective (dielectric) layer 50 follows.

  Another embodiment 10b of the conventional pixel circuit of FIG. 2 uses a mesa-isolated p-i-n photodiode 14b instead of a mesa-isolated MIS photodiode. In the embodiment 10b, the configuration of the TFT 16 is substantially the same as the embodiment 10a of FIG. However, a p-i-n photodiode 14b is used in place of the MIS photodiode 14a. The layer with the pattern of conductive material (eg, metal) that forms the source terminal 44 of the TFT 16 also forms the bottom electrode 20b of the p-i-n photodiode 14b. This is followed by a layer having a pattern of n + amorphous silicon 28b, a layer having a pattern of intrinsic amorphous silicon 24b, and p + amorphous silicon 22b (to form together the p-i-n configuration of photodiode 14b). In addition, a layer with a pattern of optically transparent conductive material (eg, indium tin oxide, or ITO) forms the upper electrode 18b. In addition, a layer with a pattern of dielectric material can deposit a conductive material (eg, metal) to form the dielectric layer 52 (the bias line 30 in contact with the top 18b of the photodiode 14b). , Via holes are formed).

  As shown in FIG. 3, another embodiment 10c of the conventional pixel circuit using the pin photodiode 14c is similar to the embodiment 10b of FIG. 2, but a substantial part of the photodiode 14c is In contrast to forming a mesa-isolated configuration, it is formed of a continuous membrane. Thus, the manufacture and materials for the various photodiodes 24c, 22c and 18c are the same except for the continuous film.

  As noted above, a common drawback of mesa-isolated MIS and p-i-n photodiode sensors is the low signal level. In a mesa-isolated configuration, such a photoelectric element has a fill ratio of 1 or less (fill ratio is defined as the area of the photoelectric element divided by the pixel area). Therefore, not all of the light that the pixel impinges on is absorbed by the photoelectric element. Therefore, the maximum possible signal strength cannot be obtained.

  The mesa isolated MIS photodiode configuration of FIG. 1 has further disadvantages. The same film used to form the channel 36 of the TFT 16 is also used to form the light absorbing layer 24a of the MIS photodiode 14a. In general, the performance of the TFT 16 is optimized when the channel 36 is thin, and the performance of the MIS photodiode 14a is optimized when the light absorption layer 24a is thick. With one film, the performance of one or both of TFT 16 and MIS photodiode 14a is problematic because the thickness of the selected film is not optimal for one or both.

  With respect to signal strength, as shown in Example 10c of FIG. 3, the p-i-n photodiode 14c substantially formed of a continuous film has improved signal strength. With this photoelectric element with a fill ratio close to 1, the maximum signal intensity can be obtained. However, with this configuration, there is significant crosstalk between adjacent pixels. For example, the interface 54 between the dielectric intermediate layer 52 and the light absorbing layer 24c has a non-zero conductivity. Therefore, a potential difference between the bottom electrodes 20c of adjacent pixels forms a slight current, that is, crosstalk, between these pixels.

  The integrated photoelectric device has a mesa-isolated semiconductor (MIS) photodiode 14 composed of one or more substantially continuous layers of semiconductor material, and a substantially continuous layer of dielectric material. .

  In accordance with embodiments of the present invention, an integrated photoelectric device is an apparatus including an integrated photoelectric device, the substrate and a metal-insulator semiconductor (MIS) photodiode, the photodiode And a metal-insulator-semiconductor (MIS) photodiode located at least a portion of the substrate. The MIS photodiode comprises a first and second electrode and one or more dielectrics, wherein at least a portion of at least one dielectric is located between the first and second electrodes ( At least one portion of the one or more dielectrics has a substantially continuous layer of dielectric material), and one or more semiconductors, at least a portion of the at least one semiconductor being one or more dielectrics A semiconductor (at least one portion of the one or more semiconductors having a substantially continuous layer of semiconductor material) located between one of the first electrode and one of the first and second electrodes; Three electrodes, and a portion of the third electrode is positioned at least partially along a peripheral portion of one of the first and second electrodes so that they are not in a common plane.

  In accordance with another embodiment of the present invention, an integrated photoelectric device includes a substrate and a MIS photodiode, at least a portion of the photodiode being located on the substrate. The MIS photodiode includes a plurality of conductive layers including at least first, second, and third conductive layers (each having first, second, and third conductive materials) and one or more insulating layers. A layer (at least a portion of at least one insulating layer is located between the first and second conductive layers, and at least one of the at least one portion of the insulating layer has a substantially continuous film of insulating material). ) And one or more semiconductor layers (at least a portion of at least one semiconductor is located between one of the one or more insulating layers and one of the first and second conductive layers) At least one portion of the semiconductor layer has a substantially continuous film of semiconductor material), and one of the first and second conductive layers includes the periphery, A conductive layer at least partially around the periphery Is positioned so as not in a common plane me.

  In accordance with another embodiment of the present invention, an integrated photoelectric array includes a substrate and a MIS photodiode, with at least a portion of the photodiode positioned side by side on the substrate. Each of at least a portion of the plurality of MIS photodiodes includes a first and a second electrode, one or more dielectrics (at least a portion of the dielectric is located between the first electrode and the second electrode). , At least one of the one or more portions of the dielectric has a substantially continuous layer of dielectric material), one or more semiconductors (at least one portion of the semiconductor is one of the one or more dielectrics) One of the first and second electrodes, at least one of the one or more semiconductor portions having a substantially continuous layer of semiconductor material), and a third electrode ( A portion of the third electrode is at least partially located along a circumference of one of the first and second electrodes.

  In accordance with another embodiment of the present invention, an integrated photoelectric device includes a substrate and a MIS photodiode, at least a portion of the photodiode being located on the substrate. An MIS photodiode includes a first and a second electrode, one or more dielectrics (at least a portion of the dielectric is located between the first electrode and the second electrode, and one or more dielectrics At least one of the bodies has a substantially continuous layer of dielectric material), one or more semiconductors (at least one portion of the semiconductor is one of the one or more dielectrics, and first and second electrodes) And a third electrode (the third electrode is at least partially) located between and at least one of the one or more semiconductor portions having a substantially continuous layer of semiconductor material) In a common plane along a peripheral portion of one of the first and second power sources.

  In accordance with another embodiment of the present invention, an integrated photoelectric device includes a substrate and a MIS photodiode, at least a portion of the photodiode being located on the substrate. MIS photodiode includes first and second electrodes, one or more dielectrics (at least a portion of the dielectric is located between the first and second electrodes), one or more A semiconductor (at least a portion of the semiconductor being located between one of the one or more dielectrics and one of the first and second electrodes), and a third electrode (third electrode) At least partially along the peripheral portions of the first and second electrodes so that they are not in a common plane.

  In accordance with another embodiment of the present invention, an integrated photoelectric device includes a substrate and a MIS photodiode, at least a portion of the photodiode being located on the substrate. The MIS photodiode includes a plurality of conductive layers, at least one insulating layer including at least first, second and third conductive layers each having a film of first, second and third conductive materials. (At least a portion of at least one of the insulating layers is located between the first conductive layer and the second conductive layer.), And one or more semiconductor layers (at least a portion of at least one of the semiconductor layers is 1 One of the two or more insulating layers and one of the first and second conductive layers.). One of the first and second conductive layers has a perimeter, and the third conductive layer is at least partially positioned so that it is not in a common plane along a portion of the perimeter.

  In accordance with another embodiment of the invention, an integrated photoelectric device includes a substrate and a plurality of MIS photodiodes, wherein at least a portion of the photodiodes are positioned in a row on the substrate. Each of at least a portion of the plurality of MIS photodiodes includes a first and a second electrode, one or more dielectrics (at least a portion of the dielectric is located between the first electrode and the second electrode). One) one or more semiconductors (at least a portion of at least one of the semiconductors is located between one of the one or more dielectrics and one of the first and second electrodes), and a third (A portion of the third electrode is located at least partially, not in a common plane along the peripheral portion of one of the first and second electrodes).

FIG. 1 is a cross-sectional view of a conventional pixel circuit using an MIS photodiode. FIG. 2 is a cross-sectional view of a conventional pixel circuit using a p-i-n photodiode. FIG. 3 is a cross-sectional view of another conventional pixel circuit using a p-i-n photodiode. FIG. 4 is a schematic diagram of a pixel circuit according to one embodiment of the present invention. FIG. 5 is a partial plan view of an integrated circuit including a pixel circuit corresponding to the schematic diagram of FIG. 6 is a cross-sectional view taken along line A-A 'of FIG. FIG. 7 is a sectional view taken along line B-B ′ of FIG. 5. FIG. 8 is a diagram showing energy bands related to integration and reset that operate in the pixel circuit of FIG. FIG. 9 is a schematic diagram of a pixel circuit according to another embodiment of the present invention. FIG. 10 is a partial plan view of an integrated circuit including a pixel circuit corresponding to the schematic diagram of FIG. FIG. 11 is a sectional view taken along line A-A ′ of FIG. 10. FIG. 12 is a schematic diagram of a pixel circuit according to another embodiment of the present invention. FIG. 13 is a partial plan view of an integrated circuit including a pixel circuit corresponding to the schematic diagram of FIG. FIG. 14 is a sectional view taken along line A-A ′ of FIG. 13. FIG. 15 is a schematic diagram of a pixel circuit according to another embodiment of the present invention. 16 is a partial plan view of an integrated circuit including a pixel circuit corresponding to the schematic diagram of FIG. FIG. 17 is a sectional view taken along line A-A ′ of FIG. 16.

  The following detailed description is of embodiments of the invention with reference to the drawings. This description is merely exemplary and is not intended to limit aspects of the invention. These embodiments are described in detail so that those skilled in the art can practice the present invention, and it is understood that other embodiments can be modified and implemented without departing from the spirit or aspect of the present invention. Let's be done.

  As shown in FIG. 4, the pixel circuit 100 according to one embodiment of the present invention includes a MIS photodiode 114 and a TFT 116 (these elements are connected to a bias line 130, a gate line 132 and a data line 146). Well-known in the technical field of pixel circuits). The MIS photodiode 114 includes an optically transparent top electrode 118 and bottom electrode 120 (with semiconductor layers 122, 124 and insulator 126 vertically between them). However, the bottom electrode 120 is in contact with a guard ring 156 connected to a guard line 158 to which a voltage is applied to suppress crosstalk between adjacent pixels (described below).

  As shown in FIG. 5, the plane of a part 200 of the integrated circuit including the pixel circuit mounted according to the pixel circuit 100 of FIG. 4 shows the pixel circuit 100b, and the pixel circuit 100b is vertically and horizontally. The pixel circuits 100a, 100c, 100d, and 100e are in contact with each other.

  FIG. 6 is a cross-sectional view taken along line A-A ′ in FIG. 5 and shows the configuration of the TFT 116 and the MIS photodiode 114. The configuration of the TFT 116 is substantially the same as that of the conventional pixel circuits 10a, 10b, and 10c shown in FIGS. Immediately above the substrate 112 (the primary role is the base and support for the material layer), guard lines 158 are formed with patterned amorphous silicon layers 136, 138 and conductive layer 142 (part of the TFT 116). Can also be used to form). There is an intermediate layer 152 of dielectric material over the guard line 158 and the TFT 116, and a via hole 160 is formed to allow contact between the bottom electrode 120 of the MIS photodiode 114 and the drain terminal 142 of the TFT 116. The The material layer used to form the bottom electrode 120 has a pattern to form the guard ring 156. Next, a dielectric layer 126 and an intrinsic amorphous silicon layer (light absorption layer) 124 follow. Next, there is a layer 122 of n + amorphous silicon in ohmic contact with the optically transparent conductive layer 118 on top. Conductive layer 118 forms the upper electrode of MIS photodiode 114. Finally, there is a protective layer 150.

  FIG. 7 is a cross-sectional view taken along the line B-B ′ in FIG. This region 162 passes through the bias line 130, the gate line 132, the guard link 156 and the guard line 158. The guard ring 156 is formed from a layer of the same material that was used to form the bottom electrodes 120a, 120b of adjacent pixel circuits 100a, 100b. The guard ring 156 contacts the guard line 158 through a via hole 164 formed in the dielectric intermediate layer 152.

  From the above, it will be understood that the pixel circuit 100 of FIG. 4 uses a MIS photodiode 114 formed from a substantially continuous film when implemented as in FIGS. . In particular, the insulator 126 in the photodiode configuration, the semiconductors 122 and 124, and the electrode 118 are continuous. The metal portion of the structure is formed with a pattern such that each pixel has a bottom electrode 120 surrounded by a guard ring 156 that contributes to reducing crosstalk between adjacent pixels.

  As shown in FIG. 8, a pixel street according to the present invention operates (at least in part) as follows. In the integrated mode of operation, the top electrode 118 has a positive potential relative to the potential of the bottom electrode 120. When light is incident on intrinsic layer 124, the light is absorbed and electron-hole pairs are generated. The generated electric field is guided to the upper electrode 118 by the electric field between the electrodes 118 and 120, and the holes move in the intrinsic layer 124 so as to reach the interface of the dielectric layer 126 which is an insulating layer. However, the holes cannot move in the dielectric layer 126 and therefore remain in the intrinsic layer 124. The hole charge collected at the semiconductor / insulator interface as a result of absorption of incident light constitutes the signal of the pixel circuit.

  During the reset mode of operation, the top electrode 118 has a negative potential with respect to the potential of the bottom electrode 120. Electrons enter the ohmic contact semiconductor layer 122 and then the intrinsic (semiconductor) layer 124 through the electrode 118. The entered electrons move to the interface between the intrinsic (semiconductor) layer 124 and the dielectric layer 126 and recombine with holes at the interface. The holes remaining in the intrinsic layer 124 are guided to the upper electrode 118.

  The guard ring 156 has a positive potential with respect to the bottom electrode 120. This forms a potential barrier against Hall signal charge that accumulates on the bottom electrode 120 during the integration mode of operation. This potential barrier suppresses even if it cannot prevent crosstalk between adjacent pixel circuits.

  As shown in FIG. 9, the pixel circuit 300 according to the embodiment of the present invention is connected to the bias line 130, the gate line 132, the data line 146, and the guard line 158 as in the embodiment of FIG. MIS photodiode 114 and TFT 116, but also includes a storage capacitor 170 and a reset line 180. These additional elements are provided for the ability to handle increased signals and for additional reset mechanisms. With respect to the former, the thick semiconductor layer 124 used in the MIS photodiode 114 produces maximum light absorption, but can only provide a low capacitance to the photodiode, limiting its ability to handle charge. This problem is solved by introducing a storage capacitance 170 designed to have a high electrical capacity, and thus can handle large charges. Regarding the latter, in the embodiment of FIG. 4, the imager is reset by pulsing the baseline 130 to a negative voltage relative to the voltage at the bottom electrode (which is nominally the voltage at the data line 146). Is done. In this embodiment 300, the MIS photodiode 114 can be reset by pulsing the reset line 180 to a sufficiently positive voltage with respect to the bias line.

  FIG. 10 is a partial plan view of an integrated circuit including a pixel circuit according to the pixel circuit 300 of FIG. 9, and the pixel circuit 300b is adjacent to the pixel circuits 300a, 300c, 300d, and 300e vertically and horizontally.

  FIG. 11 is a cross-sectional view taken along line A-A ′ in FIG. 10 and shows the configuration of the TFT 116 and the MIS diode 114. The configuration of the TFT 116 is substantially the same as that for the conventional pixel circuits 10a, 10b, and 10c of FIGS. Immediately above the substrate 112, the bottom electrode 178 of the storage capacitor 170 is formed from a layer having the same pattern of conductive material that is used to form the gate terminal 132 of the TFT 116. Next, there is a dielectric layer 176 of the storage capacitor 170, which also functions as the gate dielectric layer 134 of the TFT 116. Guard line 158 is formed from patterned amorphous silicon 136, 138 and conductive layer 142 (used to form various other portions of TFT 116). Above guard line 158 and TFT 116 is an intermediate layer 152 of dielectric material in which via holes 160 and 166 are formed. Via hole 160 allows contact between bottom electrode 120 of MIS photodiode 114 and drain terminal 142 of TFT 116. Via hole 166 allows bottom electrode 120 of MIS photodiode 114 to be in contact with dielectric layer 176 of storage capacitor 170, thereby forming top electrode 174 of storage capacitor 170. The layer of material used to form the bottom electrode 120 of the MIS photodiode 114 has a pattern that also forms the guard ring 156. On top of the layer of material having a pattern that forms the bottom electrode 120 and guard ring 156 of the MIS photodiode 114 is followed by a dielectric layer 126 followed by an intrinsic amorphous silicon layer (light absorbing layer) 124. In addition, an n + amorphous silicon layer 122 forming an ohmic contact is followed by an optically transparent conductive layer 118. Conductive layer 118 forms the upper electrode of MIS photodiode 114. Finally, there is a protective layer 150.

  As shown in FIG. 12, a pixel circuit 500 according to another embodiment of the present invention includes a bias line 130, a pass gate line 132, a data line 146, and a guard line as shown in FIG. MIS photodiode 114 and path TFT 116 connected to 158, but also includes buffer / amplifier TFT 190, reset TFT 182, initialization TFT 184, reset gate line 186, initialization gate line 188, VDD line 192, and VSS line 194. Including. The buffer / amplifier TFT 190 operates in a voltage output mode or a current output mode, depending on how the data line 146 is terminated. The reset TFT 182 clears all signal charges of the MIS photodiode 114 after the integration mode, and the initialization TFT 184 resets the potential of the bottom electrode 120 of the MIS photodiode 114 before the integration mode. Pixel circuit 500 is an example of a class of pixel circuits known as “active” pixel circuits (defined as pixel circuits including amplifiers).

  FIG. 13 is a plan view of a part 600 of the integrating circuit according to the pixel circuit 500 of FIG. 12, and shows the pixel circuit 500 that is in contact with the pixel circuits 500a, 500c, 500d, and 500e vertically and horizontally.

  FIG. 14 is a cross-sectional view taken along line A-A ′ of FIG. 13 and shows the configuration of the MIS photodiode 114, the path TFT 116, the buffer / amplifier TFT 190, the reset TFT 182, and the initialization TFT 184. The configuration of the TFT is substantially the same as the configuration of the TFT of the previous pixel circuits 10a, 10b, and 10c in FIGS. Just above the substrate 112, the guard lines 158 are formed from patterned amorphous silicon layers 136, 138 and a conductive layer 142 (also used to form part of the TFT). Overlying the guard line 158 and the TFT is a first dielectric material intermediate layer 152 with via holes formed so that the metal patterned layer can interconnect the pixel circuits. Above the interconnect metal layer is an intermediate layer 153 of a second dielectric material. Via holes formed in both dielectric material layers 152 and 153 allow the bottom electrode of MIS photodiode 114 to connect to a metal pad that connects to the gate of buffer / amplifier TFT 190. The layer of material used to form the bottom electrode 120 of the MIS photodiode 114 has a pattern that also forms the guard ring 156. On top of the layer of material with a pattern that forms the bottom electrode 120 and guard ring 156 of the MIS photodiode 114 is a dielectric layer 126, followed by a layer 124 of intrinsic amorphous silicon. In addition, there is a layer 122 of n + amorphous silicon to form an ohmic contact with the optically transparent conductive layer 118. The conductive layer 118 forms the upper electrode of the MIS photodiode 114. Finally, there is a protective layer 150.

  From the foregoing, it will be seen that the MIS photodiode 114 according to the present invention has a higher pixel fill ratio than both mesa-isolated MIS and pin photodiodes, thereby producing a higher signal level. . Despite the thick film affecting the optimization of TFT performance, the light absorbing semiconductor layer 124 is mesa-isolated by optimizing for maximum light absorption, thereby generating maximum signal. Provides advantages over MIS photodiode configurations.

  Furthermore, the use of a guard ring with a bottom electrode and a substantially enclosing boundary does not eliminate crosstalk between adjacent pixel circuits in a photodiode structure consisting of a substantially continuous film. Reduce well.

  Furthermore, MIS photodiodes according to the present invention using continuous membranes can reduce manufacturing costs compared to mesa-isolated and continuous membrane-type p-i-n photodiode configurations. Without conditions for p-type amorphous silicon material, the MIS photodiode configuration according to the present invention is the same manufacturing equipment used to form a standard TFT backplane for liquid crystal display (LCD) Can be manufactured using. Such a manufacturing facility enjoys the advantages associated with mass production, and thus can be produced at low cost.

  In embodiments of the present invention that can benefit under appropriate conditions, the bias line 130 is eliminated (see FIGS. 4-5, 7, 9-10 and 12-13). If the active area of the imager is sufficiently small and the sheet resistance of the continuous upper electrode 118 can be sufficiently small, it is not necessary to have a bias line 130 that addresses all the pixel circuits of the image sensor array. Rather, a global bias connection is made to the top electrode 118 around the array. Since the bias line 130 is the only configuration that can blur the light colliding on the MIS photodiode 114, the removal of the bias line 130 provides a pixel circuit with a filling ratio close to 1. Removal of the bias line 130 results in very high production in the manufacturing process.

  In embodiments of the invention that can benefit under appropriate conditions, the optically transparent conductive material (eg, ITO) commonly used to form the top electrode 118 is removed. (See FIGS. 6-7, 11 and 14). If the active area of the imager is sufficiently small and the sheet resistance of the n + amorphous silicon semiconductor layer 122 is sufficiently small, the n + amorphous silicon semiconductor layer 122 can function as the upper electrode 118. The removal of the optically transparent conductive material results in high productivity in the manufacturing process.

  In other embodiments of the present invention that can benefit under appropriate conditions, the guard line 158 can be eliminated (FIGS. 4-7, 9-11, 12-14). If the active area of the imager is small enough and the sheet resistance of the guard ring grid configuration 156 is small enough, there is no need to have a guard line 158 that addresses all the pixel circuits in the image sensor array. Rather, the global connection is a guard ring grid configuration around the array. Removal of the guard ring 158 provides high productivity in the manufacturing process.

  In other embodiments of the invention that can benefit, an additional dielectric layer is incorporated between the dielectric layer 126 and the semiconductor layer 124 (FIGS. 4, 6-7, 9, 11-). 12 and FIG. 14). The dielectric material between the bottom electrode 120 and the continuous semiconductor layer 124 must achieve several purposes. This dielectric material must have sufficient thickness and structural integrity so that it does not break under the electric field formed between the bottom electrode 120 and the continuous top electrode 118. This dielectric material must be sufficiently free of internal stresses so as not to distort the underlying substrate 12. This dielectric material must interface with a continuous semiconductor layer 124 that minimizes electron and hole trapping conditions, which are what cause lag problems, i.e., ghost images. None of the continuous dielectric layers 126 may fully meet all these conditions.

  In other embodiments of the invention that can benefit from, the guard ring 156 is made from one or more layers of conductive material different from that used to form the bottom electrode 120 of the MIS photodiode 114. (See FIGS. 5-7, 10-11, and 13-14). This is done, for example, to form a guard ring that reduces the parasitic capacitance of the data line 146 located directly below a portion of the guard ring 156. It is desirable to minimize the parasitic capacitance of the data line 146 where such capacitance will cause noise in the imaging process (especially for the pixel circuits of FIGS. 4 and 9). A guard ring 156 that reduces the parasitic capacitance of the data line 146 is a guard ring 156 located, for example, by deposition of a further layer of dielectric material, followed by deposition of a further layer of conductive material, and just above the bottom electrode 120. The two layers have a pattern to form a bottom electrode 120 subsequent to the formation. Further isolation of the guard ring 156 from the data line 146 reduces the parasitic capacitance of the data line 146.

  As shown in FIG. 15, a pixel circuit 700 according to another embodiment of the present invention includes a bias line 130, a pass gate line 132, a data line 146 and a guard line as shown in FIG. MIS photodiode 114 and path TFT 116 connected to 158. However, in this embodiment, the guard ring 156 and the bottom electrode 120 have a pattern different from the above-described conductive material layer, and the card ring 156 has a part of the guard ring 156 and a part of the bottom electrode 120. It is located under the bottom electrode 120 so as to overlap. In this configuration, the potential well for signal charges is maximized in a limited space in the semiconductor layer 124 above the bottom electrode 120 and is clearly defined. This configuration also minimizes the possibility of undesirable potential barrier formation between a portion of the semiconductor layer 124 above the center of the guard ring 156 and a portion of the semiconductor layer 124 above the edge of the bottom electrode 120. To do. This ensures maximum signal collection and a fill ratio of 1 or less.

  Thus, it will be appreciated from the above description that at least a portion of the guard ring 156 may be located between or below the top electrode 118 and the bottom electrode 120 as another example. At least a portion of the card ring 156 can be suitably placed above or below the bottom electrode 120 such that the card ring 156 and a portion of the bottom electrode 120 overlap each other. In other words, a common feature of these other embodiments is that at least some of the adjacent portions (eg, surrounding portions) of the guard ring 156 and the bottom electrode 120 are not in a common plane with each other. Such an arrangement can be formed as described above by forming the card ring 156 and the bottom electrode 120 in different layers, to ensure that the appropriate parts are on different sides, or even in the same layer. However, it is achieved simply by ensuring that the appropriate parts are on different sides.

  As shown in FIGS. 16 and 17, plan views of a part 800 of an integrated circuit including a pixel circuit implemented according to the pixel circuit 700 of FIG. 15 are pixel circuits 700a, 700c, 700d, 700e, 700f, A pixel circuit 700b surrounded by 700g, 700h, and 700i is illustrated, and a cross section along the line AA ′ illustrates a configuration of the MIS photodiode and the TFT. The various structural features are substantially the same as those described in connection with FIGS. 12-14 (except that the card ring 156 and the top electrode 118 are not connected to a bus line passing through each pixel). It is. Instead, the guard ring 156 and the upper electrode 118 are generally connected to the guard line 158 and the vice line 130 by metal lines at or near the periphery of the pixel array (not shown), respectively. This simplifies the overall design and enables high productivity.

  In another embodiment of the present invention that can benefit, a p + amorphous silicon layer is used, such as a doped amorphous silicon layer 122 in contact with the top electrode 118 of the MIS photodiode 114 (FIGS. 4, FIG. 4-9, see FIGS. 11-12, and FIG. 14). In this case, the polarity of all the biases, in contrast to the above case, is that the signal carrier is an electron.

  In other embodiments of the invention, other materials can be used in any part of the device configuration. For example, an organic electronic material having conductive characteristics, semiconductive characteristics, and insulating characteristics is replaced with an inorganic electronic material having the corresponding characteristics described above. In embodiments using organic electronic materials, the relative position of the various material layers, the polarity of the signal carrier, and the operating voltage vary. Such a change is necessary because the organic TFT has a gate electrode located above but not below the source and drain. However, the basic structure of a MIS photodiode using a continuous layer, employing a guard ring, and having a pixel circuit underneath is basically implemented even by using an organic electronic material.

  It will be appreciated by those skilled in the art that, as illustrated and described above, some of the features of the present invention are not essential and appropriate. For example, various layers of materials such as dielectric material 126 have been described as being continuous. Such continuity is substantive, i.e., it is not essential, it is continuous throughout the construction of the photodiode, and this objective can be achieved and related functions can be obtained. This means that it is sufficient for the purpose. (It will be appreciated that, for example, the processes used for semiconductor manufacturing are not perfect and spaces that are not required for a continuous configuration may be designed.) Similarly, with respect to the boundary of the bottom electrode 120, the guard The vicinity of the ring 156 is also substantially, i.e. absolute or complete, for the purpose of obtaining the relevant function of maintaining the desired electric field that contributes to minimizing crosstalk between adjacent pixels. It's not enough but it's enough.

  It will be apparent to those skilled in the art that various modifications and variations can be made to the structure and method of operation of the present invention without departing from the spirit or aspect of the invention. Although the invention has been described in connection with specific preferred embodiments, the invention is not limited to such specific embodiments. The embodiments of the present invention are defined by the claims, and the structures and methods within the scope of the embodiments and equivalents thereof are included in the embodiments.

Claims (37)

An apparatus comprising an integrated photoelectric device,
A substrate,
A metal / insulator semiconductor (MIS) photodiode, wherein at least a portion of the photodiode is located on the substrate; and
Including
The MIS photodiode is
First and second electrodes;
One or more dielectric layers, wherein at least a portion of at least one of the dielectric layers is located between the first and second electrodes;
One or more semiconductors, wherein at least a portion of at least one of the semiconductors is located between one of the one or more dielectric layers and one of the first and second electrodes. When,
A third electrode;
Have
At least one portion of the one or more dielectric layers has at least a substantially continuous layer of dielectric material;
At least one of the one or more portions of the semiconductor has at least a substantially continuous layer of semiconductor material;
A portion of the third electrode is at least partially positioned such that it is not in a common plane along the periphery of one of the first and second electrodes;
A device characterized by that.   2. The one of the first and second electrodes, comprising a substantially continuous electrode positioned substantially adjacent to at least one of the one or more semiconductor portions. apparatus.   The apparatus of claim 1, comprising one or more thin film transistors (TFTs) coupled to the MIS photodiode. At least one of the one or more TFTs has a channel region having a thickness;
4. The apparatus of claim 3, wherein at least one of the one or more MIS photodiodes has a thickness that is greater than a thickness of the channel region of the at least one TFT.   The at least one of the semiconductor portions of the one or more MIS phototransistors having a thickness greater than the thickness of the channel region of the at least one TFT comprises a substantially continuous layer of the semiconductor material. The device described in 1.   The apparatus of claim 3, wherein at least one of the one or more TFTs is substantially located between the MIS photodiode and the substrate. The apparatus of claim 1, wherein at least one of the semiconductor portions of the one or more MIS photodiodes includes n-type amorphous silicon (aS _i ). An apparatus comprising an integrated photoelectric device,
A substrate,
A metal / insulator semiconductor (MIS) photodiode, wherein at least a portion of the photodiode is located on the substrate; and
Including
The MIS photodiode is
A plurality of conductive layers including at least first, second and third conductive layers each having first, second and third films of conductive material;
One or more insulating layers, wherein at least a portion of at least one of the insulating layers is located between the first and second conductive layers;
One or more semiconductor layers, wherein at least a portion of at least one of the semiconductors is located between one of the one or more insulating layers and one of the first and second conductive layers. However, the semiconductor layer,
Have
At least one portion of the one or more insulating layers comprises a substantially continuous film of insulating material;
At least one of the portions of the one or more semiconductor layers comprises a substantially continuous film of semiconductor material;
One of the first and second conductive layers has a perimeter, and the third conductive layer is at least partially not in a common plane along a portion of the perimeter;
A device characterized by that.   One of the first and second conductive layers includes at least a substantially continuous conductive layer located substantially proximate to the at least one of the one or more semiconductor portions. The apparatus according to claim 8.   The apparatus of claim 8, further comprising one or more thin film transistors (TFTs) coupled to the MIS photodiode. At least one of the one or more TFTs has a channel region having a thickness;
11. The apparatus of claim 10, wherein at least one of the one or more MIS photodiodes has a thickness that is greater than a thickness of the channel region of the at least one TFT.   The at least one of the semiconductor portions of the one or more MIS phototransistors having a thickness greater than the thickness of the channel region of the at least one TFT comprises at least a substantially continuous layer of the semiconductor material. 11. The apparatus according to 11.   The apparatus of claim 10, wherein at least one of the one or more TFTs is substantially located between the MIS photodiode and the substrate. Comprising said one or more MIS photodiode semiconductor of a portion of at least one of n- type amorphous silicon (aS _i), according to claim 8. A device comprising an integrated photoelectric array,
A substrate,
A plurality of metal-insulator semiconductor (MIS) photodiodes, wherein a plurality of metal-insulator semiconductor (MIS) photodiodes wherein at least a portion of the plurality of photodiodes are arranged side by side on the substrate;
Including
Each of the at least some of the plurality of MIS photodiodes is
First and second electrodes;
One or more dielectrics, wherein at least a portion of at least one of the dielectrics is located between the first and second electrodes;
One or more semiconductors, wherein at least a portion of at least one of the semiconductors is located between one of the one or more insulators and one of the first and second electrodes; ,
A third electrode;
Have
At least one of the one or more portions of the dielectric includes at least a substantially continuous layer of dielectric material;
At least one of the one or more semiconductor portions includes at least a substantially continuous layer of semiconductor material;
A portion of the third electrode is at least partially positioned such that it is not in a common plane along a peripheral portion of one of the first and second electrodes;
A device characterized by that.   The one or more of the first and second electrodes comprises at least a substantially continuous electrode positioned substantially proximate to the at least one of the one or more semiconductor portions. Equipment.   16. The apparatus of claim 15, further comprising one or more thin film transistors (TFTs) coupled to the MIS photodiode. Each of at least a portion of the plurality of TFTs includes a channel region having a thickness;
The apparatus of claim 17, wherein at least one of a portion of the one or more MIS photodiodes in each of the plurality of MIS photodiodes has a thickness that is greater than a thickness of a channel region of the plurality of TFTs.   The at least one of the semiconductor portions of the one or more MIS photodiodes in each of the plurality of MIS photodiodes having a thickness greater than the thickness of the plurality of TFT channel regions is at least substantially the semiconductor material. The apparatus of claim 18, wherein the apparatus has a continuous layer.   The apparatus of claim 17, wherein each of at least a portion of the plurality of TFTs is substantially located between each of the at least a portion of the plurality of MIS photodiodes and the substrate.   The apparatus of claim 15, wherein at least one of the semiconductor portions of the one or more MIS photodiodes includes n-type amorphous silicon (a-Si). An apparatus comprising an integrated photoelectric device,
A substrate,
A metal / insulator semiconductor (MIS) photodiode, wherein at least a portion of the photodiode is located on the substrate; and
Including
The MIS photodiode is
First and second electrodes;
One or more dielectrics, wherein at least a portion of at least one of the dielectrics is located between the first and second electrodes;
One or more semiconductors, wherein at least a portion of at least one of the semiconductors is located between one of the one or more insulators and one of the first and second electrodes; ,
A third electrode substantially adjacent to one of the first and second electrodes;
Have
At least one of the one or more portions of the dielectric includes at least a substantially continuous layer of dielectric material;
At least one of the one or more portions of the semiconductor includes at least a substantially continuous layer of semiconductor material;
A portion of the third electrode is located at least partially such that it is not in a common plane along a peripheral portion of one of the first and second electrodes;
A device characterized by that. An apparatus comprising an integrated photoelectric device,
A substrate,
A metal / insulator semiconductor (MIS) photodiode, wherein at least a portion of the photodiode is located on the substrate; and
Including
The MIS photodiode is
First and second electrodes;
One or more dielectrics, wherein at least a portion of at least one of the dielectrics is located between the first and second electrodes;
One or more semiconductors, wherein at least a portion of at least one of the semiconductors is located between one of the one or more insulators and one of the first and second electrodes; ,
A third electrode;
Have
A portion of the third electrode is located at least partially such that it is not in a common plane along a peripheral portion of one of the first and second electrodes;
A device characterized by that.   24. The apparatus of claim 23, further comprising one or more thin film transistors (TFTs) coupled to the MIS photodiode. At least one of the one or more TFTs has a channel region having a thickness;
25. The apparatus of claim 24, wherein at least one of the one or more MIS photodiodes has a thickness that is greater than a thickness of a channel region of the at least one TFT.   25. The apparatus of claim 24, wherein at least one of the one or more TFTs is substantially located between the MIS photodiode and the substrate. Comprising said one or more MIS photodiode semiconductor of a portion of at least one of n- type amorphous silicon (aS _i), according to claim 23. An apparatus that is integrated and includes a photoelectric device,
A substrate,
A metal / insulator semiconductor (MIS) photodiode, wherein at least a portion of the photodiode is located on the substrate; and
Including
The MIS photodiode is
A plurality of conductive layers, wherein the plurality of conductive layers have at least first, second and third conductive layers each including first, second and third films of conductive material;
One or more insulating layers, wherein at least a portion of at least one of the insulating layers is located between the first and second conductive layers;
One or more semiconductor layers, wherein at least a portion of at least one of the semiconductors is located between one of the one or more insulating layers and one of the first and second conductive layers. A semiconductor layer of
Have
One of the first and second conductive layers has a perimeter, and the third conductive layer is positioned at least partially not in a common plane along a portion of the perimeter. ,
A device characterized by that.   30. The apparatus of claim 28, further comprising one or more thin film transistors (TFTs) coupled to the MIS photodiode. At least one of the one or more TFTs has a channel region having a thickness;
29. The apparatus of claim 28, wherein at least one of the one or more MIS photodiodes has a thickness that is greater than a thickness of the channel region of the at least one TFT.   30. The apparatus of claim 29, wherein at least one of the one or more TFTs is substantially located between the MIS photodiode and the substrate. Comprising said one or more MIS photodiode semiconductor of a portion of at least one of n- type amorphous silicon (aS _i), according to claim 28. A device comprising an integrated photoelectric array,
A substrate,
A plurality of metal-insulator semiconductor (MIS) photodiodes, wherein a plurality of metal-insulator semiconductor (MIS) photodiodes wherein at least a portion of the plurality of photodiodes are arranged side by side on the substrate;
Including
Each of the at least some of the plurality of MIS photodiodes is
First and second electrodes;
One or more dielectrics, wherein at least a portion of at least one of the dielectrics is located between the first and second electrodes;
One or more semiconductors, wherein at least a portion of at least one of said semiconductors is located between one of said one or more dielectrics and one of said first and second electrodes; ,
A third electrode, wherein a portion of the third electrode is located at least partially not in a common plane along a peripheral portion of the first and second electrodes;
A device characterized by that.   34. The apparatus of claim 33, further comprising a plurality of thin film transistors (TFTs) coupled to the plurality of MIS photodiodes. Each of at least a portion of the plurality of TFTs includes a channel region having a thickness;
35. The apparatus of claim 34, wherein at least one of a portion of the one or more MIS photodiodes in each of the plurality of MIS photodiodes has a thickness that is greater than a thickness of a channel region of the plurality of TFTs.   35. The apparatus of claim 34, wherein each of at least a portion of the plurality of TFTs is substantially located between each of the at least a portion of the plurality of MIS photodiodes and the substrate.   34. The apparatus of claim 33, wherein at least one of the semiconductor portions of the one or more MIS photodiodes includes n-type amorphous silicon (a-Si).

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