JP2019091788A - Solid-state imaging device and forming method thereof - Google Patents

Abstract

To provide a solid-state imaging device and a forming method thereof suitable to prevent the deterioration of image quality caused by irradiation of radiation.SOLUTION: A solid-state imaging device includes a semiconductor substrate 100, a PN junction type photodiode PD1 formed on the surface of the semiconductor substrate 100, an insulating film 106 formed on the surface of the semiconductor substrate 100 including the upper surface of the photodiode PD1, and a metal electrode MTL formed in a wiring layer having a higher level than the first wiring layer adjacent to photodiode PD1 and to which a negative voltage is applied from among a plurality of wiring layers stacked on the insulating film 106.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a solid-state imaging device and a method of forming the same, and more particularly to a solid-state imaging device suitable for preventing deterioration in image quality caused by irradiation of radiation and a method of forming the same.

  In recent years, the use of high-performance cameras is expected in the space technology field, the nuclear field and the like. For example, Patent Document 1 discloses a technique related to a solid-state imaging device used for a high-performance camera.

  The photosensitive element (solid-state imaging element) disclosed in Patent Document 1 includes a photodiode formed of a P well formed on a semiconductor substrate and an N type photosensitive region formed on the surface, and a photodiode formed on the surface of the photosensitive region. A transparent insulating layer, and a transparent conductive layer made of indium tin oxide (ITO) formed on the surface of the transparent insulating layer. Furthermore, in this photosensitive element, a P-type pinning layer (pinning layer) is formed on the surface of the photosensitive region by applying a negative voltage from the transparent conductive layer to the photosensitive region. Thereby, this photosensitive element can sweep dark current generated by thermal excitation at the interface between the photosensitive region and the transparent insulating layer to the ground via the pinning layer, thus improving the quality of the image. Can.

Patent 3049015 gazette

  However, in electronic devices used in space, nuclear facilities, radiation facilities, etc., unlike the normal environment, the fixed positive charge is fixed in the insulating film by the ionizing action of the total dose effect generated by irradiation of radiation such as gamma rays. There is a problem that various characteristics deteriorate due to the accumulation because of accumulation.

  Specifically, in the configuration of the photosensitive element disclosed in Patent Document 1, the fixed positive charge is accumulated in the transparent insulating layer by the ionizing action of the total dose effect generated by the irradiation of the radiation. The pinning layer is inverted to N-type, and the pinning layer does not function properly. As a result, in this photosensitive element, since dark current is accumulated at the interface between the photosensitive region and the transparent insulating layer, there is a problem that deterioration of the image quality such as whiteout occurs. Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, the solid-state imaging device includes a semiconductor substrate, a PN junction photodiode formed on the surface of the semiconductor substrate, and a surface of the semiconductor substrate including the surface on which the photodiode is formed. Among the formed insulating film and the plurality of wiring layers stacked on the insulating film, it is formed in a wiring layer higher than the first wiring layer adjacent to the photodiode, and a negative voltage is applied. And a first metal electrode.

  Further, according to one embodiment, in the method of forming a solid-state imaging device, a PN junction type photodiode is formed on the surface of a semiconductor substrate, and insulation is provided on the surface of the semiconductor substrate including the formation surface of the photodiode. Forming a film, forming a first metal electrode in a wiring layer higher than the first wiring layer adjacent to the photodiode among the plurality of wiring layers stacked on the insulating film, and forming the first metal Apply a negative voltage to the electrode.

  According to the embodiment, a solid-state imaging device and a method of forming the same can be provided, for example, which is suitable for preventing deterioration in image quality caused by irradiation of radiation.

FIG. 2 is a diagram showing a basic circuit configuration of a pixel unit used in the CMOS image sensor according to the first embodiment. FIG. 2 is a plan layout view of a basic part of the pixel unit shown in FIG. It is a cross-sectional schematic diagram of the fundamental part of the pixel part shown in FIG. FIG. 5 is a plan layout view of the second wiring layer and below of the pixel portion of the CMOS image sensor according to the first embodiment. FIG. 6 is a plan layout view of a third wiring layer of the pixel portion of the CMOS image sensor according to the first embodiment. FIG. 2 is a schematic cross-sectional view of a pixel portion of the CMOS image sensor according to the first embodiment. FIG. 13 is a plan layout view of the second wiring layer and below of the pixel portion of the CMOS image sensor according to the second embodiment. FIG. 7 is a plan layout view of a third wiring layer of a pixel portion of a CMOS image sensor according to Embodiment 2. FIG. 6 is a schematic cross-sectional view of a pixel portion of a CMOS image sensor according to a second embodiment. It is a cross-sectional schematic diagram of an embedded photodiode. It is a figure for demonstrating the subject at the time of irradiating a radiation to the embedded photodiode shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simplified, the technical scope of the embodiment should not be narrowly interpreted based on the description of the drawings. In addition, the same reference numerals are given to the same elements, and duplicate explanations are omitted.

  In the following embodiments, when it is necessary for the sake of convenience, it will be described by dividing into a plurality of sections or embodiments, but they are not unrelated to each other unless specifically stated otherwise, one is the other And some of all the modifications, applications, detailed explanation, supplementary explanation, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited to a specific number in principle. It is not limited to the specific number except for the number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including the operation steps and the like) are not necessarily essential unless specifically stated and when it is considered to be obviously essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships and the like of components etc., the shapes thereof are substantially the same unless particularly clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes things that are similar or similar to etc. The same applies to the above-described numbers and the like (including the number, the numerical value, the amount, the range, and the like).

<Preliminary examination by inventors>
Before describing the CMOS image sensor (solid-state imaging device) according to the first embodiment, first, a buried photodiode provided in a general surface-illuminated CMOS image sensor will be described.

FIG. 10 is a schematic cross-sectional view of the embedded photodiode.
As shown in FIG. 10, an N-type diffusion region (N ⁻ region) is formed on the surface of a P well formed in a silicon substrate. The N-type diffusion region is formed by doping the surface of the P well with an N-type impurity. Here, a PN junction type photodiode is configured by the P well and the N type diffusion region.

Also, on the surface of the P well, an element isolation region (STI; Shallow Trench Isolation) is formed at a distance from the N-type diffusion region. In addition, a P-type pinning layer is formed on the surface of the active region surrounded by the element isolation region, including the surface of the N-type diffusion region. The pinning layer is formed by doping the surface of the active region surrounded by the element isolation region with a P-type impurity. Furthermore, a SiO ₂ insulating film (PMD; Pre Metal Dielectric) is formed on the surface.

  Among the embedded photodiodes shown in FIG. 10, the ordinary photodiode has no pinning layer, and has a structure in which the surface of the N type diffusion region is directly covered with PMD.

  In a photodiode used for a solid-state imaging device, in general, dark current electrons are generated by thermal excitation in addition to signal electrons excited by an optical signal. The output of this dark current electron is better as it approaches 0, and the increase of the dark current causes the deterioration of the image quality.

  For example, in the case of a normal photodiode having no pinning layer, many dangling bonds and crystal defects are present at the interface between the N-type diffusion region and PMD, so that defect states are generated in the band gap region of the band structure. . As a result, dark current electrons generated by thermal excitation increase and dark current increases. On the other hand, in the case of a buried photodiode having a pinning layer, dark current electrons generated by thermal excitation propagate through the P-type pinning layer and the P well and are swept to ground. As a result, the increase in dark current is suppressed, so that the image quality deterioration is suppressed.

  The pinning layer is not limited to the case where it is formed by doping a P-type impurity on the surface of the active region. The pinning layer may be formed, for example, by applying a negative voltage to the photosensitive region (active region) from the ITO transparent conductive layer formed on the substrate, as disclosed in Patent Document 1 .

  Next, with reference to FIG. 11, a problem in the case where the embedded photodiode shown in FIG. 10 is used in a space, a nuclear facility, a radiation facility or the like will be described.

  As shown in FIG. 11, when radiation such as gamma rays is applied to the embedded photodiode, charge is generated in the insulator PMD due to the ionizing action of the total dose effect generated by the radiation. Among the charges, electrons having a negative charge are swept to the electrode side in a relatively short time because the mobility is high, and disappear at the electrode. On the other hand, positive holes, which have lower mobility than negative charges, are left behind in PMD. The positive charge is gradually swept out of the PMD, but in the process, it is trapped in a defect existing near the interface between the PMD and the silicon substrate to become a fixed positive charge. As described above, when fixed positive charge is generated in the vicinity of the interface between the PMD and the silicon substrate, the P-type pinning layer formed on the surface of the embedded photodiode may be inverted to N-type. In that case, the effect of dark current suppression by the pinning layer may be lost.

  Therefore, the inventors of the present invention have made the CMOS image sensor (solid-state imaging device) according to the first embodiment that can prevent the deterioration of the image quality caused by the irradiation of radiation without losing the function of the pinning layer. I found it.

Embodiment 1
First, the basic configuration of the pixel portion of the surface-illuminated CMOS image sensor (solid-state image sensor) will be described with reference to FIGS. 1, 2 and 3. FIG.

(Basic circuit configuration of pixel unit 1 of CMOS image sensor)
FIG. 1 is a diagram showing a basic circuit configuration of a pixel unit used in the CMOS image sensor according to the first embodiment. The pixel section 1 of the CMOS image sensor shown in FIG. 1 is a pixel section of a typical four-transistor type CMOS image sensor also called a so-called APS (Active Pixel Sensor).

  As shown in FIG. 1, the pixel unit 1 includes four N-channel MOS transistors TR1 to TR4 and a photodiode PD1. Hereinafter, the four N-channel MOS transistors TR1 to TR4 are also referred to as a transfer transistor TR1, a reset transistor TR2, an amplification transistor TR3, and a row selection transistor TR4, respectively.

  The anode of the photodiode PD1 is connected to the ground voltage line GND, and the cathode of the photodiode PD1 is connected to the source of the transfer transistor TR1. In the transfer transistor TR1, the drain (TR1_D) is connected to the node N1, and the gate (TR1_G) is connected to the transfer gate drive line 4 on which the transfer gate drive signal φTG propagates.

  In the reset transistor TR2, the source (TR2_S) is connected to the node N1, the drain (TR2_D) is connected to the power supply voltage line VDD, and the gate (TR2_G) is connected to the reset signal line 5 on which the reset signal φR propagates .

  In the amplification transistor TR3, the source (TR3_S) is connected to the node N2, the drain (TR3_D) is connected to the power supply voltage line VDD, and the gate (TR3_G) is connected to the node N1. That is, the drain of the transfer transistor TR1, the source of the reset transistor TR2, and the gate of the amplification transistor TR3 are connected to each other at the node N1. Further, a floating diffusion layer capacitance FD1 is formed at the node N1.

  In row selection transistor TR4, the source (TR4_S) is connected to output signal line VOUT along with a plurality of other pixels provided in the column direction, the drain is connected to node N2, and the gate (TR4_G) is row selection signal φSEL. Are connected to the propagating row selection signal line 6 of FIG.

  The photodiode PD1 converts the received light signal into an electrical signal. The transfer transistor TR1 is turned on when the transfer gate drive signal φTG becomes active, and transfers the electric signal converted from the light signal by the photodiode PD1 to the node N1. As a result, a charge corresponding to the electrical signal from the photodiode PD1 is accumulated in the floating diffusion layer capacitance FD1 formed at the node N1. The amplification transistor TR3 drives the voltage of the node N1 and outputs it to the node N2. The row selection transistor TR4 turns on when the row selection signal φSEL becomes active, and outputs the voltage of the node N2 (ie, the electrical signal converted from the light signal by the photodiode PD1) to the output signal line VOUT.

(Planar layout view and cross-sectional schematic view of basic portion of pixel unit 1)
FIG. 2 is a plan layout view showing a basic portion of the pixel unit 1 shown in FIG. 1 as a pixel unit 1B. FIG. 3 is a schematic cross-sectional view of the AA ′ portion in the plan layout view shown in FIG.

  As shown in FIG. 2, a rectangular photodiode PD1 is formed in a region that occupies most of the pixel section 1B in plan view, and the metal of the transfer gate driving line 4 is formed so as to surround the outer periphery thereof. .

  Further, four transistors TR1 to TR4 are formed in the peripheral region (upper part of the paper surface of FIG. 2) on one side of the rectangular photodiode PD1 in plan view. Further, in plan view, the ground voltage line GND, the power supply voltage line VDD and the output signal line VOUT are arranged in parallel so as to sandwich the photodiode PD1 and the transistors TR1 to TR4.

  As shown in FIG. 3, an N-type diffusion region 103 is formed on the surface of a P-well 101 formed in a semiconductor substrate 100. The N type diffusion region 103 is formed by doping the surface of the P well 101 with an N type impurity. Here, the P well 101 and the N type diffusion region 103 constitute a PN junction type photodiode PD1.

  In the surface of the P well 101, an element isolation region (STI) 102 is formed spaced apart from the N-type diffusion region 103. A P-type pinning layer 104 is formed on the surface of the active region surrounded by the element isolation region 102 including the surface of the N-type diffusion region 103. The pinning layer 104 is formed by doping the surface of the active region surrounded by the element isolation region 102 with a P-type impurity.

  The outer periphery of the N-type diffusion region 103 (in other words, the outer periphery of the photodiode PD1) is indicated by a dashed dotted line 11 in FIG. Also, the boundary between the element isolation region 102 and the active region surrounded by it is indicated by a solid line 10 in FIG. However, among the boundaries between the element isolation region 102 and the active region surrounded by the device isolation region 102, the boundaries hidden in the wiring layer are indicated by the broken line 10.

  In addition, a P-type diffusion region 105 is formed on the surface of the P well 101 separately from the N-type diffusion region 103. The P type diffusion region 105 is formed by doping the surface of the P well 101 with a P type impurity.

Furthermore, on the surface of the semiconductor substrate 100, a transparent insulating film 106 (not shown) such as SiO ₂ is formed by, eg, CVD (Chemical Vapor Deposition).

  Among the plurality of wiring layers stacked on the insulating film, the metal of the transfer gate driving line 4 described above is a photodiode in plan view in the first wiring layer adjacent (closest to) the semiconductor substrate 100. It is formed so as to surround the outer circumference of the PD 1 (the outer circumference of the N-type diffusion region 103). Thereby, stray light can be prevented from entering the photodiode PD1 from the periphery.

  In the second wiring layer, the ground voltage line GND, the power supply voltage line VDD and the output signal line VOUT described above are arranged in parallel with the photodiode PD1 and the transistors TR1 to TR4 interposed therebetween in plan view. There is. The ground voltage line GND, the power supply voltage line VDD and the output signal line VOUT arranged in the second wiring layer are also referred to as a ground voltage line GND_2, a power supply voltage line VDD_2 and an output signal line VOUT_2, respectively. In the example of FIG. 3, the ground voltage line GND_2 arranged in the second wiring layer is connected to the ground voltage line GND_1 arranged in the first wiring layer via the via V1. The ground voltage line GND_1 arranged in the first wiring layer is connected to the P-type diffusion region 105 via the contact CT1.

(Planar layout view and schematic cross-sectional view of the pixel portion 1 to which the characterizing portion of the present invention is added)
FIG. 4 and FIG. 5 are plan layout views of a configuration in which one of the features of the present invention is added to the basic portion of the pixel section 1 shown in FIG. 4 shows only the first and second wiring layers among the plurality of wiring layers, and FIG. 5 shows only the third wiring layer among the plurality of wiring layers. FIG. 6 is a schematic cross-sectional view of a BB ′ portion in the plan layout views shown in FIGS. 4 and 5.

  As shown in FIGS. 4 to 6, in the pixel portion 1, compared to the pixel portion 1B shown in FIG. 2, the metal electrode MTL is provided in the wiring layer higher than the first wiring layer among the plurality of wiring layers. It is further formed. In this example, metal electrodes MTL_2 and MTL_3 are formed in the second and third wiring layers, respectively, and they are electrically connected by vias V2. A metal electrode MTL is configured by the metal electrodes MTL_2 and MTL_3 and the via V2.

  The metal electrode MTL_2 is formed in a ring shape so as to surround the outer periphery of the photodiode PD1 (the outer periphery of the N-type diffusion region 103) in plan view in the second wiring layer. The metal electrode MTL_3 is formed to surround the outer periphery of the photodiode PD1 (the outer periphery of the N-type diffusion region 103) in plan view in the third wiring layer. Therefore, the light received by the photodiode PD1 is not blocked by the metal electrodes MTL_2 and MTL_3.

  Here, a negative voltage is applied to the metal electrode MTL (metal electrodes MTL_2 and MTL_3). Therefore, even if fixed positive charges are accumulated in the insulating film 106 by the ionizing action of the total dose effect generated by irradiation of radiation such as gamma rays, an electric field is generated in the photodiode PD1 using the negative voltage of the metal electrode MTL. Thus, the influence of the fixed positive charge to which the pinning layer 104 is subjected can be offset. Thereby, since the function of the pinning layer 104 is maintained, the dark current generated by thermal excitation at the interface between the N-type diffusion region 103 and the insulating film 106 is swept to the ground via the pinning layer 104. As a result, the quality deterioration of the image displayed by the pixel unit 1 is suppressed.

  If polysilicon used for the gate electrode of a MOS transistor or the like and a metal formed in the first wiring layer are adopted as the metal electrode MTL, the distance between the metal electrode MTL and the photodiode PD1 becomes too close. It will In this case, an electric field is generated near the periphery near the metal electrode MTL in the formation region of the photodiode PD1 in plan view, but an electric field is hardly generated at the center. Therefore, in the central portion of the photodiode PD1, the influence of the fixed positive charge received by the pinning layer 104 can not be sufficiently offset. This problem becomes more pronounced as the formation region of the photodiode PD1 increases.

  On the other hand, in the pixel unit 1 of the CMOS image sensor according to the present embodiment, the metal formed in the wiring layer higher than the first wiring layer is employed as the metal electrode MTL. As a result, the distance between the metal electrode MTL and the photodiode PD1 is appropriately separated, so that an electric field is generated relatively uniformly not only in the periphery but also in the center of the photodiode PD1 in plan view. Therefore, in the photodiode PD1, the influence of the fixed positive charge received by the pinning layer 104 can be offset over the entire surface. Thus, the pixel unit 1 of the CMOS image sensor according to the present embodiment can cause the pinning layer 104 to function with high accuracy, so that the increase of dark current can be suppressed, and as a result, the deterioration of the image quality is suppressed. can do.

  As described above, in the pixel unit 1 of the CMOS image sensor according to the first embodiment, a negative voltage is applied to surround the outer periphery of the formation region of the photodiode PD1 in plan view in a layer higher than the first wiring layer. The metal electrode MTL is formed. As a result, even if the fixed positive charge is accumulated in the insulating film 106 due to the ionizing action of the total dose effect generated by the radiation, the pixel unit 1 uses the negative voltage of the metal electrode MTL to generate an electric field in the photodiode PD1. The generation can offset the influence of fixed positive charge that the pinning layer 104 receives. Thus, the pixel unit 1 of the CMOS image sensor according to the present embodiment can cause the pinning layer 104 to function with high accuracy, so that the increase of dark current can be suppressed, and as a result, the deterioration of the image quality is suppressed. can do.

  In the pixel portion 1 of the CMOS image sensor according to the present embodiment, since the metal electrode MTL is formed in the wiring layer, unlike the case where the ITO transparent conductive layer is formed as disclosed in Patent Document 1, , No special manufacturing process is required. Therefore, it is possible to suppress the manufacturing problems and the increase in the process cost associated with the addition of the ITO transparent electrode.

  In the present embodiment, the case where the photodiode PD1 has a buried type structure covered in advance with the pinning layer 104 has been described as an example, but the present invention is not limited to this. The photodiode PD1 may have a structure not previously covered with the pinning layer 104. In this case, a P-type diffusion region corresponding to the pinning layer 104 can be formed on the surface of the N-type diffusion region 103 by increasing the negative voltage applied to the metal electrode MTL.

  Further, although the case where the metal electrode MTL is formed across the two wiring layers has been described as an example in the present embodiment, the present invention is not limited to this. The metal electrode MTL may be formed only in one wiring layer higher than the first wiring layer, or may be formed across three or more wiring layers higher than the first wiring layer.

Second Embodiment
7 and 8 are plan layout views of the pixel section 2 of the surface-illuminated CMOS image sensor according to the second embodiment. 7 shows only the first and second wiring layers among the plurality of wiring layers, and FIG. 8 shows only the third wiring layer among the plurality of wiring layers. FIG. 9 is a schematic cross-sectional view of a portion C-C 'in the plan layout views shown in FIGS. 7 and 8.

  As shown in FIGS. 7 to 9, the pixel unit 2 further includes a metal electrode MTL_2a in comparison with the pixel unit 1. The metal electrode MTL_2a is formed to overlap a part of the formation region of the photodiode PD1 in plan view in the second wiring layer. In this example, the metal electrode MTL_2a is formed in a band shape from one side of the metal electrode MTL2 to the other side opposed to the central portion of the formation region of the photodiode PD1 in plan view in the second wiring layer . The metal electrode MTL_2a is electrically connected to the metal electrode MTL_2. Therefore, a negative voltage is also applied to the metal electrode MTL_2a.

  The other structure of the pixel unit 2 is the same as that of the pixel unit 1, and thus the description thereof is omitted.

  As described above, in the pixel unit 2 of the CMOS image sensor according to the second embodiment, a negative voltage is applied to surround the outer periphery of the formation region of the photodiode PD1 in plan view in a layer higher than the first wiring layer. The metal electrode MTL is formed. As a result, even if the fixed positive charge is accumulated in the insulating film 106 due to the ionizing action of the total dose effect generated by the radiation, the pixel unit 2 uses the negative voltage of the metal electrode MTL to generate an electric field in the photodiode PD1. The generation can offset the influence of fixed positive charge that the pinning layer 104 receives. Thus, the pixel unit 2 of the CMOS image sensor according to the present embodiment can cause the pinning layer 104 to function with high accuracy, so that the increase of dark current can be suppressed, and as a result, the deterioration of the image quality is suppressed. can do.

  Furthermore, in the pixel unit 2 of the CMOS image sensor according to the present embodiment, in a layer higher than the first wiring layer, it overlaps with a part (in particular, the central part) of the formation region of the photodiode PD1 in plan view. A metal electrode MTL_2a to which a negative voltage is applied is formed. Thus, the pixel unit 2 can generate a strong electric field not only in the peripheral portion of the top surface of the photodiode PD1 but also in the central portion. That is, the pixel unit 2 can generate an electric field more uniformly over the entire top surface of the photodiode PD1. Thus, the pixel unit 2 can more accurately offset the influence of the fixed positive charge that the pinning layer 104 receives. As a result, the pixel section 2 of the CMOS image sensor according to the present embodiment can function the pinning layer 104 more accurately, and therefore, the increase in dark current can be further suppressed, and as a result, the image quality is degraded. Can be further suppressed.

  In addition, although the case where the metal electrode MTL_2a is provided in addition to the metal electrodes MTL_2 and MTL_3 as the metal electrode MTL has been described in the present embodiment, the present invention is not limited thereto. As the metal electrode MTL, a single metal electrode MTL_2a may be provided. Even in such a case, by forming the metal electrode MTL_2a in the wiring layer higher than the first wiring layer, the distance between the metal electrode MTL_2a and the photodiode PD1 can be appropriately separated, so the photodiode PD1 is formed. An electric field can be generated relatively uniformly over the entire top surface.

  Further, in the present embodiment, the metal electrode MTL_2a is formed so as to overlap with a part of the formation region of the photodiode PD1 in plan view, but the metal electrode MTL_2a has another narrowest wiring width. By setting the width corresponding to the wiring width of the metal wiring (specifically, by setting the minimum size on the process rule), the influence of the reduction in sensitivity of the photodiode PD1 due to light shielding can be minimized.

  Further, in the present embodiment, the metal electrode MTL_2a is formed in a band shape from one side of the formation region of the rectangular photodiode PD1 to the other side opposed in plan view, but the present invention is not limited thereto. The metal electrode MTL_2a may have any shape as long as it can generate an electric field uniformly over the entire upper surface of the photodiode PD1 and can suppress the decrease in sensitivity of the photodiode PD1 due to light shielding within an acceptable range. Good. The metal electrode MTL_2a may be disposed in any wiring layer as long as it is a layer higher than the first wiring layer.

  Furthermore, although the case where the photodiode PD1 has a buried type structure covered in advance with the pinning layer 104 has been described as an example in the present embodiment, the present invention is not limited thereto. The photodiode PD1 may have a structure not previously covered with the pinning layer 104. In this case, a P-type diffusion region corresponding to the pinning layer 104 can be formed on the surface of the N-type diffusion region 103 by increasing the negative voltage applied to the metal electrode MTL.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the embodiment mentioned already, A various change in the range which does not deviate from the gist It goes without saying that it is possible. For example, the conductivity type of each MOS transistor may be replaced with P-type to N-type and N-type to P-type, respectively.

1, 2 Pixel part 1 B Basic part of pixel part 4 Transfer gate drive line 5 Reset signal line 6 Row selection signal line 10 Boundary line between element isolation area and active area surrounded by it 11 Outer periphery of N type diffusion area 100 Semiconductor substrate 101 P well 102 element isolation region 103 N type diffusion region 104 pinning layer 105 P type diffusion region 106 insulating film CT1 contact FD1 floating diffusion capacitance MTL metal electrode MTL_1 metal electrode wired in first layer wire in second layer MTL_2 wire in second layer Metal electrode MTL_2a Additional metal electrode arranged in the second layer N1, N2 Node PD1 Photodiode TR1 Transfer transistor TR2 Reset transistor TR3 Amplifier transistor TR4 Row selection transistor GND Ground voltage line GND_1 Ground wired in the first layer Voltage line GND_2 Ground voltage line wired to the second layer V1, V2 Via VDD Power supply voltage line VDD_2 Power voltage line wired to the second layer VOUT Output signal line VOUT_2 Output signal line wired to the second layer

Claims (14)

A semiconductor substrate,
A PN junction type photodiode formed on the surface of the semiconductor substrate;
An insulating film formed on the surface of the semiconductor substrate including the surface on which the photodiode is formed;
A first metal electrode formed in a wiring layer higher than a first wiring layer adjacent to the photodiode among the plurality of wiring layers stacked on the insulating film and to which a negative voltage is applied;
, A solid-state imaging device. The first metal electrode is formed so as to surround an outer periphery of a formation region of the photodiode in plan view.
The solid-state imaging device according to claim 1. The first metal electrode is
Of the plurality of wiring layers, it is formed in two or more wiring layers higher than the first wiring layer,
The solid-state imaging device according to claim 1. The first metal electrode is
Including vias provided between the two or more wiring layers,
The solid-state imaging device according to claim 3. In a wiring layer higher than the first wiring layer among the plurality of wiring layers, the wiring layer is formed so as to overlap with a part of the formation region of the photodiode in plan view, and electrically connected to the first metal electrode Further comprising a second metal electrode connected in series
The solid-state image sensor as described in any one of Claims 1-4. The second metal electrode is formed to overlap with a central portion of a formation region of the photodiode in plan view.
The solid-state imaging device according to claim 5. The second metal electrode is formed in a band shape from one side of the formation region of the rectangular photodiode in plan view to the other side passing through the central portion and opposed to each other in plan view.
The second metal electrode is formed to have a band width corresponding to the wiring width of the metal wiring having the narrowest wiring width.
The solid-state imaging device according to claim 6. The first metal electrode is formed to overlap a part of the formation region of the photodiode in plan view.
The solid-state imaging device according to claim 1. The first metal electrode is formed to overlap a central portion of a formation region of the photodiode in plan view.
The solid-state imaging device according to claim 8. The first metal electrode is formed in a band shape so as to have a band width corresponding to the wiring width of the other metal wiring having the narrowest wiring width in plan view.
The solid-state imaging device according to claim 9. The photodiode is
A well of one conductivity type formed in the semiconductor substrate;
And a diffusion region of the other conductivity type formed on the well.
The solid-state imaging device according to any one of claims 1 to 10. The photodiode is
A well of one conductivity type formed in the semiconductor substrate;
A diffusion region of the other conductivity type formed on the well;
A conductive pinning layer formed on the surface of the diffusion region;
The solid-state imaging device according to any one of claims 1 to 10. The first wiring layer is further provided with a metal wiring which is formed so as to surround the outer periphery of the formation region of the photodiode in plan view, and which is formed so as to be electrically separated from the first metal electrode.
The solid-state imaging device according to any one of claims 1 to 12. Form a PN junction photodiode on the surface of the semiconductor substrate,
Forming an insulating film on the surface of the semiconductor substrate including the upper surface of the photodiode;
Forming a first metal electrode in a wiring layer higher than a first wiring layer adjacent to the photodiode among the plurality of wiring layers stacked on the insulating film;
Applying a negative voltage to the first metal electrode,
Method of forming a solid-state imaging device

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