JP2010515188A - 電子回路の一時的なロック - Google Patents
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- 238000000034 method Methods 0.000 claims abstract description 25
- 230000002159 abnormal effect Effects 0.000 claims abstract description 11
- 238000007667 floating Methods 0.000 claims description 60
- 230000006870 function Effects 0.000 claims description 23
- 230000015654 memory Effects 0.000 claims description 16
- 238000012795 verification Methods 0.000 claims description 16
- 238000007599 discharging Methods 0.000 claims description 4
- 230000014759 maintenance of location Effects 0.000 description 44
- 230000007246 mechanism Effects 0.000 description 30
- 238000010586 diagram Methods 0.000 description 20
- 238000012545 processing Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 8
- 239000000243 solution Substances 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005672 electromagnetic field Effects 0.000 description 3
- 101100522123 Caenorhabditis elegans ptc-1 gene Proteins 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 206010000117 Abnormal behaviour Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
- G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
- G06Q20/341—Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q20/00—Payment architectures, schemes or protocols
- G06Q20/30—Payment architectures, schemes or protocols characterised by the use of specific devices or networks
- G06Q20/34—Payment architectures, schemes or protocols characterised by the use of specific devices or networks using cards, e.g. integrated circuit [IC] cards or magnetic cards
- G06Q20/357—Cards having a plurality of specified features
- G06Q20/3576—Multiple memory zones on card
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07F—COIN-FREED OR LIKE APPARATUS
- G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
- G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
- G07F7/0806—Details of the card
- G07F7/0813—Specific details related to card security
- G07F7/082—Features insuring the integrity of the data on or in the card
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- G—PHYSICS
- G07—CHECKING-DEVICES
- G07F—COIN-FREED OR LIKE APPARATUS
- G07F7/00—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus
- G07F7/08—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means
- G07F7/10—Mechanisms actuated by objects other than coins to free or to actuate vending, hiring, coin or paper currency dispensing or refunding apparatus by coded identity card or credit card or other personal identification means together with a coded signal, e.g. in the form of personal identification information, like personal identification number [PIN] or biometric data
- G07F7/1008—Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
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Abstract
Description
フローティングノードに接続された第1電極を有する少なくとも1つの第1容量性素子と、
前記フローティングノードに接続された第1電極を有し、前記第1容量性素子の静電容量より大きな静電容量を有する少なくとも1つの第2容量性素子と、
前記フローティングノードに接続され、絶縁された制御端子を有する少なくとも1つの第1トランジスタとを備える。
前記第1容量性素子は、前記フローティングゲート・トランジスタのトンネル窓の誘電体の厚さが他のセルの誘電体の厚さより小さい少なくとも1つの第1セルの第1サブセットを有し、
前記第2容量性素子は、前記フローティングゲート・トランジスタのドレイン及びソースが相互接続されている少なくとも1つの第2セルの第2サブセットを有し、
前記第3容量性素子は、少なくとも1つの第3セルの第3サブセットを有し、
前記第1トランジスタは、そのトンネル窓が除去された少なくとも1つの第4セルの第4サブセットを有する。
静電容量C1: 2fF、誘電体の厚さ: 40Å
静電容量C2: 20fF、誘電体の厚さ: 160Å
静電容量C3: 1fF、誘電体の厚さ: 80Å
VPP1は、VPP2より大きい。
VSELは、VREAD より大きい。
VREAD は、V114と同程度の大きさである。
実施形態の具体例によれば、
VPP1 = 14ボルト
VPP2 = 12ボルト
VSEL = 4ボルト
VREAD = 2ボルト
V114 = 1ボルト
数個の素子C2が、電子回路の放電時間を増加させるべくフローティングノードF の静電容量を増加させるために並列接続して用いられてもよく、
数個の素子170 が、プログラミング中のフローティングノードF での充電速度又は放電速度を増加させるべく並列接続して用いられてもよく、
数個のリーク素子C1が、システムの放電時間を減少させるために並列接続して用いられてもよく、及び/又は
数個の読み取り素子160 が、電荷保持回路の評価に更に大きな電流を与えるために並列接続して導入されてもよい。
Claims (10)
- 電子回路(10') に含まれる少なくとも1つの情報を、前記電子回路の異常動作が閾値より多い回数であると検出された場合に、前記電子回路の少なくとも1つの機能を無効化することにより保護する方法において、
前記機能の無効化は、一時的であり、前記電子回路に電力が供給されているか否かに無関係に、所定の継続時間行われて、前記機能の無効化の継続時間は、その誘電性空間を介してリークを示す少なくとも1つの第1容量性素子(C1)を備えた少なくとも1つの電荷保持回路(100) によって設定されることを特徴とする方法。 - 前記機能の無効化は、前記第1容量性素子(C1)への充電又は前記第1容量性素子からの放電により引き起こされることを特徴とする請求項1に記載の方法。
- 異常動作は、保護されるべき情報を用いた認証の試行の失敗であることを特徴とする請求項1に記載の方法。
- 認証コードの付与による前記電子回路(10') のユーザ認証に適用されることを特徴とする請求項3に記載の方法。
- 署名の照合による前記電子回路(10') によって受信されたデータの認証に適用されることを特徴とする請求項3に記載の方法。
- 前記電子回路(10') の動作の無効化の継続時間は、1時間乃至1週間であることを特徴とする請求項1に記載の方法。
- 請求項1に記載の方法を実行するための手段を備えることを特徴とする電子回路(10') 。
- 前記一又は複数の電荷保持回路は、
フローティングノード(F) に接続された第1電極(121) を有する少なくとも1つの第1容量性素子(C1)と、
前記フローティングノード(F) に接続された第1電極(131) を有し、前記第1容量性素子の静電容量より大きな静電容量を有する少なくとも1つの第2容量性素子(C2)と、
前記フローティングノードに接続され、絶縁された制御端子を有する少なくとも1つの第1トランジスタ(150,160) と
を備えることを特徴とする請求項7に記載の電子回路。 - 少なくとも1つの第3容量性素子(C3,170)が、前記フローティングノード(F) に接続された第1電極(141) と、電圧源に接続可能な第2電極(142) とを有することを特徴とする請求項8に記載の電子回路。
- EEPROMタイプの複数のメモリセルのネットワークに埋め込まれており、各メモリセルが、フローティングゲート・トランジスタと直列の選択トランジスタを備えており、前記トランジスタの夫々のフローティングゲートが相互接続されている前記メモリセルの同一列では、
前記第1容量性素子は、前記フローティングゲート・トランジスタのトンネル窓の誘電体(212) の厚さが他のセルの誘電体の厚さより小さい少なくとも1つの第1セル(C1)の第1サブセットを有し、
前記第2容量性素子は、前記フローティングゲート・トランジスタのドレイン及びソースが相互接続されている少なくとも1つの第2セル(C2)の第2サブセットを有し、
前記第3容量性素子は、少なくとも1つの第3セル(170) の第3サブセットを有し、
前記第1トランジスタは、そのトンネル窓が除去された少なくとも1つの第4セル(160) の第4サブセットを有することを特徴とする請求項9に記載の電子回路。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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FR0752553 | 2007-01-05 | ||
FR0752553 | 2007-01-05 | ||
PCT/EP2008/050074 WO2008084018A1 (fr) | 2007-01-05 | 2008-01-04 | Verrouillage temporaire d'un circuit electronique |
Publications (2)
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JP2010515188A true JP2010515188A (ja) | 2010-05-06 |
JP4882007B2 JP4882007B2 (ja) | 2012-02-22 |
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JP2009544416A Active JP4882007B2 (ja) | 2007-01-05 | 2008-01-04 | 電子回路の一時的なロック |
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US (1) | US9036414B2 (ja) |
EP (1) | EP2108165A1 (ja) |
JP (1) | JP4882007B2 (ja) |
CN (1) | CN101606162A (ja) |
WO (1) | WO2008084018A1 (ja) |
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US8566931B2 (en) * | 2007-01-05 | 2013-10-22 | Proton World International N.V. | Protection of information contained in an electronic circuit |
WO2010056438A2 (en) * | 2008-11-13 | 2010-05-20 | Proteus Biomedical, Inc. | Shielded stimulation and sensing system and method |
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US8566931B2 (en) * | 2007-01-05 | 2013-10-22 | Proton World International N.V. | Protection of information contained in an electronic circuit |
EP2108164B1 (fr) * | 2007-01-05 | 2015-08-26 | Proton World International N.V. | Limitation d'acces a une ressource d'un circuit electronique |
JP5570455B2 (ja) * | 2011-02-16 | 2014-08-13 | オムロンオートモーティブエレクトロニクス株式会社 | 漏電検知装置 |
JP5710307B2 (ja) * | 2011-02-16 | 2015-04-30 | オムロンオートモーティブエレクトロニクス株式会社 | 漏電検知装置 |
-
2008
- 2008-01-04 JP JP2009544416A patent/JP4882007B2/ja active Active
- 2008-01-04 CN CNA200880001701XA patent/CN101606162A/zh active Pending
- 2008-01-04 WO PCT/EP2008/050074 patent/WO2008084018A1/fr active Application Filing
- 2008-01-04 EP EP08701254A patent/EP2108165A1/fr not_active Withdrawn
- 2008-01-04 US US12/521,773 patent/US9036414B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108431848A (zh) * | 2015-12-11 | 2018-08-21 | 万事达卡国际公司 | 交易的委托 |
JP2019502204A (ja) * | 2015-12-11 | 2019-01-24 | マスターカード インターナシヨナル インコーポレーテツド | トランザクションの代理 |
Also Published As
Publication number | Publication date |
---|---|
EP2108165A1 (fr) | 2009-10-14 |
US20110007567A1 (en) | 2011-01-13 |
WO2008084018A1 (fr) | 2008-07-17 |
CN101606162A (zh) | 2009-12-16 |
US9036414B2 (en) | 2015-05-19 |
JP4882007B2 (ja) | 2012-02-22 |
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