JP2010508167A - マイクロマシンデバイスの製造方法 - Google Patents

マイクロマシンデバイスの製造方法 Download PDF

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Publication number
JP2010508167A
JP2010508167A JP2009535072A JP2009535072A JP2010508167A JP 2010508167 A JP2010508167 A JP 2010508167A JP 2009535072 A JP2009535072 A JP 2009535072A JP 2009535072 A JP2009535072 A JP 2009535072A JP 2010508167 A JP2010508167 A JP 2010508167A
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JP
Japan
Prior art keywords
layer
forming
protective layer
substrate
micromachine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009535072A
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English (en)
Japanese (ja)
Other versions
JP2010508167A5 (https=
Inventor
アン・ウィトフルーウ
リュック・ハスペスラーフフ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
ASML Netherlands BV
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
ASML Netherlands BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC, ASML Netherlands BV filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of JP2010508167A publication Critical patent/JP2010508167A/ja
Publication of JP2010508167A5 publication Critical patent/JP2010508167A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
    • B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24479—Structurally defined web or sheet [e.g., overall dimension, etc.] including variation in thickness
    • Y10T428/24612—Composite web or sheet

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2009535072A 2006-10-31 2007-10-31 マイクロマシンデバイスの製造方法 Pending JP2010508167A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US86367906P 2006-10-31 2006-10-31
EP2007061558 2007-10-26
PCT/EP2007/061731 WO2008053008A2 (en) 2006-10-31 2007-10-31 Method for manufacturing a micromachined device

Publications (2)

Publication Number Publication Date
JP2010508167A true JP2010508167A (ja) 2010-03-18
JP2010508167A5 JP2010508167A5 (https=) 2011-09-15

Family

ID=39273064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009535072A Pending JP2010508167A (ja) 2006-10-31 2007-10-31 マイクロマシンデバイスの製造方法

Country Status (3)

Country Link
US (1) US20100062224A1 (https=)
JP (1) JP2010508167A (https=)
WO (1) WO2008053008A2 (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7557433B2 (en) 2004-10-25 2009-07-07 Mccain Joseph H Microelectronic device with integrated energy source
EP1801067A3 (en) * 2005-12-21 2012-05-09 Imec Method for forming silicon germanium layers at low temperatures for controlling stress gradient
EP2183743A1 (en) 2007-08-29 2010-05-12 Imec Method for formation of tips
US8487386B2 (en) * 2009-06-18 2013-07-16 Imec Method for forming MEMS devices having low contact resistance and devices obtained thereof
US20130001550A1 (en) * 2011-06-29 2013-01-03 Invensense, Inc. Hermetically sealed mems device with a portion exposed to the environment with vertically integrated electronics
US8647977B2 (en) * 2011-08-17 2014-02-11 Micron Technology, Inc. Methods of forming interconnects
US9580776B2 (en) 2011-09-30 2017-02-28 Intel Corporation Tungsten gates for non-planar transistors
EP2761664A4 (en) * 2011-09-30 2015-06-17 Intel Corp CLOSING DIELECTRIC STRUCTURES FOR TRANSISTOR GATES
WO2013048524A1 (en) 2011-10-01 2013-04-04 Intel Corporation Source/drain contacts for non-planar transistors
CN104053626B (zh) 2011-10-28 2017-06-30 意法半导体股份有限公司 用于制造针对氢氟酸蚀刻的保护层的方法、设置有该保护层的半导体器件及制造该半导体器件的方法
ITTO20120834A1 (it) * 2012-09-26 2014-03-27 St Microelectronics Srl Sensore inerziale con strato di protezione da attacco e relativo metodo di fabbricazione
WO2015077324A1 (en) * 2013-11-19 2015-05-28 Simpore Inc. Free-standing silicon oxide membranes and methods of making and using same
US10553492B2 (en) * 2018-04-30 2020-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Selective NFET/PFET recess of source/drain regions
US11699623B2 (en) 2020-10-14 2023-07-11 Applied Materials, Inc. Systems and methods for analyzing defects in CVD films
IT202100022511A1 (it) 2021-08-30 2023-03-02 St Microelectronics Srl Procedimento di fabbricazione di un sistema integrato includente un sensore di pressione capacitivo e un sensore inerziale, e sistema integrato

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004358654A (ja) * 2003-06-03 2004-12-24 Hewlett-Packard Development Co Lp Ｍｅｍｓ素子およびｍｅｍｓ素子を形成する方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851370A (en) * 1987-12-28 1989-07-25 American Telephone And Telegraph Company, At&T Bell Laboratories Fabricating a semiconductor device with low defect density oxide
US5007982A (en) * 1988-07-11 1991-04-16 North American Philips Corporation Reactive ion etching of silicon with hydrogen bromide
US7176111B2 (en) * 1997-03-28 2007-02-13 Interuniversitair Microelektronica Centrum (Imec) Method for depositing polycrystalline SiGe suitable for micromachining and devices obtained thereof
AU3346000A (en) * 1999-01-15 2000-08-01 Regents Of The University Of California, The Polycrystalline silicon germanium films for forming micro-electromechanical systems
US6346459B1 (en) * 1999-02-05 2002-02-12 Silicon Wafer Technologies, Inc. Process for lift off and transfer of semiconductor devices onto an alien substrate
US6599814B1 (en) * 1999-05-03 2003-07-29 Interuniversitair Microelektronica Centrum (Imec) Method for removal of sic
US6822304B1 (en) * 1999-11-12 2004-11-23 The Board Of Trustees Of The Leland Stanford Junior University Sputtered silicon for microstructures and microcavities
US20040157426A1 (en) * 2003-02-07 2004-08-12 Luc Ouellet Fabrication of advanced silicon-based MEMS devices
EP1482069A1 (en) * 2003-05-28 2004-12-01 Interuniversitair Microelektronica Centrum Vzw Method for producing polycrystalline silicon germanium suitable for micromachining
JP4191000B2 (ja) * 2003-10-06 2008-12-03 エルピーダメモリ株式会社 半導体装置及びその製造方法
TWI366218B (en) * 2004-06-01 2012-06-11 Semiconductor Energy Lab Method for manufacturing semiconductor device
US7557027B2 (en) * 2005-01-24 2009-07-07 Interuniversitair Microelektronica Centrum Method of producing microcystalline silicon germanium suitable for micromachining
KR100689826B1 (ko) * 2005-03-29 2007-03-08 삼성전자주식회사 불소 함유된 화학적 식각 가스를 사용하는 고밀도 플라즈마화학기상증착 방법들 및 이를 채택하여 반도체 소자를제조하는 방법들
EP1801067A3 (en) * 2005-12-21 2012-05-09 Imec Method for forming silicon germanium layers at low temperatures for controlling stress gradient

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004358654A (ja) * 2003-06-03 2004-12-24 Hewlett-Packard Development Co Lp Ｍｅｍｓ素子およびｍｅｍｓ素子を形成する方法

Also Published As

Publication number Publication date
WO2008053008A2 (en) 2008-05-08
WO2008053008A3 (en) 2008-06-19
US20100062224A1 (en) 2010-03-11

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