JP2010505195A5 - - Google Patents

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Publication number
JP2010505195A5
JP2010505195A5 JP2009530492A JP2009530492A JP2010505195A5 JP 2010505195 A5 JP2010505195 A5 JP 2010505195A5 JP 2009530492 A JP2009530492 A JP 2009530492A JP 2009530492 A JP2009530492 A JP 2009530492A JP 2010505195 A5 JP2010505195 A5 JP 2010505195A5
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JP
Japan
Prior art keywords
cache
data
effective address
display instruction
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009530492A
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English (en)
Japanese (ja)
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JP2010505195A (ja
Filing date
Publication date
Priority claimed from US11/536,085 external-priority patent/US7555605B2/en
Application filed filed Critical
Publication of JP2010505195A publication Critical patent/JP2010505195A/ja
Publication of JP2010505195A5 publication Critical patent/JP2010505195A5/ja
Pending legal-status Critical Current

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JP2009530492A 2006-09-28 2007-07-19 キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法 Pending JP2010505195A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/536,085 US7555605B2 (en) 2006-09-28 2006-09-28 Data processing system having cache memory debugging support and method therefor
PCT/US2007/073833 WO2008042494A2 (en) 2006-09-28 2007-07-19 Data processing system having cache memory debugging support and method therefor

Publications (2)

Publication Number Publication Date
JP2010505195A JP2010505195A (ja) 2010-02-18
JP2010505195A5 true JP2010505195A5 (OSRAM) 2010-09-09

Family

ID=39262339

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009530492A Pending JP2010505195A (ja) 2006-09-28 2007-07-19 キャッシュ・メモリ・デバッグ・サポートを有するデータ処理システムおよびそのための方法

Country Status (4)

Country Link
US (3) US7555605B2 (OSRAM)
EP (1) EP2074510A4 (OSRAM)
JP (1) JP2010505195A (OSRAM)
WO (1) WO2008042494A2 (OSRAM)

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US20090006803A1 (en) * 2007-06-28 2009-01-01 David Arnold Luick L2 Cache/Nest Address Translation
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CN103946813B (zh) 2011-09-30 2017-08-25 英特尔公司 基于使用统计量追踪的远存储器访问信号的生成
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EP3712774B1 (en) 2011-09-30 2023-02-15 Tahoe Research, Ltd. Apparatus and method for implementing a multi-level memory hierarchy
US9317429B2 (en) 2011-09-30 2016-04-19 Intel Corporation Apparatus and method for implementing a multi-level memory hierarchy over common memory channels
US10372590B2 (en) 2013-11-22 2019-08-06 International Business Corporation Determining instruction execution history in a debugger
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