JP2010502009A - フィン電界効果トランジスタを製造するためのシステムと方法 - Google Patents
フィン電界効果トランジスタを製造するためのシステムと方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 84
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 230000005669 field effect Effects 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 125000006850 spacer group Chemical group 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 238000000206 photolithography Methods 0.000 claims abstract description 7
- 230000008569 process Effects 0.000 claims description 21
- 239000003989 dielectric material Substances 0.000 claims description 5
- KIENCNBXSPQMBA-UHFFFAOYSA-N [Si](O)(O)(O)O.C(C)[Si](CC)(CC)CC Chemical compound [Si](O)(O)(O)O.C(C)[Si](CC)(CC)CC KIENCNBXSPQMBA-UHFFFAOYSA-N 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 description 20
- 239000000463 material Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000009499 grossing Methods 0.000 description 5
- 238000002360 preparation method Methods 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 241000699670 Mus sp. Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 235000019504 cigarettes Nutrition 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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- H01L29/772—Field effect transistors
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Abstract
Description
減らすことが望ましい。
スフローを記載する。デバイスとプロセスフローの観点からこの実施形態を扱う前に、本技法の実施形態に従う例示的なシステムが記載される。
易にするために、電気的結合のための機構を提供する。図3の実施形態は様々な標準規格に従って利用され得る。例えば、メモリモジュール52は、シングルデータレート(SDR)、完全バッファ型(FB)-DIMM、ダブルデータレート(DDR)、およびダブルデータレート2(DDR2)システム10で利用されてもよい。
グラフィーマスクはおよそ200以下の幅とおよそ1500以上の長さを持つ壁166を画定し得る。フォトリソグラフィーマスクが適用された後、技法102は、ブロック138で示されるように、壁166を形成するために窒化物層164とPADOX 162をエッチングすることを含み得る。一実施形態では、窒化物層とPADOX 162のエッチングは、活性イオンエッチングもしくは他の適切な形の異方性エッチングなどの、in situエッチングを行うことを含み得る。あるいは、他の適切な形の湿式エッチングと乾式エッチングが利用されてもよい。加えて、いくつかの実施形態では、技法102は、窒化物層164とPADOX 162のエッチングと同時に基板160の一部分を通るエッチングも含み得る。例えば、一実施形態では、技法102は、壁166よりも下ではない領域において、基板160からおよそ200Åエッチングすることを含み得る。エッチングが完了した後、技法102は、ブロック140で示されるようにフォトリソグラフィーマスクを除去することを含み得る。ブロック140の後に形成される半導体構造の一実施形態は図6に図示される。
Claims (21)
- 基板の上に窒化物の層を堆積するステップと、
壁の位置を画定するために前記窒化物の層の上にフォトリソグラフィーマスクを配置するステップと、
前記壁を作るために前記窒化物の層をエッチングするステップと、
前記フォトリソグラフィーマスクを除去するステップと、
前記壁に隣接するスペーサー層を堆積するステップと、
前記壁に隣接するスペーサーを作るために前記スペーサー層をエッチングし、前記スペーサーと前記壁は前記基板の第一の部分を覆う、ステップと、
トレンチを作るために、前記スペーサーによって覆われていない前記基板の第二の部分をエッチングするステップと、
を含む方法。 - 前記スペーサー層を堆積するステップは、オルトケイ酸テトラエチルシリコンの層を堆積するステップを含む、請求項1に記載の方法。
- 前記トレンチを誘電材料で充填するステップを含む、請求項1に記載の方法。
- 前記トレンチを充填するステップは、前記トレンチをスピンオン誘電体で充填するステップを含む、請求項3に記載の方法。
- 前記基板の前記第一の部分の一部を露出するために、前記窒化物の層をエッチングするステップを含む、請求項3に記載の方法。
- チャネルを作るために、前記基板の前記第一の部分の前記露出された部分をある深さまでエッチングするステップを含む、請求項5に記載の方法。
- 前記誘電材料を前記基板とおおよそ同じ深さまでエッチングするステップを含む、請求項6に記載の方法。
- 前記誘電材料を前記基板とおおよそ同じ深さまでエッチングするステップは、フィンを作るステップを含む、請求項7に記載の方法。
- 前記フィンを作るステップは、前記基板の上面より下に埋め込まれたフィンを作るステップを含む、請求項8に記載の方法。
- 前記誘電材料を前記基板とおおよそ同じ深さまでエッチングするステップは、第一のフィンと第二のフィンを作るステップを含む、請求項7に記載の方法。
- 前記基板の前記第一の部分の前記露出された部分をエッチングするステップは、前記第一のフィンの第一の壁と、前記第二のフィンの第一の壁を作るステップを含む、請求項7に記載の方法。
- 前記基板上に堆積されたゲートを形成するステップを含む、請求項7に記載の方法。
- フィンの上にゲートを形成するステップを含む、請求項7に記載の方法。
- フォトリソグラフィーマスクを使用せずに、フィンの第一の壁を作るために第一のエッチングを行うステップと、
前記フィンの第二の壁を作るために第二のエッチングを行うステップと、
前記フィンの上にゲートを堆積し、前記ゲートは前記第二のエッチングの後に堆積される、ステップと、
を含む、フィンとゲートを含むトランジスタの製造方法。 - 前記第一のエッチングを行うステップは、基板の上面よりも下に埋め込まれた前記フィンの前記第一の壁を作るステップを含む、請求項14に記載の方法。
- 前記方法は単一ゲートを含むトランジスタを製造するステップを含む、請求項14に記載の方法。
- 前記第一のエッチングを行うステップは、別のフィンの第一の壁を作る、請求項14に記載の方法。
- 基板内のトレンチと、
エッチングプロセスによって形成されるチャネルを含む、前記トレンチによって部分的に画定される前記基板からの露出部と、
前記トレンチの第一の側面上の前記露出部の上面の上に配列された第一のスペーサーと、
前記トレンチの第二の側面上の前記露出部の前記上面の上に配列された第二のスペーサーとを含み、
前記第一のスペーサーと前記第二のスペーサーは前記エッチングプロセス中に前記露出部をマスクするように構成される、
構造。 - 前記チャネルはフィンの壁を画定する、請求項18に記載の構造。
- 前記第一のスペーサーはオルトケイ酸テトラエチルシリコンを含む、請求項18に記載の構造。
- 前記露出部の前記上面は、前記基板の前記上面より下に埋め込まれる、請求項18に記載の構造。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/508,047 US7745319B2 (en) | 2006-08-22 | 2006-08-22 | System and method for fabricating a fin field effect transistor |
US11/508,047 | 2006-08-22 | ||
PCT/US2007/017571 WO2008024200A1 (en) | 2006-08-22 | 2007-08-07 | System and method for fabricating a fin field effect transistor |
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JP2010502009A true JP2010502009A (ja) | 2010-01-21 |
JP5299703B2 JP5299703B2 (ja) | 2013-09-25 |
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US9281402B2 (en) | 2016-03-08 |
US20100252886A1 (en) | 2010-10-07 |
WO2008024200A1 (en) | 2008-02-28 |
KR20090042275A (ko) | 2009-04-29 |
CN101506957B (zh) | 2015-11-25 |
CN101506957A (zh) | 2009-08-12 |
US8748280B2 (en) | 2014-06-10 |
TWI352394B (en) | 2011-11-11 |
KR101064467B1 (ko) | 2011-09-15 |
US20080050885A1 (en) | 2008-02-28 |
US8076721B2 (en) | 2011-12-13 |
US7745319B2 (en) | 2010-06-29 |
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