JP2010258301A - インターポーザ及び半導体装置 - Google Patents

インターポーザ及び半導体装置 Download PDF

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Publication number
JP2010258301A
JP2010258301A JP2009108269A JP2009108269A JP2010258301A JP 2010258301 A JP2010258301 A JP 2010258301A JP 2009108269 A JP2009108269 A JP 2009108269A JP 2009108269 A JP2009108269 A JP 2009108269A JP 2010258301 A JP2010258301 A JP 2010258301A
Authority
JP
Japan
Prior art keywords
interposer
connection terminal
chip
wiring board
chip component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009108269A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010258301A5 (enExample
Inventor
Eiji Takaike
英次 高池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2009108269A priority Critical patent/JP2010258301A/ja
Publication of JP2010258301A publication Critical patent/JP2010258301A/ja
Publication of JP2010258301A5 publication Critical patent/JP2010258301A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2009108269A 2009-04-27 2009-04-27 インターポーザ及び半導体装置 Pending JP2010258301A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009108269A JP2010258301A (ja) 2009-04-27 2009-04-27 インターポーザ及び半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009108269A JP2010258301A (ja) 2009-04-27 2009-04-27 インターポーザ及び半導体装置

Publications (2)

Publication Number Publication Date
JP2010258301A true JP2010258301A (ja) 2010-11-11
JP2010258301A5 JP2010258301A5 (enExample) 2012-04-12

Family

ID=43318855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009108269A Pending JP2010258301A (ja) 2009-04-27 2009-04-27 インターポーザ及び半導体装置

Country Status (1)

Country Link
JP (1) JP2010258301A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014212183A (ja) * 2013-04-18 2014-11-13 大日本印刷株式会社 貫通電極基板の製造方法、貫通電極基板、および半導体装置
US10806033B2 (en) 2017-10-03 2020-10-13 Murata Manufacturing Co., Ltd. Interposer and electronic device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03501426A (ja) * 1988-08-01 1991-03-28 サーキット・コンポーネンツ・インコーポレイテッド 高誘電率の軟質シート材料
JPH1074668A (ja) * 1996-08-30 1998-03-17 Rohm Co Ltd アレイ型固体電解コンデンサの構造及びその製造方法
JP2001352004A (ja) * 2000-06-09 2001-12-21 Fujitsu Ltd 回路基板及びその製造方法並びに半導体装置
JP2005150490A (ja) * 2003-11-18 2005-06-09 Canon Inc Ｉｃとプリント配線基板間のシート部品
JP2005236008A (ja) * 2004-02-19 2005-09-02 Fujitsu Ltd コンデンサシート
JP2009049087A (ja) * 2007-08-16 2009-03-05 Panasonic Corp 電子部品と電子部品の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03501426A (ja) * 1988-08-01 1991-03-28 サーキット・コンポーネンツ・インコーポレイテッド 高誘電率の軟質シート材料
JPH1074668A (ja) * 1996-08-30 1998-03-17 Rohm Co Ltd アレイ型固体電解コンデンサの構造及びその製造方法
JP2001352004A (ja) * 2000-06-09 2001-12-21 Fujitsu Ltd 回路基板及びその製造方法並びに半導体装置
JP2005150490A (ja) * 2003-11-18 2005-06-09 Canon Inc Ｉｃとプリント配線基板間のシート部品
JP2005236008A (ja) * 2004-02-19 2005-09-02 Fujitsu Ltd コンデンサシート
JP2009049087A (ja) * 2007-08-16 2009-03-05 Panasonic Corp 電子部品と電子部品の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014212183A (ja) * 2013-04-18 2014-11-13 大日本印刷株式会社 貫通電極基板の製造方法、貫通電極基板、および半導体装置
US10806033B2 (en) 2017-10-03 2020-10-13 Murata Manufacturing Co., Ltd. Interposer and electronic device

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