JP2010251668A - Semiconductor integrated circuit which has wiring peeling preventing structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To fabricate a peeling preventing structure for a wiring layer without increasing a chip area of a semiconductor integrated circuit, thereby preventing wiring from being cut off by a stress applied to the chip. <P>SOLUTION: The semiconductor integrated circuit includes metal wiring layers 202 to 205 in peripheral portions of a semiconductor integrated circuit chip having a multilayer wiring structure. through-holes for connecting the metal wiring layers, or contact holes for electrically connecting the lowermost metal wiring layer to elements formed on the substrate, are arranged on the metal wiring layers respectively in a concentrated manner so that a region 101 where the through-holes are formed right above the metal wiring layers, and that a region 102 where the through-holes or the contact holes are formed right below the metal wiring layers do not overlap each other in the face of the substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly, to an integrated circuit chip composed of a plurality of wiring layers, and a structure for preventing wiring from being cut by stress applied to the chip.

  In current semiconductor integrated circuit design, a multilayer wiring structure having a plurality of wiring layers for connecting active elements or passive elements on a semiconductor substrate is used because of demands for miniaturization and high-speed operation. Each of the plurality of wiring layers is separated and formed by an interlayer insulating film, and connection between the wiring layers is made by a through hole penetrating the interlayer insulating film. Examples of the material for the interlayer insulating film that separates the wiring layers include an inorganic oxide dielectric material such as a silicon oxide film. Recently, in order to suppress the wiring delay, an organic polymer material or a porous material having a low dielectric constant is used instead of the conventional inorganic oxide dielectric material.

  However, due to stress applied to the chip during the manufacturing process or reliability test, the multilayer film may be peeled off at the interface between the interlayer insulating film and the wiring layer, and a crack may occur between the wiring layers. In particular, the low dielectric constant material generally has a considerably lower adhesive strength than conventional inorganic oxide dielectric materials, and has a large difference in elastic modulus and thermal expansion coefficient. Therefore, due to mechanical stress and thermal stress, Peeling occurs at the interface of the low dielectric interlayer insulating film, and cracks are likely to occur between the wiring layers.

  In order to prevent the above-described peeling, as shown in FIG. 5, the conductive pads 501 formed of multiple layers are connected by a metal wiring layer to form a mesh-like wiring pattern 502, and further conductive vias (through holes and contact holes). Is disclosed in Patent Document 1 in which a structure in which a structure) is formed in a region 503 in a conductive pad is disposed in a peripheral portion of a chip. FIG. 6 is a cross-sectional view of the structure as viewed from side A in FIG. 5. The wiring layers 202 to 205 are connected to each other through through holes 210 to 212 provided in the interlayer insulating films 206 to 208. In addition, the formation regions of the through holes 210 to 212 and the contact holes 213 formed above and below are overlapped to form a peeling prevention structure, thereby preventing the wiring layer from peeling and cracking.

  Patent Document 2 is a patent relating to a method for manufacturing a multilayer wiring structure.

JP 2003-243401 A JP 2003-347299 A

  In the conventional example shown in FIGS. 5 and 6, since it is necessary to arrange the peeling prevention structure in a region different from the wiring, the region where the peeling prevention structure is arranged is restricted, and the chip is formed by reducing the area of other circuit portions. The effect of reducing the overall area is diminished.

  Furthermore, in the conventional example, through holes connecting the wiring layers from the uppermost layer to the lowermost layer are formed in the conductive pad region formed in each wiring layer so as to overlap in a direction perpendicular to the substrate surface. The through hole formed in the upper portion may become unstable when the flatness of the lower wiring layer and insulating layer is insufficient. This is because, as the wiring becomes multi-layered, variations in the multi-layered film formation process are added, resulting in a very wavy (uneven, unstable) film structure. It becomes a problem.

  The present invention has been made in view of the above problems, and an object of the present invention is to prevent disconnection of wiring due to chip stress without increasing the chip area in a semiconductor integrated circuit using a multilayer wiring structure. Another object of the present invention is to provide a wiring layer peeling prevention structure.

  A semiconductor integrated circuit according to the present invention has three or more wiring layers, and includes an interlayer insulating film that electrically insulates between the wiring layers and the lowermost wiring layer and the substrate, and between the wiring layers. A through hole that penetrates through the interlayer insulating film and electrically connects adjacent wiring layers through the interlayer insulating film, and a lowermost wiring layer that penetrates through the interlayer insulating film on the substrate In a semiconductor integrated circuit in which a multilayer wiring structure is formed by a contact hole that electrically connects an active element or a passive element on the substrate to each other, the wiring layer includes at least three wiring layers adjacent to each other via the interlayer insulating film. Each of the peeling prevention wiring layers has a first region overlapping in a direction perpendicular to the substrate surface, and the plurality of through holes are concentrated in each of the interlayer insulating films between the peeling prevention wiring layers in the first region. Shi A second region having a single closed contour line is formed, and each of the peeling prevention wiring layers except the uppermost layer and the lowermost layer penetrates the interlayer insulating film immediately above the peeling prevention wiring layer. The second region in which the through hole is formed overlaps the second region in which the through hole penetrating the interlayer insulating film directly below is formed in a direction perpendicular to the substrate surface, and the peeling prevention wiring layer Each region in the second region where the through hole penetrating the interlayer insulating film immediately above is formed in the second region where the through hole penetrating the interlayer insulating film immediately below is formed. A first feature is that each of the plurality of regions has a wiring peeling prevention structure that does not overlap in a direction perpendicular to the substrate surface.

  Furthermore, in addition to the first feature, the semiconductor integrated circuit according to the present invention includes the peeling prevention wiring layer including the lowermost wiring layer, and the interlayer insulating film immediately above the lowermost peeling prevention wiring layer. In the second region in which the through-hole penetrating the substrate is formed, a plurality of the contact holes penetrating the interlayer insulating film on the substrate are formed in a concentrated manner, and the contact holes are formed in a concentrated manner. It is second that each region does not overlap each of the plurality of regions in the second region where the through hole is formed immediately above the lowermost peeling prevention wiring layer in a direction perpendicular to the substrate surface. It is characterized by.

  The semiconductor integrated circuit according to the present invention includes a plurality of wiring layers, an interlayer insulating film that electrically insulates between the wiring layers and the lowermost wiring layer and the substrate, and between the wiring layers. A through hole that penetrates through the interlayer insulating film and electrically connects adjacent wiring layers through the interlayer insulating film, and a lowermost wiring layer that penetrates through the interlayer insulating film on the substrate In a semiconductor integrated circuit in which a multilayer wiring structure is formed by a contact hole that electrically connects an active element or a passive element on the substrate and the uppermost layer of the wiring layer adjacent thereto via the interlayer insulating film Each of the two anti-peeling wiring layers of the wiring layer has a first region overlapping in a direction perpendicular to the substrate surface, and a plurality of interlayer insulating films between the anti-peeling wiring layers are provided in the first region. Of the above A plurality of contact holes penetrating through the interlayer insulating film on the substrate are concentrated in the second region. The individual regions formed by concentrating the contact holes do not overlap each of the plurality of regions in the second region where the through holes are formed in a direction perpendicular to the substrate surface. A third feature is that it has a wiring peeling prevention structure.

  Furthermore, in addition to any of the second or third features, the semiconductor integrated circuit according to the present invention penetrates the interlayer insulating film on the substrate in the second region in the wiring peeling prevention structure. A fourth feature is that each of the contact holes is two-dimensionally arranged with an interval equal to or larger than the diameter of the contact hole.

  Furthermore, in addition to any one of the first to fourth features, the semiconductor integrated circuit according to the present invention has the interlayer insulating film between the peeling prevention wiring layers in each second region in the wiring peeling prevention structure. The fifth feature is that each of the through-holes penetrating through the two-dimensionally is arranged two-dimensionally with an interval larger than the diameter of the through-hole.

  Furthermore, in the semiconductor integrated circuit according to the present invention, in addition to any of the first to fifth features, the peeling prevention wiring layer is also used as a power supply wiring for supplying power to the semiconductor integrated circuit. This is the sixth feature.

  According to the present invention, the wiring exfoliation preventing structure includes an individual region where a plurality of through holes penetrating an interlayer insulating film directly above the exfoliation preventing wiring layer are formed in the first region, and an interlayer insulating film immediately below Disperses the stress applied to the chip by arranging the through-holes or contact holes alternately above and below without overlapping each other in each of the regions where a plurality of through-holes or contact holes are formed. It is possible to prevent peeling and cracking of the wiring layer.

  Also, through holes or contact holes are arranged alternately above and below, dispersion in the film formation process is dispersed, resulting in instability of the film structure that becomes prominent in the multilayer film structure (irregularity, wavy structure) Rather, a flatter multilayer wiring structure can be obtained. Here, the interval between the through holes or contact holes formed in a concentrated manner in the interlayer insulating film may be formed so as to be separated by at least one through hole or contact hole. Thereby, a flatter wiring layer can be formed in the upper layer of the through hole or contact hole.

  Further, when the peeling prevention structure is configured without using the contact hole, there is no restriction on the arrangement due to the device region arranged on the chip. As a result, the degree of freedom of wiring is improved and the chip area can be easily reduced.

  The above-described wiring peeling prevention structure can be applied to a semiconductor integrated circuit having a multilayer wiring structure having two or more layers, and is particularly effective when it has three or more wiring layers. In a semiconductor integrated circuit having a multilayer wiring structure of three or more layers, it is desirable to use the entire wiring layer as a peeling prevention wiring layer. However, the wiring peeling prevention structure can be manufactured by using at least two wiring layers including the lowermost wiring layer as the peeling prevention wiring layer. In that case, and when there are two wiring layers, there are two peeling prevention wiring layers, a through hole formed between the peeling prevention wiring layers, a lower peeling prevention wiring layer, and an element formed on the substrate. A wiring peeling prevention structure can be manufactured by a contact hole for electrically connecting the two.

  Thus, by providing a wiring peeling prevention structure in a wiring region constituted by a multilayer wiring layer having a wide wiring width so as to flow a large current, it is possible to simultaneously prevent peeling of power supply wiring of a semiconductor integrated circuit such as a power supply IC. It can be carried out.

  Therefore, according to the present invention, it is possible to prevent an increase in chip size and prevent wiring peeling without changing the manufacturing process.

The figure which shows the formation pattern (peeling prevention pattern) of a through hole in the wiring peeling prevention structure which concerns on 1st Embodiment of this invention. The structure sectional view of the wiring exfoliation prevention structure concerning a 1st embodiment of the present invention. The figure which shows the formation pattern (peeling prevention pattern) of a through hole in the wiring peeling prevention structure which concerns on 2nd Embodiment of this invention. The structure sectional view of the wiring exfoliation prevention structure concerning a 2nd embodiment of the present invention. The figure which shows the formation pattern (peeling prevention pattern) of the wiring pattern for the peeling prevention of wiring in the prior art, and a through hole. Sectional drawing of the wiring peeling prevention structure in a prior art.

<First Embodiment>
An example of the wiring peeling preventing structure in the present invention is shown in FIGS. FIG. 1 shows a through hole formation pattern (hereinafter referred to as a “peeling prevention pattern”) viewed from a direction perpendicular to the substrate surface, and FIG. 2 shows a structural cross-sectional view viewed from the A plane of FIG. In the following drawings, the main part of the wiring peeling prevention structure, particularly the wiring layer and the through hole are highlighted, and the dimensional ratio between each part of the actual wiring peeling prevention structure and each part shown in the drawing is not necessarily limited. Does not match.

  As shown in FIG. 2, four metal wiring layers 202 to 205 are formed as an anti-peeling wiring layer on an insulating layer 201 on a substrate 200 through interlayer insulating films 206 to 209, and the interlayer insulating films 206 to 209 are formed. Each of the metal wiring layers 202 to 205 adjacent via 208 has a plurality of first through holes 210 penetrating the interlayer insulating film 206, a plurality of second through holes 211 penetrating the interlayer insulating film 207, and The plurality of third through holes 212 penetrating the interlayer insulating film 208 are electrically connected to each other. The wiring width of the metal wiring layers 202 to 205 is sufficiently larger than the size of one of the through holes 210 to 212, and the metal wiring layers 202 to 205 are power supply wirings made larger than the wiring width of the internal circuit. .

  The metal wiring layers 202 to 205 that are also peeling prevention wiring layers overlap in a direction perpendicular to the substrate surface, and the first to third through holes are formed in a part of the overlapping portion (hereinafter referred to as a first region). The wiring peeling prevention structure is formed by forming 210 to 212 in a concentrated manner. FIG. 1 shows a pattern in which first to third through holes are formed in a first region where each of the metal wiring layers 202 to 205 overlaps in a direction perpendicular to the substrate surface. In the wiring peeling prevention structure, regions (hereinafter referred to as second regions) 103 to 105 in the first region where the first to third through holes 210 to 212 are formed in a concentrated manner are formed as interlayer insulating films 206 to 208. The second regions 103 to 105 overlap each other in a direction perpendicular to the substrate surface.

  Each region (shaded portion 101 in FIG. 1) in the second region 103 in which the first through hole 210 penetrating the interlayer insulating film 206 on the metal wiring layer 203 from the top layer to the second layer is formed. The second through-hole 211 penetrating the interlayer insulating film 207 under the metal wiring layer 203 is formed so as not to overlap each of the regions in the second region 104 (the white portion 102 in FIG. 1). Each region (white portion 102 in FIG. 1) in the second region 104 in which the second through hole 211 penetrating the interlayer insulating film 207 on the metal wiring layer 204 of the third layer from the upper layer is formed In order not to overlap each of the regions in the second region 105 where the third through hole 212 penetrating the interlayer insulating film 208 under the metal wiring layer 204 is formed (shaded portion 101 in FIG. 1). 3 through holes 21 -212 is respectively more, they are arranged in a concentrated on the metal wiring layers 203-205. Thereby, the formation regions 101 and 102 of the respective through holes 210 to 212 form the peeling prevention pattern shown in FIG. 1 on the metal wiring layers 202 to 205.

  By arranging the through holes 210 to 212 formed vertically adjacent to the metal wiring layers 202 to 205 so as not to overlap each other, the stress applied to the chip can be dispersed, and the metal wiring layers 202 to 205 are peeled off. And cracks can be prevented. In addition, by forming the through holes 210 to 212 so as not to overlap each other, the instability of the multilayer wiring structure (irregularity, wavy structure) is alleviated, and a flatter metal wiring layer can be formed.

Second Embodiment
Another example of the wiring peeling preventing structure in the present invention is shown in FIGS. In this example, three metal wiring layers are connected by two through holes and contact holes. FIG. 5 shows through hole and contact hole formation patterns (peeling prevention patterns) as seen from the direction perpendicular to the substrate surface, and FIG. 4 shows a structural sectional view as seen from the A surface in FIG. As shown in FIG. 4, three metal wiring layers 202 to 204 are formed on the insulating layer 201 on the substrate 200 as an anti-peeling wiring layer via interlayer insulating films 206 and 207, and the interlayer insulating film 206, Each of the metal wiring layers 202 to 204 that are adjacent to each other through 207 includes a plurality of first through holes 210 that penetrate the interlayer insulating film 206 and a plurality of second through holes 211 that penetrate the interlayer insulating film 207. Further, the lowermost metal wiring layer 206 is also electrically connected to the elements 214 and 215 on the substrate through a plurality of contact holes 213 penetrating the insulating film 201. Similar to the first embodiment, the wiring width of the metal wiring layers 202 to 204 is sufficiently larger than the size of each of the through holes 210 and 211 and the contact hole 213, and the metal wiring layers 202 to 204 are formed of the internal circuit. It is a power supply wiring made larger than the wiring width.

  The metal wiring layers 202 to 204, which are also peeling prevention wiring layers, overlap in a direction perpendicular to the substrate surface, and the first to second through holes are formed in a part of the overlapping portion (hereinafter referred to as the first region). The wiring peeling prevention structure is formed by forming 210 and 211 and the contact hole 213 in a concentrated manner. FIG. 3 shows a pattern in which first to second through holes and contact holes are formed in a first region where each of the metal wiring layers 202 to 204 overlaps in a direction perpendicular to the substrate surface. In the wiring peeling prevention structure, regions (hereinafter referred to as second regions) 303 and 304 in the first region where the first to second through holes 210 and 211 are concentrated are formed as interlayer insulating films 206 and 304. The second regions 303 and 304 overlap each other in a direction perpendicular to the substrate surface. The second regions 303 and 304 also overlap with a region 305 in the first region where the contact holes 213 are concentrated, in a direction perpendicular to the substrate surface.

  Each region (shaded portion 301 in FIG. 3) in the second region 303 in which the first through hole 210 penetrating the interlayer insulating film 206 on the metal wiring layer 203 from the uppermost layer to the second layer is formed. In order not to overlap each of the regions (white portions 302 in FIG. 3) in the second region 304 where the second through hole 211 penetrating the interlayer insulating film 207 under the metal wiring layer 203 is formed. A plurality of second through-holes 210 and 211 are concentrated on the metal wiring layers 203 and 204, respectively. Further, individual regions (in FIG. 3) in the second region 304 in which the second through holes 211 penetrating the interlayer insulating film 207 on the metal wiring layer 204 from the uppermost layer to the third layer (lowermost layer) are formed. A white portion 302) is a region in the region 305 (hatched portion 301 in FIG. 3) where the contact hole 213 that penetrates the insulating film 201 below the metal wiring layer 204 and is connected to the elements 214 and 215 on the substrate is formed. A plurality of contact holes 213 are concentrated under the metal wiring layer 204 so as not to overlap each other. Thereby, the formation regions 301 and 302 of the through holes 210 and 211 and the contact hole 213 form the peeling prevention pattern shown in FIG. 3 on the metal wiring layers 203 to 204.

  By arranging the through holes 210 and 211 and the contact holes 213 formed vertically adjacent to the metal wiring layers 202 to 204 so as not to overlap each other, the stress applied to the chip can be dispersed. -204 peeling and cracking can be prevented. In addition, by forming the through holes 210 and 211 and the contact hole 213 so as not to overlap each other, the instability of the multilayer wiring structure (irregularity, wavy structure) is alleviated, and a flatter metal wiring layer is formed. be able to.

  The above-described embodiment is an example of a preferred embodiment of the present invention. The embodiment of the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention.

<Another embodiment>
Another embodiment will be described below.

  <1> In the first and second embodiments, the regions 101, 102 or 301, 302 where the through holes or contact holes (conductive vias) are formed are shown as squares in FIGS. However, the present invention is not limited to this. For example, the through hole or contact hole formation region may be circular or rectangular. Further, in the above embodiment, the positions where the through holes or contact holes are formed are square lattice-shaped peeling prevention patterns, but the present invention is not limited to this, and for example, triangular lattices, hexagons The anti-peeling pattern can also be configured with other patterns such as a lattice pattern.

  <2> In the first and second embodiments, all layers of the multilayer wiring layer constitute the peeling prevention wiring layer, but a part of the multilayer wiring layer is used as the peeling prevention wiring layer, and the wiring peeling prevention structure is used. Can be created.

  <3> By the way, in the first and second embodiments, aluminum added with copper as a material for the metal wiring layer, a silicon oxide film as the material for the interlayer insulating film, and a material for the through hole and the contact hole are used. Tungsten is used, respectively, and the adhesion between the metal wiring layer and the interlayer insulating film is improved at the interface between the metal wiring layer and the interlayer insulating film, and aluminum reacts with the interlayer insulating film during the metal wiring formation process. In order to prevent this, a laminated film (TiN / Ti) of titanium and titanium nitride is formed as a barrier metal, but the present invention is not limited to this. The wiring peeling prevention structure of the present invention can be applied to any metal wiring material, interlayer insulating film material, through hole and contact hole material combination. Moreover, the wiring peeling preventing structure of the present invention can be manufactured by a known manufacturing process technique.

  The present invention can be used for a semiconductor integrated circuit having a multilayer wiring structure.

101, 102, 301, 302, 503: formation regions 103 to 105, 303, 304 of conductive vias (through holes or contact holes) 200: regions in which through holes are concentrated 200: substrate 201: insulating layers 202 to 205 : Wiring layers 206 to 208: Interlayer insulating film 209: Passivation layers 210 to 212: Through hole 213: Contact holes 214 and 215: Element 305 on substrate: Region 501 where contact holes are concentrated 501: Conductive pad 502: Mesh-like wiring pattern

Claims (6)

The wiring layer has three or more wiring layers, and the interlayer insulating film that electrically insulates between the wiring layer and the lowermost wiring layer and the substrate, and penetrates through the interlayer insulating film between the wiring layers. A through hole for electrically connecting the wiring layers adjacent to each other through an interlayer insulating film, and the lowermost wiring layer through the interlayer insulating film on the substrate and an active element or passive on the substrate In a semiconductor integrated circuit in which a multilayer wiring structure is formed by a contact hole that electrically connects an element,
Each of the peeling prevention wiring layers composed of at least three wiring layers adjacent via the interlayer insulating film has a first region overlapping in a direction perpendicular to the substrate surface;
In each of the first regions, each of the interlayer insulating films between the respective peeling prevention wiring layers has a second region having a closed single contour line formed by concentrating the plurality of through holes,
For each of the peeling prevention wiring layers excluding the uppermost layer and the lowermost layer,
The second region in which the through hole penetrating the interlayer insulating film immediately above the peeling prevention wiring layer is formed, the second region in which the through hole penetrating the interlayer insulating film immediately below is formed; Overlapping in the direction perpendicular to the substrate surface,
The individual regions in the second region in which the through holes penetrating the interlayer insulating film immediately above the peeling prevention wiring layer are formed, and the through holes penetrating the interlayer insulating film immediately below are formed. Do not overlap each of the plurality of regions in the second region in a direction perpendicular to the substrate surface;
A semiconductor integrated circuit having a wiring peeling prevention structure. The peeling prevention wiring layer includes the lowermost wiring layer,
A plurality of contact holes penetrating the interlayer insulating film on the substrate are concentrated in the second region in which the through hole penetrating the interlayer insulating film immediately above the lowermost anti-separation wiring layer is formed. Formed
The individual regions where the contact holes are concentrated are as follows:
2. The method according to claim 1, wherein each of the plurality of regions in the second region in which the through hole is formed immediately above the lowermost anti-separation wiring layer does not overlap in a direction perpendicular to the substrate surface. The semiconductor integrated circuit as described. A plurality of wiring layers; and an interlayer insulating film that electrically insulates between the wiring layer and the lowermost wiring layer and the substrate; and the interlayer insulating layer through the interlayer insulating film between the wiring layers A through hole that electrically connects the wiring layers adjacent to each other through a film; and the lowermost wiring layer penetrating the interlayer insulating film on the substrate and an active element or a passive element on the substrate In a semiconductor integrated circuit in which a multilayer wiring structure is formed by contact holes that electrically connect
Each of the peeling prevention wiring layers composed of two layers of the lowermost wiring layer adjacent to the interlayer insulating film and the upper wiring layer has a first region overlapping in a direction perpendicular to the substrate surface,
A second region having a closed single contour line formed by concentrating a plurality of the through holes in the interlayer insulating film between the peeling prevention wiring layers in the first region;
In the second region, a plurality of the contact holes penetrating the interlayer insulating film on the substrate are formed intensively,
The individual regions formed by concentrating the contact holes do not overlap each of the plurality of regions where the through holes are formed in the second region in a direction perpendicular to the substrate surface.
A semiconductor integrated circuit having a wiring peeling prevention structure.   In the wiring exfoliation preventing structure, each of the contact holes penetrating the interlayer insulating film on the substrate in the second region is two-dimensionally arranged with an interval larger than the diameter of the contact hole. The semiconductor integrated circuit according to claim 2 or 3,   In the wiring exfoliation preventing structure, each of the through holes penetrating the interlayer insulating film between the exfoliation preventing wiring layers in each of the second regions is two-dimensionally spaced with an interval larger than the diameter of the through hole. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is arranged. The semiconductor integrated circuit according to claim 1, wherein the peeling prevention wiring layer is also used as a power supply wiring for supplying power to the semiconductor integrated circuit.

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