JP2010245433A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a p-type MIS transistor formed on a semiconductor substrate having a (110) plane as a principal surface, the performance of the p-type MIS transistor being improved more. <P>SOLUTION: The semiconductor device includes the p-type MIS transistor PTr formed on the semiconductor substrate 10 having the (110) plane as the principal surface. The p-type MIS transistor PTr includes a first gate insulating film 13a formed on a first active region 10a of the semiconductor substrate 10, and a first gate electrode 14A composed of a first metal film 14a formed on the first gate insulating film 13a, and a first silicon film 15a formed on the first metal film 14a. The first metal film 14a has a film thickness of 1 to 10 nm. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device including a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate electrode including a metal film on a semiconductor substrate having a (110) plane as a main surface. It relates to a manufacturing method.

In order to improve the performance of semiconductor integrated circuits, alumina (Al ₂ O ₃ ), hafnia (HfO ₂ ), and hafnium silicate (HfSiO) are used instead of the conventional gate insulating film made of silicon oxide film (or silicon oxynitride film). _A gate insulating film made of a high dielectric material represented by _x ) has been put into practical use. Further, instead of the conventional polysilicon gate electrode made of a polysilicon film, a full metal gate electrode made of a metal film, or MIPS (Metal-inserted Poly-silicon) in which a metal film is inserted between the polysilicon film and the gate insulating film. The use of a gate electrode with a Stack structure is underway.

  As a technique for improving the performance of a p-type MISFET (hereinafter referred to as “p-type MIS transistor”), for example, a technique for providing a SiGe layer in a p-type source / drain region has been proposed. Thereby, compressive stress is applied in the gate length direction of the channel region, and the performance of the p-type MIS transistor is improved.

  Second, for example, instead of a conventional semiconductor substrate having a (100) plane as a main surface (hereinafter referred to as “(100) plane substrate”), a semiconductor substrate having a (110) plane as a main surface (hereinafter referred to as “ (Referred to as non-patent documents 1 to 3), in which a p-type MIS transistor is provided on a (110) plane substrate. This increases the hole mobility and improves the performance of the p-type MIS transistor.

  In the case of the first example, since a new SiGe layer is provided in the p-type source / drain region, there is a problem that the number of processes increases and the cost increases.

  On the other hand, in the case of the second example, since it is only necessary to change from the (100) plane substrate to the (110) plane substrate, the number of processes does not increase, and the performance of the p-type MIS transistor can be easily and inexpensively. Can be improved, so it is considered promising.

S. A. Krishnan et al., “High Performing pMOSFETs on Si (110) for Application to Hybrid Orientation Technologies? Comparison of HfO2 and HfSiON”, IEDM Tech. Digest 2006 Y. Tateshita et al., “High-Performance and Low-Power CMOS Device Technologies Featuring Metal / High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates”, IEDM Tech. Digest 2006 H. R. Harris et al., “Flexible, Simplified CMOS on Si (110) with Metal Gate / High κ for HP and LSTP”, IEDM Tech. Digest 2007, pp 57-60

  By the way, in the technique of providing a p-type MIS transistor on a (110) plane substrate, an optimum gate insulating film material has been studied in order to increase hole mobility.

  With the miniaturization of semiconductor devices, further performance improvement of p-type MIS transistors is required. However, there is a limit to improving the performance of the p-type MIS transistor only by using an optimum gate insulating film material as the gate insulating film material, and it is difficult to satisfy the above requirements.

  In view of the above, an object of the present invention is to further improve the performance of a p-type MIS transistor in a semiconductor device including a p-type MIS transistor formed on a semiconductor substrate having a (110) plane as a main surface.

  In order to achieve the object of the present invention, the present inventors have conducted intensive studies and found out the following.

  In the p-type MIS transistor formed on the (100) plane substrate, the relationship between the effective electric field and the hole mobility in each of the cases where the thickness of the metal film of the gate electrode is small and large was verified. FIG. 1A is a graph showing the relationship between effective electric field and hole mobility in a p-type MIS transistor formed on a (100) plane substrate. The solid line shown in FIG. 1A indicates the case where the thickness of the metal film of the gate electrode is 5 nm, and the solid line indicates the case where the thickness of the metal film of the gate electrode is 15 nm.

  On the other hand, in the p-type MIS transistor formed on the (110) plane substrate, the relationship between the effective electric field and the hole mobility was examined when the thickness of the metal film of the gate electrode was small and large. FIG. 1B is a graph showing the relationship between effective electric field and hole mobility in a p-type MIS transistor formed on a (110) plane substrate. The solid line shown in FIG. 1B indicates the case where the thickness of the metal film of the gate electrode is 5 nm, and the solid line indicates the case where the thickness of the metal film of the gate electrode is 15 nm.

  The dotted lines shown in FIGS. 1A and 1B are universal lines when a silicon oxide film is used as the gate insulating film in the p-type MIS transistor formed on the (100) plane substrate.

  In FIGS. 1A and 1B, the configuration of the p-type MIS transistor of the ■ line (or ◯ line) is as follows. The p-type MIS transistor includes a gate insulating film and a gate electrode having a MIPS structure (that is, a gate electrode made of a metal film formed on the gate insulating film and a silicon film formed on the metal film). The gate insulating film is made of a high dielectric constant film containing hafnium (Hf). The metal film of the gate electrode is a titanium nitride (TiN) film having a thickness of 5 nm (or a thickness of 15 nm). The silicon film of the gate electrode is made of a polysilicon film having a thickness of 100 nm.

1A and 1B, the configuration of the p-type MIS transistor of the universal line is as follows. The p-type MIS transistor includes a gate insulating film and a gate electrode. The gate insulating film is made of a SiO ₂ film. The gate electrode is made of a polysilicon film having a thickness of 100 nm.

  In the case of a conventional (100) plane substrate, as shown in FIG. 1 (a), the effective electric field is positive when the metal film thickness is small in the actual use region, that is, in the range of the electric field actually generated in the transistor operation. The hole mobility (see the ■ line) is higher than the hole mobility (see the ○ line) when the thickness of the metal film is large.

  In the case of a (110) plane substrate, as shown in FIG. 1B, the effective electric field is positive in the actual use region, that is, in the range of the electric field actually generated in the transistor operation, when the metal film thickness is small. The hole mobility (see the ■ line) is higher than the hole mobility (see the ○ line) when the thickness of the metal film is large.

  Regarding the degree of hole mobility when the metal film thickness is small compared to the hole mobility when the metal film thickness is large, the (100) plane substrate and (110) plane substrate When compared with the case, as can be seen from FIGS. 1A and 1B, the degree in the case of the (110) plane substrate is larger than the degree in the case of the (100) plane substrate.

  From this, the present inventors have found the following findings. In particular, in the case of a p-type MIS transistor formed on a (110) plane substrate, the hole mobility is effectively increased by reducing the film thickness of the metal film of the gate electrode, thereby further improving the performance of the p-type MIS transistor. Can be improved.

  In order to achieve the above object, the present invention has been made on the basis of the knowledge found by the present inventors. Specifically, the semiconductor device according to the present invention mainly has a (110) plane. A semiconductor device including a p-type MIS transistor formed on a semiconductor substrate serving as a surface, wherein the p-type MIS transistor includes a first gate insulating film formed on a first active region in the semiconductor substrate, A first metal film formed on one gate insulating film and a first gate electrode made of a first silicon film formed on the first metal film, the first metal film having a film thickness Is 1 nm or more and 10 nm or less.

  According to the semiconductor device of the present invention, the thickness of the first metal film of the first gate electrode is 1 nm or more and 10 nm or less. Thereby, the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved.

  Furthermore, since the thickness of the first metal film is 10 nm or less, an increase in EOT can be suppressed.

  In the semiconductor device according to the present invention, the first metal film preferably has a thickness of 1 nm or more and 5 nm or less.

  If it does in this way, hole mobility can be raised more effectively.

  In the semiconductor device according to the present invention, the first gate insulating film preferably includes a high dielectric constant film made of a metal oxide.

  In the semiconductor device according to the present invention, a first offset spacer having an I-shaped cross section formed on the side surface of the first gate electrode, and a first offset spacer on the side surface of the first gate electrode. The first sidewall having an L-shaped cross-section and the upper surface of the region located on the side of the first sidewall in the first active region from the surface of the first sidewall. It is preferable that the first insulating film is further formed.

  In the semiconductor device according to the present invention, the semiconductor device further includes an n-type MIS transistor formed on the semiconductor substrate, and the n-type MIS transistor is formed on the second active region in the semiconductor substrate. It is preferable to include a film and a second gate electrode having a second metal film formed over the second gate insulating film.

  In the semiconductor device according to the present invention, the second gate electrode includes a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film. Thus, it is preferable that the first metal film and the second metal film have the same film thickness and are made of the same metal material.

  In the semiconductor device according to the present invention, the second gate electrode includes a second metal film formed on the second gate insulating film, a third metal film formed on the second metal film, A second silicon film formed on the third metal film, wherein the first metal film and the second metal film are made of different metal materials, and the first metal film and the third metal film The films preferably have the same film thickness and are made of the same metal material.

  In this case, as the metal material of the second metal film in contact with the second gate insulating film, the metal material of the first metal film in contact with the first gate insulating film (that is, work suitable for the p-type MIS transistor). A metal material having a work function suitable for an n-type MIS transistor can be used without using the same metal material as that having a function. Therefore, the performance of the n-type MIS transistor can be improved.

  In the semiconductor device according to the present invention, the second gate electrode is composed of a second metal film formed on the second gate insulating film, and the first metal film and the second metal film are different from each other. The second metal film is made of a metal material, and the film thickness of the second metal film is equal to or more than the total film thickness of the film thickness of the first metal film and the film thickness of the first silicon film. Larger is preferred.

  In this case, as the metal material of the second metal film in contact with the second gate insulating film, the metal material of the first metal film in contact with the first gate insulating film (that is, work suitable for the p-type MIS transistor). A metal material having a work function suitable for an n-type MIS transistor can be used without using the same metal material as that having a function. Therefore, the performance of the n-type MIS transistor can be improved.

  In the semiconductor device according to the present invention, it is preferable that the first metal film and the second metal film have different work functions.

  In the semiconductor device according to the present invention, it is preferable that the first gate insulating film and the second gate insulating film include high dielectric constant films made of the same metal oxide.

  In the semiconductor device according to the present invention, a second offset spacer having an I-shaped cross-section formed on the side surface of the second gate electrode and a second offset spacer on the side surface of the second gate electrode The second sidewall having an L-shaped cross-section and the upper surface of the region located on the side of the second sidewall in the second active region from the surface of the second sidewall. And a second insulating film formed preferably.

  In the semiconductor device according to the present invention, the second insulating film is preferably a stress insulating film that generates tensile stress in the gate length direction of the channel region in the second active region.

  In this case, a tensile stress can be applied in the gate length direction of the channel region in the second active region by the stress insulating film, so that the performance of the n-type MIS transistor can be improved.

  In order to achieve the above object, the present invention has been made on the basis of the knowledge found by the present inventors. Specifically, a method for manufacturing a semiconductor device according to the present invention includes (110) A method for manufacturing a semiconductor device including a p-type MIS transistor formed in a first active region in a semiconductor substrate having a main surface as a surface, wherein a gate insulating film forming film is formed on the first active region in the semiconductor substrate. Forming a first metal film forming film on the gate insulating film forming film (b), and forming a silicon film forming film on the first metal film forming film ( c) and the first gate insulating film formed of the gate insulating film forming film on the first active region by sequentially patterning the silicon film forming film, the first metal film forming film, and the gate insulating film forming film. And a first metal film forming film. And a step (d) of forming a first gate electrode made of a first silicon film made of a metal film and a silicon film forming film, wherein the first metal film forming film has a thickness of 1 nm or more. And it is 10 nm or less.

  According to the semiconductor device manufacturing method of the present invention, the thickness of the first metal film of the first gate electrode is set to 1 nm or more and 10 nm or less. Thereby, the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved.

  Furthermore, since the thickness of the first metal film is 10 nm or less, an increase in EOT can be suppressed.

  In the method for manufacturing a semiconductor device according to the present invention, the first metal film forming film preferably has a thickness of 1 nm or more and 5 nm or less.

  If it does in this way, hole mobility can be raised more effectively.

  In the method for manufacturing a semiconductor device according to the present invention, the semiconductor device further includes an n-type MIS transistor formed in the second active region of the semiconductor substrate, and the step (a) is performed on the second active region of the semiconductor substrate. The step (d) includes forming a second insulating region by sequentially patterning the silicon film forming film, the first metal film forming film, and the gate insulating film forming film. A second gate insulating film comprising a second gate insulating film comprising a gate insulating film forming film, a second metal film comprising a first metal film forming film, and a second silicon film comprising a silicon film forming film. It is preferable to include a step of forming an electrode.

  In the method for manufacturing a semiconductor device according to the present invention, the semiconductor device further includes an n-type MIS transistor formed in the second active region of the semiconductor substrate, and the step (a) is performed on the second active region of the semiconductor substrate. Forming a second metal film on the gate insulating film forming film on the second active region after the step (a) and before the step (b). A step (e) of forming a film, wherein the step (b) includes forming a first metal film formation film on the gate insulating film formation film on the first active region and the second metal film formation film; In the step (d), the silicon film forming film, the first metal film forming film, the second metal film forming film, and the gate insulating film forming film are sequentially patterned to form a second active layer. A second gate insulating film comprising a gate insulating film forming film on the region; A second metal film made of the second metal film formation film, a third metal film made of the first metal film formation film, and a second gate made of the second silicon film made of the silicon film formation film It is preferable to include a step of forming an electrode.

  In this case, since the metal material having a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film, the performance of the n-type MIS transistor can be improved.

  In the method for manufacturing a semiconductor device according to the present invention, the semiconductor device further includes an n-type MIS transistor formed in the second active region of the semiconductor substrate, and the step (a) is performed on the second active region of the semiconductor substrate. The step (d) includes forming a second insulating region by sequentially patterning the silicon film forming film, the first metal film forming film, and the gate insulating film forming film. Forming a second gate insulating film made of a gate insulating film forming film, a dummy metal film made of a first metal film forming film, and a dummy silicon film made of a silicon film forming film; After (d), the step (e) of removing the dummy silicon film and the dummy metal film, and after the step (e), the second gate electrode made of the second metal film is formed on the second gate insulating film. Form Preferably further comprising a step (f).

  In this case, since the metal material having a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film, the performance of the n-type MIS transistor can be improved.

  Furthermore, the dummy metal film and the dummy silicon film formed with high precision can be replaced with the second metal film. Therefore, the second gate electrode made of the second metal film can be formed with high accuracy.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, in the p-type MIS transistor formed on the semiconductor substrate having the (110) plane as the main surface, the thickness of the first metal film of the first gate electrode is 1 nm. Above and 10 nm or less. Thereby, the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved. Furthermore, since the thickness of the first metal film is 10 nm or less, an increase in EOT can be suppressed.

(a) is a graph which shows the relationship between an effective electric field and a hole mobility in each of the case where the film thickness of the metal film is small and large in the p-type MIS transistor formed on the (100) plane substrate. . On the other hand, (b) is a graph showing the relationship between the effective electric field and the hole mobility when the metal film thickness is small and large in the p-type MIS transistor formed on the (110) plane substrate. It is. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention in process order. It is a graph which shows about the relationship between the film thickness of a metal film, and a hole mobility, and the relationship between the film thickness of a metal film, and EOT. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention in process order. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order. (a)-(c) is process sectional drawing of the principal part of the gate length direction which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention in process order.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
A semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  2 (a) to (c), FIGS. 3 (a) to (c) and FIGS. 4 (a) to (c) are described below with respect to a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The description will be given with reference. 2 (a) to 4 (c) are cross-sectional views of main steps in the gate length direction showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. 2 (a) to 4 (c), FIG. 6 (a) to FIG. 7 (c), which will be described later, and FIG. 8 (a) to FIG. 10 (c), which will be described later. "Indicates a region where a p-type MIS transistor is formed, and" nMIS region "shown on the right side indicates a region where an n-type MIS transistor is formed.

  First, as shown in FIG. 2A, by, for example, an embedded element isolation (Shallow Trench Isolation: STI) method, an upper portion of a semiconductor substrate 10 made of, for example, p-type silicon and having a (110) plane as a main surface An element isolation region 11 in which an insulating film is embedded in the trench is selectively formed. As a result, a first active region 10 a made of the semiconductor substrate 10 surrounded by the element isolation region 11 is formed in the pMIS region. On the other hand, in the nMIS region, a second active region 10b made of the semiconductor substrate 10 surrounded by the element isolation region 11 is formed. Thereafter, an n-type impurity such as P (phosphorus) is implanted into the pMIS region in the semiconductor substrate 10 by lithography and ion implantation. On the other hand, a p-type impurity such as B (boron) is implanted into the nMIS region in the semiconductor substrate 10. Thereafter, the semiconductor substrate 10 is heat-treated at, for example, 850 ° C. for 30 seconds. Thereby, an n-type well region 12 a is formed in the pMIS region in the semiconductor substrate 10. On the other hand, a p-type well region 12 b is formed in the nMIS region in the semiconductor substrate 10.

  Next, as shown in FIG. 2B, after cleaning the surface of the semiconductor substrate 10 by, for example, dilute hydrofluoric acid treatment, the first active region 10a and the first active region 10a and by, for example, ISSG (In-Situ Steam Generation) oxidation method. On the second active region 10b, a base film (not shown) made of a silicon oxide film having a film thickness of 0.8 nm to 1 nm, for example, is formed. After that, for example, by a metal organic chemical vapor deposition (MOCVD) method or an ALD (Atomic Layer Deposition) method, a gate insulating film made of a high dielectric constant film having a film thickness of, for example, 2 nm is formed on the base film. A formation film 13 is deposited. Here, the gate insulating film forming film 13 preferably includes a high dielectric constant film made of a metal oxide having a relative dielectric constant of, for example, 10 or more.

  Thereafter, a first metal film forming film 14 made of, for example, titanium nitride (TiN) is deposited on the gate insulating film forming film 13 by, eg, CVD (Chemical Vapor Deposition), ALD, or sputtering. At this time, the first metal film forming film 14 has a film thickness of, for example, 1 nm or more and 10 nm or less (preferably, for example, 1 nm or more and 5 nm or less).

  Thereafter, a silicon film forming film 15 made of, for example, a polysilicon film having a thickness of 100 nm is deposited on the first metal film forming film 14 by, eg, CVD.

  Next, as shown in FIG. 2C, a resist pattern (not shown) having a gate pattern shape is formed on the silicon film forming film 15 by photolithography. Thereafter, using the resist pattern as a mask, the silicon film forming film 15, the first metal film forming film 14, and the gate insulating film forming film 13 are sequentially patterned by dry etching. Thus, the first gate insulating film 13a, the first metal film 14a, and the first silicon film 15a are sequentially formed on the first active region 10a. At the same time, a second gate insulating film 13b, a second metal film 14b, and a second silicon film 15b are sequentially formed on the second active region 10b. Thereafter, the resist pattern is removed.

  In this manner, the first gate insulating film 13a and the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a are formed on the first active region 10a. At the same time, a second gate insulating film 13b and a second gate electrode 14B made of the second metal film 14b and the second silicon film 15b are formed on the second active region 10b.

  Next, as shown in FIG. 3A, an insulating film for offset spacer made of, for example, a silicon oxide film having a thickness of 8 nm is deposited on the entire surface of the semiconductor substrate 10 by, eg, CVD. Thereafter, anisotropic etching is performed on the insulating film for offset spacer. Thus, a first offset spacer 16a having an I-shaped cross section is formed on the side surfaces of the first gate insulating film 13a and the first gate electrode 14A. At the same time, a second offset spacer 16b having an I-shaped cross section is formed on the side surfaces of the second gate insulating film 13b and the second gate electrode 14B.

Thereafter, a p-type impurity such as BF ₂ is implanted into the first active region 10a using the first gate electrode 14A as a mask by lithography and ion implantation. As a result, a p-type source / drain region (LDD region or extension region) 17a having a relatively shallow junction depth is formed in a self-aligned manner below the side of the first gate electrode 14A in the first active region 10a. On the other hand, an n-type impurity such as As (arsenic) is implanted into the second active region 10b using the second gate electrode 14B as a mask. As a result, an n-type source / drain region (LDD region or extension region) 17b having a relatively shallow junction depth is formed in a self-aligned manner below the side of the second gate electrode 14B in the second active region 10b.

  Next, as shown in FIG. 3B, an insulating film for an inner sidewall made of, for example, a silicon oxide film having a thickness of 10 nm and a film thickness of 30 nm are formed on the entire surface of the semiconductor substrate 10 by, eg, CVD. An insulating film for the outer side wall made of a silicon nitride film is sequentially deposited. Thereafter, anisotropic etching is performed on the inner sidewall insulating film and the outer sidewall insulating film. As a result, the first inner sidewall 18a having the L-shaped cross section and the first side wall are formed on the side surfaces of the first gate insulating film 13a and the first gate electrode 14A via the first offset spacer 16a. A first sidewall 19A composed of the outer sidewall 19a is formed. At the same time, on the side surfaces of the second gate insulating film 13b and the second gate electrode 14B, a second inner side wall 18b having a L-shaped cross section and a second shape are provided via a second offset spacer 16b. A second sidewall 19B composed of the outer sidewall 19b is formed.

  Thereafter, by lithography and ion implantation, the first active region 10a is masked with the first gate electrode 14A, the first offset spacer 16a, and the first sidewall 19A, for example, B (boron) or the like. A p-type impurity is implanted. As a result, the p-type source / drain having a junction depth deeper than the shallow p-type source / drain region 17a and relatively deep in the first active region 10a outside the first sidewall 19A. The region 20a is formed in a self-aligning manner. On the other hand, an n-type impurity such as As (arsenic) is implanted into the second active region 10b using the second gate electrode 14B, the second offset spacer 16b, and the second sidewall 19B as a mask. As a result, the n-type source / drain having a junction depth deeper than the shallow n-type source / drain region 17b and relatively deep in the second active region 10b outside the second sidewall 19B. The region 20b is formed in a self-aligning manner. Thereafter, the conductive impurities contained in the deep p-type and n-type source / drain regions 20a and 20b are activated by heat treatment.

  Next, as shown in FIG. 3C, for example, the first and second inner sidewalls (silicon oxide films) 18a and 18b are selectively used with the first or second dry etching method or wet etching method. The second outer side walls (silicon nitride films) 19a and 19b are removed.

  Next, as shown in FIG. 4A, natural oxide films (not shown) formed on the surfaces of the deep p-type and n-type source / drain regions 20a and 20b, and the first and second silicon films 15a. , 15b, a natural oxide film (not shown) formed on the upper surface is removed. Thereafter, a metal film for silicide (not shown) made of nickel (Ni) having a thickness of 10 nm, for example, is deposited on the entire surface of the semiconductor substrate 10 by, for example, sputtering. Thereafter, Si in the deep p-type and n-type source / drain regions 20a and 20b is reacted with Ni in the metal film for silicide by, for example, first RTA (Rapid Thermal Annealing) treatment at 320 ° C. in a nitrogen atmosphere. First and second metal silicide films 21a and 21b made of nickel silicide are formed on the deep p-type and n-type source / drain regions 20a and 20b. At the same time, the Si of the first and second silicon films 15a and 15b and Ni of the metal film for silicide are reacted to form a third of nickel silicide on the first and second silicon films 15a and 15b. , Fourth metal silicide films 22a and 22b are formed. Thereafter, the semiconductor substrate 10 is immersed in an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide. Thus, portions remaining on the element isolation region 11, the first and second offset spacers 16a and 16b, the first and second inner sidewalls 18a and 18b, etc. in the silicide metal film (that is, the silicide metal) The unreacted part of the membrane) is removed. Thereafter, the first and second metal silicide films 21a and 21b and the third and fourth metal silicides are formed by the second RTA process under a temperature (for example, 550 ° C.) higher than the temperature in the first RTA process. The silicide composition ratio of the films 22a and 22b is stabilized.

  Next, as shown in FIG. 4B, first and second insulating films 23a and 23b made of a silicon nitride film of, eg, a 50 nm-thickness are deposited on the entire surface of the semiconductor substrate 10 by, eg, plasma CVD. (Note that the first insulating film 23a and the second insulating film 23b are integrally formed).

  Thereafter, a first interlayer insulating film 24 made of a silicon oxide film is deposited on the first and second insulating films 23a and 23b by, for example, CVD, and then the first interlayer insulating film 24 is formed by, for example, CMP (Chemical Mechanical Polishing). The surface of the interlayer insulating film 24 is planarized.

  Next, as shown in FIG. 4C, the first insulating film 23a and the first interlayer insulating film 24 are formed on the first insulating film 23a and the first interlayer insulating film 24 by dry etching, as in the method of manufacturing a semiconductor device having a normal MIS transistor. A first contact hole 25a exposing the upper surface of one metal silicide film 21a is formed. At the same time, a second contact hole 25 b exposing the upper surface of the second metal silicide film 21 b is formed in the second insulating film 23 b and the first interlayer insulating film 24. At this time, the etching is stopped once when the first and second insulating films 23a and 23b are exposed, and the first and second metal silicide films 21a and 21b are used by using a two-step etching method in which etching is performed again. The amount of overetching can be reduced.

  Thereafter, a barrier metal formed by sequentially depositing titanium and titanium nitride on the bottom and side walls of the first and second contact holes 25a and 25b and the first interlayer insulating film 24 by sputtering or CVD. A film is formed. Thereafter, a conductive film made of tungsten is deposited on the barrier metal film by CVD so as to fill the first and second contact holes 25a and 25b. Thereafter, portions of the conductive film and the barrier metal film formed outside the first and second contact holes 25a and 25b are removed by CMP. In this way, first and second contact plugs 26a and 26b are formed in which the conductive film is buried in the first and second contact holes 25a and 25b via the barrier metal film. Thereafter, metal wiring (not shown) that is electrically connected to the first and second contact plugs 26 a and 26 b is formed on the first interlayer insulating film 24.

  As described above, the semiconductor device according to the present embodiment, that is, the p-type MIS transistor PTr having the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a, and the second metal A semiconductor device including the n-type MIS transistor NTr having the second gate electrode 14B made of the film 14b and the second silicon film 15b can be manufactured.

  The configuration of the semiconductor device according to the first embodiment of the present invention will be described below with reference to FIG.

  As shown in FIG. 4C, a p-type MIS transistor PTr is provided in the pMIS region of the semiconductor substrate 10 having the (110) plane as a main surface, and the n-type MIS is provided in the nMIS region of the semiconductor substrate 10. A transistor NTr is provided.

  As shown in FIG. 4C, the p-type MIS transistor PTr includes a first gate insulating film 13a formed on the first active region 10a and a first gate insulating film 13a formed on the first gate insulating film 13a. A first gate electrode 14A composed of one metal film 14a and a first silicon film 15a, a first offset spacer 16a having an I-shaped cross section formed on the side surface of the first gate electrode 14A, A shallow p-type source / drain region 17a formed laterally below the first gate electrode 14A in the first active region 10a and a first offset spacer 16a formed on the side surface of the first gate electrode 14A. A first p-type source / drain region formed on the outer side of the first inner side wall 18a in the first active region 10a. A first metal silicide film 21a formed on the region 20a, the deep p-type source / drain region 20a, a third metal silicide film 22a formed on the first gate electrode 14A, and a first gate electrode And a first insulating film 23a formed across the upper surface of the region located on the side of the first inner sidewall 18a in the first active region 10a from the upper surface of 14A.

  As shown in FIG. 4C, the n-type MIS transistor NTr includes a second gate insulating film 13b formed on the second active region 10b and a second gate insulating film 13b formed on the second gate insulating film 13b. A second gate electrode 14B composed of two metal films 14b and a second silicon film 15b, a second offset spacer 16b having an I-shaped cross section formed on the side surface of the second gate electrode 14B, A shallow n-type source / drain region 17b formed laterally below the second gate electrode 14B in the second active region 10b, and a second offset spacer 16b formed on a side surface of the second gate electrode 14B. And a deep n-type source / drain region formed on the outer side of the second inner sidewall 18b in the second active region 10b. A second metal silicide film 21b formed on the region 20b, the deep n-type source / drain region 20b, a fourth metal silicide film 22b formed on the second gate electrode 14B, and a second gate electrode. And a second insulating film 23b formed over the upper surface of the region located on the side of the second inner sidewall 18b in the second active region 10b from the upper surface of 14B.

  A first interlayer insulating film 24 is formed on the integrally formed first and second insulating films 23a and 23b. A first contact plug 26a having a lower end connected to the first metal silicide film 21a is formed in the first insulating film 23a and the first interlayer insulating film 24. In the second insulating film 23b and the first interlayer insulating film 24, a second contact plug 26b whose lower end is connected to the second metal silicide film 21b is formed.

  The first metal film 14a has a thickness of 1 nm or more and 10 nm or more (preferably 1 nm or more and 5 nm or less).

  The first metal film 14a and the second metal film 14b have the same film thickness and are made of the same metal material (for example, TiN). The first metal film 14a and the second metal film 14b have the same work function.

  The first gate insulating film 13a and the second gate insulating film 13b include high dielectric constant films made of the same metal oxide.

  As described above, the inventors of the present invention made extensive studies and found the following findings. In the p-type MIS transistor formed on the (110) plane substrate, the hole mobility is effectively increased by reducing the film thickness of the metal film of the gate electrode, thereby further improving the performance of the p-type MIS transistor. be able to.

  Then, when this inventors verified about the film thickness of a metal film, it discovered that it showed as follows.

  In the p-type MIS transistor formed on the (110) plane substrate, the relationship between the thickness of the metal film and the hole mobility, and the thickness of the metal film and the equivalent oxide thickness (EOT) The relationship will be described with reference to FIG. FIG. 5 is a graph showing the relationship between the thickness of the metal film and the hole mobility, and the relationship between the thickness of the metal film and EOT.

  The Δ line shown in FIG. 5 indicates the relationship between the thickness of the metal film and the hole mobility in the p-type MIS transistor formed on the (110) plane substrate. For comparison, the relationship between the thickness of the metal film and the hole mobility in a p-type MIS transistor formed on a (100) plane substrate is shown (see FIG. 5: line ▲).

  The squares shown in FIG. 5 indicate the relationship between the thickness of the metal film and EOT in the p-type MIS transistor formed on the (110) plane substrate. For comparison, the relationship between the thickness of the metal film and the EOT in a p-type MIS transistor formed on a (100) plane substrate is shown (see FIG. 5: ■ line).

  The configuration of the p-type MIS transistors of the △ line, ▲ line, □ line, and ■ line is as follows. The p-type MIS transistor includes a gate insulating film and a gate electrode having a MIPS structure. The gate insulating film is made of a high dielectric constant film containing Hf. The metal film of the gate electrode is a TiN film having a film thickness of 4 nm, 10 nm, or 15 nm. The silicon film of the gate electrode is made of a polysilicon film having a thickness of 100 nm.

-Relationship between metal film thickness and hole mobility-
In the case of a (110) plane substrate, as shown by the Δ line in FIG. 5, the hole mobility increases as the metal film thickness decreases.

  As can be seen from the Δ line shown in FIG. 5, the hole mobility can be effectively increased if the thickness of the metal film is 10 nm or less, and preferably the thickness of the metal film is 5 nm or less. The hole mobility can be increased more effectively.

-Relationship between metal film thickness and EOT-
In the case of a (110) plane substrate, as shown by the □ line in FIG. 5, the EOT is substantially constant when the thickness of the metal film is 4 nm or more and 10 nm or less. On the other hand, when the thickness of the metal film exceeds 10 nm, EOT increases as the thickness of the metal film increases.

  When EOT becomes large, there arises a problem that the driving capability of the p-type MIS transistor is lowered. Therefore, from the viewpoint of suppressing the increase in EOT, the thickness of the metal film is preferably 10 nm or less as can be seen from the □ line in FIG.

  The factors that increase EOT as the thickness of the metal film increases are considered as follows. As the thickness of the metal film increases, the amount of oxygen contained in the metal film increases. Oxygen contained in the metal film diffuses into the gate insulating film during heat treatment (specifically, for example, RTA treatment) performed after the metal film is formed. Therefore, as the thickness of the metal film increases, the amount of oxygen that diffuses into the gate insulating film increases, so that EOT increases.

  As described above, by setting the thickness of the metal film to 10 nm or less, the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved. In addition, an increase in EOT can be suppressed by setting the thickness of the metal film to 10 nm or less. Furthermore, the hole mobility can be more effectively increased by setting the thickness of the metal film to 5 nm or less. Therefore, the upper limit of the thickness of the metal film is preferably 10 nm (preferably 5 nm).

  On the other hand, the lower limit of the thickness of the metal film is preferably 1 nm. The reason for this is as follows. First, in order to form a metal film uniformly, it is preferable that the film thickness of the metal film is 1 nm or more. When the thickness of the metal film is less than 1 nm, it is difficult to form the metal film uniformly. Secondly, in order to suppress depletion of the gate electrode, the thickness of the metal film is preferably 1 nm or more. When the thickness of the metal film is less than 1 nm, the gate electrode is easily depleted, and the effective thickness of the gate insulating film increases due to the depletion of the gate electrode. Therefore, the lower limit of the film thickness of the metal film is preferably 1 nm from the viewpoint of film formation uniformity and depletion suppression.

  According to the present embodiment, in the p-type MIS transistor formed on the semiconductor substrate 10 having the (110) plane as the main surface, the thickness of the first metal film 14a of the first gate electrode 14A is 1 nm or more. And 10 nm or less (preferably 1 nm or more and 5 nm or less). Thereby, the hole mobility can be effectively increased and the performance of the p-type MIS transistor can be further improved.

  Furthermore, since the thickness of the first metal film 14a is 10 nm or less, an increase in EOT can be suppressed.

  In this embodiment, as shown in FIG. 3 (c), after the first and second outer side walls 19a and 19b are removed, they are integrally formed as shown in FIG. 4 (b). As the first and second insulating films 23a and 23b, a case where a base insulating film made of a silicon nitride film is formed by plasma CVD, for example, has been described as a specific example. However, the present invention is not limited to this. is not.

  First, for example, after removing the first and second outer sidewalls, a base insulating film is formed as the first insulating film, while the gate of the channel region in the second active region is used as the second insulating film. A stress insulating film that generates tensile stress in the long direction may be formed. Here, as a specific example of the method of forming the stress insulating film, a silicon nitride film containing a large amount of hydrogen is deposited by, for example, a plasma CVD method, and then the hydrogen contained in the silicon nitride film is blown off by ultraviolet irradiation, thereby causing stress. A method of forming an insulating film is given.

  In this case, a tensile stress can be applied in the gate length direction of the channel region in the second active region by the stress insulating film, so that the performance of the n-type MIS transistor can be improved.

  In addition, since the stress insulating film is formed after the removal of the second outer side wall, the stress insulating film can be formed as thick as the second outer side wall is removed. A tensile stress can be effectively applied in the gate length direction of the channel region.

  Furthermore, since the stress insulating film is formed after the removal of the second outer side wall, the stress insulating film is formed as close to the channel region in the second active region as the second outer side wall is removed. Therefore, tensile stress can be effectively applied in the gate length direction of the channel region in the second active region.

  Second, for example, after removing the first and second outer sidewalls, a first stress insulating film that generates compressive stress in the gate length direction of the channel region in the first active region is used as the first insulating film. On the other hand, a second stress insulating film that generates a tensile stress in the gate length direction of the channel region in the second active region may be formed as the second insulating film.

  In this way, the same effect as in the first example can be obtained.

  Furthermore, since the compressive stress can be applied in the gate length direction of the channel region in the first active region by the first stress insulating film, the performance of the p-type MIS transistor can be improved.

  In addition, since the first stress insulating film is formed after the removal of the first outer side wall, the first stress insulating film can be formed thicker by the amount removed of the first outer side wall. A compressive stress can be effectively applied in the gate length direction of the channel region in the first active region.

  Further, since the first stress insulating film is formed after the removal of the first outer side wall, the first stress insulating film is removed from the channel region in the first active region by the amount removed of the first outer side wall. Therefore, compressive stress can be effectively applied in the gate length direction of the channel region in the first active region.

As specific examples of the metal oxide of the high dielectric constant film included in the gate insulating film forming film 13 in this embodiment, for example, hafnium oxide (HfO ₂ ), hafnium silicate (HfSiO), nitrided hafnium silicate (HfSiON), etc. And oxides containing tantalum (Ta), zirconium (Zr), titanium (Ti), aluminum (Al), scandium (Sc), yttrium (Y), lanthanum (La), and the like.

  In the present embodiment, a polysilicon film is used as the silicon film forming film 15. However, instead of this, for example, an amorphous silicon film or a silicon film may be used.

  In this embodiment, Ni is used as the material for the silicide metal film. However, instead of this, a metal for silicide such as platinum, cobalt, titanium, and tungsten may be used.

(Second Embodiment)
A semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. The semiconductor device and the manufacturing method thereof according to the second embodiment will be described mainly with respect to the differences from the semiconductor device according to the first embodiment and the manufacturing method thereof, and common points will be omitted as appropriate. I will explain.

  A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. 6 (a) to (c) and FIGS. 7 (a) to (c). FIG. 6A to FIG. 7C are cross-sectional views of main steps in the gate length direction showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps. 6 (a) to 7 (c), the same components as those in the first embodiment are shown in FIGS. 2 (a) to 4 (c) in the first embodiment. The same reference numerals as those in FIG.

  First, the same process as the process shown in FIG. 2A in the first embodiment is performed. As a result, a configuration similar to the configuration shown in FIG.

  Next, as shown in FIG. 6A, after the surface of the semiconductor substrate 10 is cleaned by, for example, diluted hydrofluoric acid treatment, the first active region 10a and the second active region 10b are formed by, for example, ISSG oxidation method. Then, a base film (not shown) made of a silicon oxide film having a film thickness of 0.8 nm to 1 nm is formed. Thereafter, a gate insulating film forming film 13 made of a high dielectric constant film having a film thickness of, for example, 2 nm is deposited on the base film by, eg, MOCVD or ALD.

  Thereafter, a second metal film formation film 27 made of tantalum nitride (TaN) having a film thickness of 5 nm, for example, is deposited on the gate insulating film formation film 13 by, for example, CVD, ALD, or sputtering. Thereafter, a resist pattern 28 that opens the pMIS region and covers the nMIS region is formed on the second metal film forming film 27 by photolithography.

  Next, as shown in FIG. 6B, using the resist pattern 28 as a mask, the portion formed in the pMIS region in the second metal film forming film 27 is removed by dry etching or wet etching. As a result, the upper surface of the portion formed in the pMIS region in the gate insulating film forming film 13 is exposed, while the second metal film forming film 27 is formed on the portion formed in the nMIS region in the gate insulating film forming film 13. To remain. Thereafter, the resist pattern 28 is removed.

  In this way, the second metal is formed on the gate insulating film forming film 13 on the second active region 10b (that is, the portion formed on the second active region 10b in the gate insulating film forming film 13). A film forming film 27 is formed.

  Thereafter, the first metal made of, for example, TiN is formed on the portion of the gate insulating film forming film 13 formed in the pMIS region and the second metal film forming film 27 by, for example, CVD, ALD, or sputtering. A film forming film 14 is deposited. At this time, the first metal film forming film 14 has a film thickness of, for example, 1 nm or more and 10 nm or less (preferably, for example, 1 nm or more and 5 nm or less).

  In this way, the gate insulating film forming film 13 on the first active region 10a (that is, the portion formed on the first active region 10a in the gate insulating film forming film 13) and the second metal film formation are formed. A first metal film formation film 14 is formed on the film 27.

  Next, as shown in FIG. 6C, a silicon film forming film 15 made of, for example, a polysilicon film having a thickness of 100 nm is deposited on the first metal film forming film 14 by, eg, CVD.

  Next, as shown in FIG. 7A, a resist pattern (not shown) having a gate pattern shape is formed on the silicon film forming film 15 by photolithography. Thereafter, the silicon film formation film 15, the first metal film formation film 14, the second metal film formation film 27, and the gate insulating film formation film 13 are sequentially patterned by dry etching using the resist pattern as a mask. Thus, the first gate insulating film 13a, the first metal film 14a, and the first silicon film 15a are sequentially formed on the first active region 10a. At the same time, a second gate insulating film 13b, a second metal film 27b, a third metal film 14bx, and a second silicon film 15b are sequentially formed on the second active region 10b. Thereafter, the resist pattern is removed.

  In this manner, the first gate insulating film 13a and the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a are formed on the first active region 10a. At the same time, on the second active region 10b, a second gate insulating film 13b, a second gate electrode 27B made of the second metal film 27b, the third metal film 14bx, and the second silicon film 15b, Form.

  Next, as shown in FIG. 7B, a first offset spacer 16a is formed on the side surfaces of the first gate insulating film 13a and the first gate electrode 14A. At the same time, a second offset spacer 16b is formed on the side surfaces of the second gate insulating film 13b and the second gate electrode 27B. Thereafter, a p-type source / drain region 17a having a relatively shallow junction depth is formed below the side of the first gate electrode 14A in the first active region 10a. On the other hand, an n-type source / drain region 17b having a relatively shallow junction depth is formed below the side of the second gate electrode 27B in the second active region 10b. Thus, the same process as the process shown in FIG. 3A in the first embodiment is performed.

  Thereafter, the same steps as those shown in FIGS. 3B to 3C and FIGS. 4A to 4C in the first embodiment are sequentially performed to obtain the configuration shown in FIG. 7C.

  As described above, the semiconductor device according to the present embodiment, that is, the p-type MIS transistor PTr having the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a, and the second metal A semiconductor device including the n-type MIS transistor NTr having the second gate electrode 27B made of the film 27b, the third metal film 14bx, and the second silicon film 15b can be manufactured.

  Hereinafter, differences in configuration between the present embodiment and the first embodiment will be described.

  In the first embodiment, as shown in FIG. 4C, the second gate electrode 14B includes a second metal film 14b made of, for example, TiN, and a second silicon film 15b made of, for example, a polysilicon film. Consists of. The second metal film 14b in contact with the second gate insulating film 13b has the same film thickness as the first metal film 14a in contact with the first gate insulating film 13a, and the same metal as the first metal film 14a. Made of material.

  On the other hand, in the present embodiment, as shown in FIG. 7C, the second gate electrode 27B includes a second metal film 27b made of TaN, for example, and a third metal film 14bx made of TiN, for example. For example, a second silicon film 15b made of a polysilicon film. The second metal film 27b in contact with the second gate insulating film 13b is made of a metal material different from the first metal film 14a in contact with the first gate insulating film 13a (in other words, the second metal film 27b is The work function is different from that of the first metal film 14a). The third metal film 14bx has the same film thickness as the first metal film 14a and is made of the same metal material as the first metal film 14a.

  Thus, the metal material of the metal film in contact with the second gate insulating film 13b differs between the present embodiment and the first embodiment (first embodiment: TiN, second embodiment: TaN). The work function of TaN has a work function suitable for an n-type MIS transistor compared to the work function of TiN. Therefore, in this embodiment, the performance of the n-type MIS transistor NTr can be improved as compared with the first embodiment.

  According to this embodiment, the same effect as that of the first embodiment can be obtained.

  Furthermore, since the metal material (for example, TaN) having a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film 27b, the performance of the n-type MIS transistor can be improved.

(Third embodiment)
A semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings. The semiconductor device and the manufacturing method thereof according to the third embodiment will be described mainly with respect to differences from the semiconductor device according to the above-described first embodiment and the manufacturing method thereof, and common points will be omitted as appropriate. I will explain.

  8A to 8C, FIGS. 9A to 9C, and FIGS. 10A to 10C are described below with respect to a method for manufacturing a semiconductor device according to the third embodiment of the present invention. The description will be given with reference. FIG. 8A to FIG. 10C are cross-sectional views of relevant steps in the gate length direction showing the semiconductor device manufacturing method according to the third embodiment of the present invention in the order of steps. 8 (a) to 10 (c), the same constituent elements as those in the first embodiment are shown in FIGS. 2 (a) to 4 (c) in the first embodiment. The same reference numerals as those in FIG.

  First, steps similar to those shown in FIGS. 2A to 2B in the first embodiment are sequentially performed. As a result, a configuration similar to the configuration shown in FIG.

  Next, as shown in FIG. 8A, a resist pattern (not shown) having a gate pattern shape is formed on the silicon film formation film by photolithography. Thereafter, using the resist pattern as a mask, the silicon film forming film, the first metal film forming film, and the gate insulating film forming film are sequentially patterned by dry etching. Thus, the first gate insulating film 13a, the first metal film 14a, and the first silicon film 15a are sequentially formed on the first active region 10a. At the same time, a second gate insulating film 13b, a dummy metal film 14by, and a dummy silicon film 15by are sequentially formed on the second active region 10b. Thereafter, the resist pattern is removed.

  In this manner, the first gate insulating film 13a and the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a are formed on the first active region 10a. At the same time, a second gate insulating film 13b and a dummy gate electrode 14BY composed of a dummy metal film 14by and a dummy silicon film 15by are formed on the second active region 10b.

  Next, the same steps as those shown in FIGS. 3A to 4A in the first embodiment are sequentially performed, and then, as shown in FIG. First and second insulating films 23a and 23b made of, for example, a 50 nm-thickness silicon nitride film are deposited on the entire surface of the substrate 10 (Note that the first insulating film 23a and the second insulating film 23b are integrally formed. Formed).

  Next, as shown in FIG. 8C, a first interlayer insulating film 24 made of a silicon oxide film is deposited on the first and second insulating films 23a and 23b by, eg, CVD. Thereafter, for example, by CMP, the first interlayer insulating film is exposed until the upper surfaces of the portions formed on the third and fourth metal silicide films 22a and 22b in the first and second insulating films 23a and 23b are exposed. 24 is removed by polishing. After that, the first interlayer insulating film 24, the first and second insulating films 23a, 23b, the third, and the third are continuously grown by CMP until the upper surfaces of the first silicon film 15a and the dummy silicon film 15by are exposed. The fourth metal silicide films 22a and 22b, the first and second offset spacers 16a and 16b, and the first and second inner sidewalls 18a and 18b are removed by polishing.

  Next, as shown in FIG. 9A, a resist pattern 29 that covers the pMIS region and opens the nMIS region is formed on the semiconductor substrate 10. Thereafter, using the resist pattern 29 as a mask, the dummy metal film 14by, the second offset spacer 16b, the second inner sidewall 18b, the second insulating film 23b, and the first interlayer insulating film 24 are selectively dried. The dummy silicon film 15by in the dummy gate electrode 14BY is removed using an etching method or a wet etching method.

  Next, as shown in FIG. 9B, using the resist pattern 29 as a mask, the second gate insulating film 13b, the second offset spacer 16b, the second inner sidewall 18b, and the second insulating film 23b are used. Then, the dummy metal film 14by in the dummy gate electrode 14BY is removed by using a wet etching method having selectivity with the first interlayer insulating film 24. Thereafter, the resist pattern 29 is removed.

  In this manner, the dummy silicon film 15by and the dummy metal film 14by in the dummy gate electrode 14BY are sequentially removed to form a recess 30 in which the second gate insulating film 13b is exposed on the bottom surface.

  Next, as shown in FIG. 9C, the second metal film made of TaN, for example, is embedded in the entire surface of the semiconductor substrate 10 by, for example, the CVD method, the ALD method, or the sputtering method. A formation film 31 is deposited.

  Next, as shown in FIG. 10A, the second metal film forming film 31 is removed by, for example, a CMP method or an etch back method until the upper surface of the first interlayer insulating film 24 is exposed. Thereby, the second metal film 31 b is formed in the recess 30.

  In this manner, the second gate electrode 31B made of the second metal film 31b is formed on the second gate insulating film 13b.

  Next, as shown in FIG. 10B, after removing a natural oxide film (not shown) formed on the upper surface of the first silicon film 15a, the entire surface of the semiconductor substrate 10 is formed by sputtering, for example. For example, a metal film for silicide (not shown) made of Ni having a thickness of 10 nm is deposited. Thereafter, the Si of the first silicon film 15a and Ni of the metal film for silicide are reacted by, for example, the first RTA process under a nitrogen atmosphere at 320 ° C., and the upper part of the first silicon film 15a A metal silicide film 32 made of nickel silicide is formed. Thereafter, the semiconductor substrate 10 is immersed in an etching solution made of a mixed solution of sulfuric acid and hydrogen peroxide. Thus, the first interlayer insulating film 24, the first and second insulating films 23a and 23b, the first and second inner sidewalls 18a and 18b, and the first and second offset spacers 16a in the metal film for silicide. , 16b and the like (that is, unreacted portions in the silicide metal film) are removed. Thereafter, the silicide composition ratio of the metal silicide film 32 is stabilized by the second RTA process under a temperature (for example, 550 ° C.) higher than the temperature in the first RTA process.

  Next, as shown in FIG. 10C, the second interlayer insulating film is formed on the first interlayer insulating film 24 so as to cover the first and second gate electrodes 14A and 31B by, for example, the CVD method. After depositing 33, the surface of the second interlayer insulating film 33 is planarized by, eg, CMP.

  After that, the first metal film 23a, the first interlayer insulating film 24, and the second interlayer insulating film 33 are formed on the first metal film 23a, the first interlayer insulating film 24, and the second metal film by dry etching in the same manner as in the method of manufacturing a semiconductor device having a normal MIS transistor. A first contact hole 25a exposing the upper surface of the silicide film 21a is formed. At the same time, a second contact hole 25b exposing the upper surface of the second metal silicide film 21b is formed in the second insulating film 23b, the first interlayer insulating film 24, and the second interlayer insulating film 33. Thereafter, first and second contact plugs 26a and 26b are formed in the first and second contact holes 25a and 25b, in which a conductive film is buried via a barrier metal film. Thereafter, metal wiring (not shown) that is electrically connected to the first and second contact plugs 26 a and 26 b is formed on the second interlayer insulating film 33.

  As described above, the semiconductor device according to the present embodiment, that is, the p-type MIS transistor PTr having the first gate electrode 14A composed of the first metal film 14a and the first silicon film 15a, and the second metal A semiconductor device including the n-type MIS transistor NTr having the second gate electrode 31B made of the film 31b can be manufactured.

  Hereinafter, differences in configuration between the present embodiment and the first embodiment will be described.

  In the first embodiment, as shown in FIG. 4C, the first insulating film 23a is formed on the first inner side wall 18a in the first active region 10a from the upper surface of the first gate electrode 14A. It is formed over the upper surface of the region located on the side of. Similarly, the second insulating film 23b is formed so as to extend from the upper surface of the second gate electrode 14B to the upper surface of the region located on the side of the second inner sidewall 18b in the second active region 10b. Has been.

  On the other hand, in this embodiment, as shown in FIG. 10C, the first insulating film 23a is formed on the first inner side wall 18a from the first inner side in the first active region 10a. It is formed across the upper surface of the region located on the side of the sidewall 18a. Similarly, the second insulating film 23b extends from the surface of the second inner side wall 18b to the upper surface of the region located on the side of the second inner side wall 18b in the second active region 10b. Is formed.

  In the first embodiment, as shown in FIG. 4C, the second gate electrode 14B includes a second metal film 14b made of, for example, TiN, and a second silicon film 15b made of, for example, a polysilicon film. Consists of. The second metal film 14b in contact with the second gate insulating film 13b has the same film thickness as the first metal film 14a in contact with the first gate insulating film 13a, and the same metal as the first metal film 14a. Made of material.

  On the other hand, in the present embodiment, as shown in FIG. 10C, the second gate electrode 31B is made of the second metal film 31b made of TaN, for example. The second metal film 31b in contact with the second gate insulating film 13b is made of a metal material different from the first metal film 14a in contact with the first gate insulating film 13a (in other words, the second metal film 31b is The work function is different from that of the first metal film 14a). The film thickness T31b of the second metal film 31b is larger than the total film thickness obtained by adding the film thickness T14a of the first metal film 14a and the film thickness T15a of the first silicon film 15a (T31b> T14a + T15a).

  Thus, the metal material of the metal film in contact with the second gate insulating film 13b is different between the present embodiment and the first embodiment (first embodiment: TiN, third embodiment: TaN). In addition, the second gate electrode 31B in the present embodiment is made of only a metal film, whereas the second gate electrode 14B in the first embodiment is made of a metal film and a silicon film.

  Here, the second gate electrode 31B made of only the second metal film 31b is formed as follows. As shown in FIG. 8A, the silicon film forming film, the first metal film forming film, and the gate insulating film forming film are sequentially patterned to form the second gate insulating film 13b, the dummy metal film 14by, and the dummy silicon. A dummy gate electrode 14BY made of the film 15by is formed. Thereafter, as shown in FIG. 9B, the dummy silicon film 15by and the dummy metal film 14by in the dummy gate electrode 14BY are sequentially removed to form the recesses 30. Thereafter, as shown in FIG. 10A, a second metal film 31b is formed in the recess 30 to form a second gate electrode 31B made of only the second metal film 31b.

  In addition to the above method, the following method can be used as a method for forming a gate electrode made of only a metal film. The metal film forming film and the gate insulating film forming film are sequentially patterned to form a gate insulating film and a gate electrode made of only the metal film. However, this method has the following problems. In general, it is difficult to pattern a metal film forming film with higher accuracy than a silicon film forming film. Therefore, in this method, since the metal film forming film is relatively thick, the gate electrode cannot be formed with high accuracy.

  On the other hand, in this embodiment, since the first metal film forming film is relatively thin, the dummy gate electrode 14BY can be formed with high accuracy. As a result, the second metal film is formed in the concave portion (that is, the concave portion formed with high precision) 30 formed by sequentially removing the dummy silicon film 15by and the dummy metal film 14by in the dummy gate electrode 14BY formed with high precision. 31b can be formed. Therefore, the second gate electrode 31B made of the second metal film 31b can be formed with high accuracy.

  According to this embodiment, the same effect as that of the first embodiment can be obtained.

  In addition, since the metal material (for example, TaN) having a work function suitable for the n-type MIS transistor can be used as the metal material of the second metal film 31b, the performance of the n-type MIS transistor can be improved. (That is, the same effect as in the second embodiment can be obtained).

  Furthermore, since the thickness of the first metal film forming film is relatively small, the dummy gate electrode 14BY can be formed with high accuracy. Thereby, the dummy metal film 14by and the dummy silicon film 15by in the dummy gate electrode 14BY formed with high precision can be replaced with the second metal film 31b. Therefore, the second gate electrode 31B made of the second metal film 31b can be formed with high accuracy.

  In this embodiment, after forming the second gate electrode 31B as shown in FIG. 10A, a metal silicide film is formed on the first silicon film 15a as shown in FIG. 10B. As shown in FIG. 10C, the second interlayer insulating film 33 and the first and second contact plugs 26a and 26b are formed as a specific example. The present invention is not limited to this.

  For example, after forming the second gate electrode, the second interlayer insulating film and the first and second contact plugs may be formed without forming the metal silicide film on the first silicon film. In this case, the thickness of the second metal film is equal to the total thickness obtained by adding the thickness of the first metal film and the thickness of the first silicon film.

  The present invention can further improve the performance of a p-type MIS transistor in a p-type MIS transistor formed on a semiconductor substrate having a (110) plane as a main surface. It is useful for the manufacturing method.

DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 10a 1st active region 10b 2nd active region 11 Element isolation region 12a N-type well region 12b P-type well region 13 Gate insulating film formation film 13a 1st gate insulating film 13b 2nd gate insulating film 14 First metal film formation film 14a First metal film 14b Second metal film 15 Silicon film formation film 15a First silicon film 15b Second silicon film 14A First gate electrode 14B Second gate electrode 16a First One offset spacer 16b Second offset spacer 17a Shallow p-type source / drain region 17b Shallow n-type source / drain region 18a First inner side wall 18b Second inner side wall 19a First outer side wall 19b Second outer side Side wall 19A First side wall 19B Second side Wall 20a Deep p-type source / drain region 20b Deep n-type source / drain region 21a First metal silicide film 21b Second metal silicide film 22a Third metal silicide film 22b Fourth metal silicide film 23a First insulating film 23b 2nd insulating film 24 1st interlayer insulating film 25a 1st contact hole 25b 2nd contact hole 26a 1st contact plug 26b 2nd contact plug 27 2nd metal film formation film 27b 2nd metal film 14bx third metal film 27B second gate electrode 28 resist pattern 14by dummy metal film 15by dummy silicon film 14BY dummy gate electrode 29 resist pattern 30 recess 31 second metal film formation film 31b second metal film 31B second Gate electrode 32 Metal silicidation 33 Second interlayer insulating film

Claims (17)

A semiconductor device comprising a p-type MIS transistor formed on a semiconductor substrate having a (110) plane as a main surface,
The p-type MIS transistor is
A first gate insulating film formed on a first active region in the semiconductor substrate;
A first gate electrode formed on the first gate insulating film and comprising a first metal film and a first silicon film formed on the first metal film;
The semiconductor device according to claim 1, wherein the first metal film has a thickness of 1 nm or more and 10 nm or less. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first metal film has a thickness of 1 nm or more and 5 nm or less. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the first gate insulating film includes a high dielectric constant film made of a metal oxide. The semiconductor device according to any one of claims 1 to 3,
A first offset spacer having an I-shaped cross-section formed on a side surface of the first gate electrode;
A first sidewall having an L-shaped cross-section formed on the side surface of the first gate electrode via the first offset spacer;
A first insulating film formed across the upper surface of a region located on the side of the first sidewall in the first active region from the surface of the first sidewall; A semiconductor device. The semiconductor device of any one of Claims 1-4 WHEREIN:
The semiconductor device further includes an n-type MIS transistor formed on the semiconductor substrate,
The n-type MIS transistor is
A second gate insulating film formed on a second active region in the semiconductor substrate;
And a second gate electrode having a second metal film formed on the second gate insulating film. The semiconductor device according to claim 5,
The second gate electrode includes the second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film,
The first metal film and the second metal film have the same film thickness and are made of the same metal material. The semiconductor device according to claim 5,
The second gate electrode includes the second metal film formed on the second gate insulating film, a third metal film formed on the second metal film, and the third metal film. A second silicon film formed on the metal film,
The first metal film and the second metal film are made of different metal materials,
The semiconductor device, wherein the first metal film and the third metal film have the same film thickness and are made of the same metal material. The semiconductor device according to claim 5,
The second gate electrode is composed of the second metal film formed on the second gate insulating film,
The first metal film and the second metal film are made of different metal materials,
The film thickness of the second metal film is equal to or greater than the total film thickness obtained by adding the film thickness of the first metal film and the film thickness of the first silicon film. A semiconductor device characterized by the above. The semiconductor device according to any one of claims 5, 7, and 8,
The semiconductor device according to claim 1, wherein the first metal film and the second metal film have different work functions. The semiconductor device according to any one of claims 5 to 9,
The semiconductor device according to claim 1, wherein the first gate insulating film and the second gate insulating film include high dielectric constant films made of the same metal oxide. The semiconductor device of any one of Claims 5-10,
A second offset spacer having an I-shaped cross-section formed on a side surface of the second gate electrode;
A second sidewall having an L-shaped cross-section formed on the side surface of the second gate electrode via the second offset spacer;
And a second insulating film formed across the upper surface of the region located on the side of the second sidewall in the second active region from the surface of the second sidewall. A semiconductor device. The semiconductor device according to claim 11,
The semiconductor device, wherein the second insulating film is a stress insulating film that generates a tensile stress in the gate length direction of the channel region in the second active region. A method of manufacturing a semiconductor device including a p-type MIS transistor formed in a first active region in a semiconductor substrate having a (110) plane as a main surface,
Forming a gate insulating film forming film on the first active region in the semiconductor substrate;
A step (b) of forming a first metal film forming film on the gate insulating film forming film;
Forming a silicon film formation film on the first metal film formation film (c);
By sequentially patterning the silicon film formation film, the first metal film formation film, and the gate insulation film formation film, a first gate insulation made of the gate insulation film formation film is formed on the first active region. And (d) forming a film and a first metal film made of the first metal film forming film and a first gate electrode made of the first silicon film made of the silicon film forming film,
The method of manufacturing a semiconductor device, wherein the first metal film forming film has a thickness of 1 nm or more and 10 nm or less. In the manufacturing method of the semiconductor device according to claim 13,
The method of manufacturing a semiconductor device, wherein the first metal film forming film has a thickness of 1 nm or more and 5 nm or less. In the manufacturing method of the semiconductor device according to claim 13 or 14,
The semiconductor device further includes an n-type MIS transistor formed in a second active region in the semiconductor substrate,
The step (a) includes a step of forming the gate insulating film forming film on the second active region in the semiconductor substrate,
In the step (d), the gate insulating film forming film is formed on the second active region by sequentially patterning the silicon film forming film, the first metal film forming film, and the gate insulating film forming film. Forming a second gate insulating film comprising: a second metal film comprising the first metal film forming film; and a second gate electrode comprising the second silicon film comprising the silicon film forming film. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 13 or 14,
The semiconductor device further includes an n-type MIS transistor formed in a second active region in the semiconductor substrate,
The step (a) includes a step of forming the gate insulating film forming film on the second active region in the semiconductor substrate,
A step (e) of forming a second metal film forming film on the gate insulating film forming film on the second active region after the step (a) and before the step (b); Prepared,
The step (b) includes a step of forming the first metal film forming film on the gate insulating film forming film on the first active region and on the second metal film forming film,
In the step (d), the second active region is formed by sequentially patterning the silicon film forming film, the first metal film forming film, the second metal film forming film, and the gate insulating film forming film. A second gate insulating film made of the gate insulating film forming film, a second metal film made of the second metal film forming film, and a third metal film made of the first metal film forming film. And a step of forming a second gate electrode made of the second silicon film made of the silicon film forming film. In the manufacturing method of the semiconductor device according to claim 13 or 14,
The semiconductor device further includes an n-type MIS transistor formed in a second active region in the semiconductor substrate,
The step (a) includes a step of forming the gate insulating film forming film on the second active region in the semiconductor substrate,
In the step (d), the gate insulating film forming film is formed on the second active region by sequentially patterning the silicon film forming film, the first metal film forming film, and the gate insulating film forming film. Forming a second gate insulating film made of, a dummy metal film made of the first metal film forming film, and a dummy silicon film made of the silicon film forming film,
A step (e) of removing the dummy silicon film and the dummy metal film after the step (d);
A step (f) of forming a second gate electrode made of a second metal film on the second gate insulating film after the step (e) is further provided. Production method.

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