JP2012099549A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device with high yield and high performance by avoiding complicated steps and obtaining high effective work function value.SOLUTION: P-type source/drain regions 25p are formed on both sides of a dummy electrode 22 in an n-type active region 13 by introducing p-type impurity ions into the n-type active region 13 using the dummy electrode 22 as a mask, and then the formed source/drain regions 25 are heat-treated. After the heat treatment, an interlayer insulating film 26 is formed on the n-type active region 13 so as to cover the dummy electrode 22. The dummy electrode 22 is exposed from the formed interlayer insulating film 26, and then the exposed dummy electrode 22 is removed. Subsequently, a second metal electrode 27 is selectively formed in a recess 26a from which the dummy electrode 22 in the interlayer insulating film 26 is removed.

Description

  The present invention relates to a method for manufacturing a semiconductor device using a metal for a gate electrode.

In recent years, semiconductor devices are required to have low power consumption and high speed operation. In order to increase the speed of the semiconductor device, for example, a method of increasing the drive current of the MISFET by increasing the gate capacitance of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is employed. In order to increase the gate capacitance, it is necessary to reduce the distance between the substrate and the gate electrode by thinning the gate insulating film. In order to meet this requirement, the physical film thickness of the gate insulating film in the MISFET is currently reduced to about 2 nm when SiON (silicon oxynitride) is used. However, there is a problem that gate leakage increases only by reducing the thickness of the gate insulating film. Therefore, in order to suppress gate leakage while reducing the thickness of the gate insulating film, a high dielectric material such as an oxide containing Hf (hafnium) is used as the gate insulating film instead of a silicon oxide (SiO ₂ ) -based material. Use is under consideration.

Further, with the thinning of the gate insulating film, the gate electrode made of polycrystalline silicon (polysilicon) that has been used until now has a problem that the gate electrode is depleted and the gate capacitance is reduced. The amount of decrease in the gate capacitance due to depletion of the gate electrode corresponds to increasing the film thickness by about 0.5 nm when converted to the film thickness of the gate insulating film made of, for example, silicon oxide (SiO ₂ ). If depletion of the gate electrode can be suppressed, the effective thickness of the gate insulating film can be reduced without increasing gate leakage. In the case where the gate insulating film is SiO ₂ , if the film thickness is reduced by 0.1 nm, the leakage current increases to 10 times or more compared to before the thinning. For this reason, the effect of reducing the thickness of the effective gate insulating film by suppressing the depletion of the gate electrode is extremely large.

  Therefore, in order to suppress or avoid depletion of the gate electrode, studies have been made to replace the constituent material of the gate electrode with a metal that does not cause depletion from polycrystalline silicon. However, polycrystalline silicon can form an impurity level by adding an impurity, and can separately form a p-type MISFET electrode and an n-type MISFET electrode. On the other hand, in the case of a gate electrode using a metal, it cannot be made differently by adding impurities as in the case of polycrystalline silicon. For this reason, a metal having a work function (WF) value substantially corresponding to the center of the work function (WF) value of the p-side region and the work function (WF) value of the n-side region is converted into a p-type MISFET electrode and an n-type electrode. By using it as a common material for the MISFET electrode, the p-type MISFET and the n-type MISFET are designed to have the same threshold voltage Vt.

  In recent years, since MISFETs are required to operate at higher speeds, it is indispensable to lower the threshold voltage. Each of the p-type MISFET electrode and the n-type MISFET electrode has a work function close to the band edge of silicon ( It has become necessary to have a (WF) value. The band edge here means a high WF value close to the work function value (= about 5.2 eV) of the upper part (top edge) of the valence band of silicon in the p-side region, and the n-side region. Is a low WF value close to the work function value (= about 4.1 eV) at the bottom (bottom edge) of the conduction band of silicon. For this reason, a semiconductor device in which a metal having a WF value substantially corresponding to the center of the WF value in the p-side region and the WF value in the n-side region is used as an electrode material for the p-type MISFET and the n-type MISFET is no longer practical. It is gone.

  At present, a search for metal materials that can be used as gate electrodes of p-type MISFETs and n-type MISFETs has been actively conducted. However, it has become clear that even if a material exhibits an appropriate WF value at room temperature, the appropriate WF value fluctuates after a high temperature treatment such as activation of the source and drain.

JP 2010-098157 A JP 2009-194352 A JP 2010-135735 A

S. Kubicek et al, "IEDM Tech Dig.", 2007, p. 49 P. D. Kirsch, "IEDM", 2006, p. 629

  At present, mainly two countermeasures have been taken against the problem that the WF value of the metal used for the gate electrode fluctuates after the high temperature treatment.

  The first countermeasure is to form a MISFET by forming polysilicon or a silicon oxide-based material as a dummy electrode in the gate electrode formation region where the metal electrode is formed, and after performing the necessary high-temperature heat treatment, the dummy electrode is removed. Then, a metal electrode is formed on the removed portion. Since the gate structure is formed last in this way, it is often called a gate last method (replacement gate, damascene gate). In the gate last method, after processing (patterning) the electrode, an interlayer insulating film is formed so as to cover the dummy gate, and then the interlayer insulating film is removed while being planarized by CMP (Chemical Mechanical Polish) etc. In many cases, so-called cueing is performed to expose the dummy gate portion. Thereafter, the dummy gate is removed and a desired metal electrode is deposited. Therefore, in order to obtain a work function (WF) value required for each of the p-type MISFET and the n-type MISFET, it is necessary to deposit different electrode materials for the p-type MISFET and the n-type MISFET. For this reason, the dummy gate is removed over the entire surface, a metal electrode for p-type MISFET (or n-type MISFET) is deposited on the entire surface, and then an electrode formed in the n-type MISFET region (or p-type MISFET region) is deposited. Then, a metal electrode for n-type MISFET (or p-type MISFET) is deposited. As a result, the gate insulating film undergoes removal cleaning twice, and there is a high possibility that the gate insulating film will be damaged, resulting in fluctuations in electrical characteristics and deterioration in reliability of the MISFET.

  In Patent Document 1 described above, a method is shown in which the dummy gate structure is a two-layer structure of polysilicon (Si) and titanium nitride (TiN), and only the polysilicon portion is removed. Although this method can prevent the gate insulating film from slipping, in order to obtain an appropriate effective work function (eWF) value, the electrode material for the p-type MISFET and the electrode material for the n-type MISFET are respectively provided in the respective regions. Need to be formed. Here, the effective work function (eWF) is an effective work function acting on the Si substrate side of the MISFET. The Vt (threshold voltage) or Vfb (flat band voltage) of the MISFET is theoretically determined from the work function of the electrode metal and the physical constants and impurities of Si constituting the substrate. It fluctuates due to the electric charge in the film and the influence of the dipole existing at the interface with the insulating film. Here, all the influences are not separated, and the value calculated as the work function of the electrode is called an effective work function. Therefore, it is necessary to deposit the entire surface of the first metal electrode, to remove the first metal electrode in some FETs, and to redeposit the second metal electrode in some FETs. . For this reason, film slippage of the first metal electrode cannot be avoided. Moreover, the dimension of the gate structure is getting smaller year by year, and it is 40 nm or less in the generation to which the metal gate is applied. Since the first metal electrode is embedded in the trench (recess) having a width of 40 nm or less, when removing the embedded first metal electrode, the first metal electrode remains at the bottom of the trench, Problems such as the occurrence of defective filling of the metal electrode 2 occur. For this reason, repeating the deposition and removal of the metal electrode twice directly leads to a decrease in yield.

  As a second countermeasure, a cap material for controlling or adjusting (modulating) an effective work function (eWF) value is deposited between the high dielectric film and the gate electrode, and the inside of the gate insulating film or the high dielectric film and the metal In this method, the eWF value is controlled by forming a dipole at the interface (see Non-Patent Document 1, for example). For example, lanthanum oxide (LaO) is known to have an effect of lowering the eWF value, and is expected as a cap material for forming a gate electrode of an n-type MISFET (see, for example, Non-Patent Document 2). Conversely, aluminum oxide (AlO) is known to have an effect of increasing the eWF value, and is expected as a cap material for forming a gate electrode of a p-type MISFET.

  Further, as described in the above-mentioned Patent Document 2, a complementary metal oxide semiconductor (CMOS) circuit using LaO and AlO is currently being developed. In this case, the method for forming the transistor is a method called a gate first method because the gate structure is formed before heat treatment as usual. In addition, in the case of a metal gate having a gate-first structure, a two-layer electrode in which polysilicon is deposited on a metal electrode is used for reasons such as consistency with a post-process flow constructed with a conventional polysilicon electrode. In many cases, this structure is called a MIPS (Metal Inserted Poly Silicon) structure.

  The gate-first method has fewer processing problems than the gate-last method, but it is extremely difficult to control the eWF value. In particular, the p-type MISFET has a large amount of metal material whose eWF value decreases after heat treatment, and aluminum oxide (AlO), which is a dipole forming material, has a low dielectric constant, and thus reduces the capacity of the gate insulating film. For this reason, there is a problem that a sufficiently high eWF value cannot be obtained, for example, the amount of AlO used cannot be increased to such an extent that a sufficient eWF value can be obtained.

  As described above, in the gate last method, there is a problem in the complexity of the manufacturing process, in particular, in the process of separately forming the p-type MISFET and the n-type MISFET in the ultrafine trench portion, and in the gate-first method, the WF The control of the value, especially the realization of the high eWF value of the p-type MISFET, is a major problem in the development of the metal gate CMOS.

  An object of the present invention is to solve the above-mentioned problems, avoid complicated processes, and obtain a high effective work function (eWF) value, thereby realizing a high-yield and high-performance semiconductor device. To do.

  In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device. First, patterning and forming a diffusion region and heat treatment are performed with a first metal electrode and a dummy electrode formed thereon, The dummy electrode is replaced with a second metal electrode.

  Specifically, the method for manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film forming film on a first conductivity type semiconductor region, and a first metal electrode forming on the gate insulating film forming film. A step of forming a film, a step of forming a dummy electrode formation film on the first metal electrode formation film, and patterning the dummy electrode formation film, the first metal electrode formation film, and the gate insulating film formation film Forming a dummy electrode from the dummy electrode forming film, forming a first metal electrode from the first metal electrode forming film, and forming a gate insulating film from the gate insulating film forming film; and using the dummy electrode as a mask, By introducing impurity ions of the second conductivity type into the semiconductor region, a diffusion region is formed in regions on both sides of the dummy electrode in the semiconductor region, and a heat treatment is performed on the formed diffusion region; A step of forming an interlayer insulating film on the semiconductor region so as to cover the dummy electrode; a step of exposing the dummy electrode from the formed interlayer insulating film; and a step of removing the dummy electrode exposed from the interlayer insulating film; And a step of selectively forming a second metal electrode in the recess from which the dummy electrode in the insulating film is removed.

  According to the semiconductor device manufacturing method of the present invention, the first metal electrode and the dummy electrode are formed on the gate insulating film, and in this state, the diffusion region is formed and heat treatment is performed. Thereafter, the dummy electrode is removed, and a second metal electrode is formed in the removed portion. Therefore, when the dummy electrode is removed, the gate insulating film is not exposed, so that the gate insulating film is not likely to be damaged such as a film slip. In addition, since the second metal electrode is formed after the heat treatment, the effective work function (eWF) value is not lowered particularly in the case of a p-type semiconductor device (p-type MISFET). Therefore, a complicated process can be avoided and a high eWF value can be obtained, so that a high yield and high performance semiconductor device can be realized.

  In the method for manufacturing a semiconductor device of the present invention, the first metal electrode may be made of titanium nitride.

  In the method for manufacturing a semiconductor device of the present invention, the second metal electrode may be made of titanium nitride.

  In the method for manufacturing a semiconductor device of the present invention, the gate insulating film may contain hafnium.

  In this case, the method for manufacturing a semiconductor device according to the present invention provides an aluminum film on the gate insulating film forming film between the step of forming the gate insulating film forming film and the step of forming the first metal electrode forming film. And forming a first cap film including the first metal electrode forming film on the first cap film, and the first cap film together with the first metal electrode forming film. Patterning may be performed.

  In this case, when the second conductivity type is p-type, the diffusion of aluminum into the gate insulating film increases the eWF value of the metal electrode, so that the characteristics of the p-type transistor are improved.

  In this case, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate insulating film forming film and a step of forming a first metal electrode forming film on the gate insulating film forming film. A step of forming a second cap film containing lanthanum, a step of diffusing lanthanum into the gate insulating film formation film by heating the second cap film, and removing the second cap film after heating. And a process.

  In this case, when the second conductivity type is n-type, lanthanum diffuses into the gate insulating film, thereby reducing the eWF value of the metal electrode, and the characteristics of the n-type transistor are improved.

  In the method for manufacturing a semiconductor device of the present invention, a solution comprising ammonia-hydrogen peroxide solution may be used in the step of removing the dummy electrode.

  In the method for manufacturing a semiconductor device of the present invention, the second metal electrode may be formed wider in the gate length direction than the first metal electrode.

  By the way, metals such as titanium nitride (TiN) have an effective work function (eWF) value dependent on the film thickness of the electrode, and the eWF value increases as the electrode film thickness increases, and the eWF value is It has been found that when heat treatment is applied, it decreases. Note that the film thickness dependency that the eWF value increases as the film thickness increases is not affected by the presence or absence of heat treatment.

  Furthermore, as a result of various experiments, the inventor of the present application has found that a metal electrode such as TiN can be deposited again on the metal electrode even if the eWF value is lowered by the heat treatment. The knowledge that eWF value rises has been obtained.

  FIG. 1 is a graph and a schematic diagram for explaining the above-mentioned knowledge, and represents the respective eWF values of metal electrodes made of titanium nitride (TiN) formed in five ways of treatments (a) to (e). Yes. When the heat treatment at 800 ° C. is applied to the eWF value of TiN having a thickness of 19 nm shown in treatment (a) and not annealed as in treatment (b), the eWF value of the heat-treated TiN is lowered. . However, as shown in the cases of the treatments (c) to (e), when TiN is deposited and annealed, and then TiN is deposited again, the eWF value in that case is the treatment (b) ) And higher. The amount of increase in the eWF value increases as the thickness of TiN deposited after annealing increases. Taking the process (e) as an example, a process of first depositing a TiN film having a thickness of 4 nm, subsequently performing annealing at 800 ° C., and then further depositing a TiN film having a thickness of 15 nm. Represents. Therefore, it can be seen from the treatment (e) that an eWF value that is substantially the same as TiN that is not annealed at a thickness of 19 nm can be obtained from the treatment (a).

  Utilizing this knowledge, for example, after constructing a metal gate CMOS that separates p-type MISFETs and n-type MISFETs by a gate-first method that adopts the MIPS structure, which is a method described in Patent Document 3 above. If the polysilicon film that is a dummy electrode is removed and replaced with an electrode material such as TiN that has not been annealed, the addition of the gate-last method without the complicated separate process of p-type MISFET and n-type MISFET Higher eWF values can be obtained. At this time, the eWF value of the n-type MISFET that requires a low eWF value also increases. However, the eWF value of the n-type MISFET is adjusted by e.g. lanthanum oxide (LaO) having a high dielectric constant and a large dipole effect. Is relatively easy. Therefore, it is possible to set the eWF value in anticipation of an improvement in the eWF value by depositing the second metal electrode.

  In addition, according to the present invention, by making the p-type and n-type MISFETs differently by the gate first method, the process complexity in the gate last method can be avoided. Furthermore, since the eWF value in each of the p-type and n-type MISFETs can be shifted in the overall high direction by the gate last method, it is possible to avoid a decrease in the eWF value due to high-temperature processing during the process.

  As described above, when the dummy electrode is removed, the second metal electrode is embedded in the MISFET without removing the previously formed first metal electrode, so that the gate insulating film can be used as a chemical. There is no direct exposure. Thereby, there is no deterioration in the reliability of the gate insulating film (defect generation at the atomic level of the film), and there is no threshold fluctuation of the p-type MISFET. Therefore, the eWF values of both the p-type MISFET and the n-type MISFET can be adjusted to appropriate values.

  According to the semiconductor device manufacturing method of the present invention, a high yield and high performance semiconductor device can be realized by avoiding complicated processes and obtaining a high effective work function (eWF) value.

FIG. 1 is a graph showing the value of effective work function (eWF) after each treatment for titanium nitride (TiN) for explaining the effect of the present invention. FIG. 2 is a schematic cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 3A to FIG. 3C are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 4A to FIG. 4C are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5A to FIG. 5C are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 6A to FIG. 6C are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 7A and FIG. 7B are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

(One embodiment)
An embodiment of the present invention will be described with reference to FIG.

  As shown in FIG. 2, the semiconductor device according to the present embodiment includes a complementary MIS (CMIS) having a p-type MISFET formed in the p-type transistor region 10p and an n-type MISFET formed in the n-type transistor region 10n. ) A semiconductor device having a structure.

  Specifically, for example, an n-type transistor region 10p is formed with an n-type by an element isolation region 12 made of shallow trench isolation (STI) formed on an upper portion of a semiconductor substrate 11 made of silicon (Si). An active region (n-well) 13 is defined, and a p-type active region (p-well) 14 is defined in the n-type transistor region 10n so as to be insulated from each other.

In the p-type transistor region 10p, on the n-type active region 13, a base film 15 made of silicon oxide (SiO ₂ ) or the like, a gate insulating film 16 made of a high dielectric, and a first film made of aluminum oxide (AlO). A first cap electrode 17 and a first metal electrode 21 and a second metal electrode 27 constituting a gate electrode 30 made of titanium nitride (TiN) or the like are sequentially stacked. Sidewalls 24 made of silicon oxide, silicon nitride, or the like are formed on both side surfaces of the gate electrode 30.

  A p-type extension region 23p is formed in a region on both sides of the gate electrode 30 above the n-type active region 13, and a p-type source / drain region 25p is provided in each region outside the extension region 23p. It is formed deeper than the region 23p and at a high concentration.

On the other hand, in the n-type transistor region 10n, on the p-type active region 14, a base film 15 made of silicon oxide (SiO ₂ ) or the like and a gate insulating film 16 made of a high dielectric material are both titanium nitride (TiN). The first metal electrode 21 and the second metal electrode 27 that constitute the gate electrode 30 made of or the like are sequentially laminated. Sidewalls 24 made of silicon oxide or the like are formed on both side surfaces of the gate electrode 30.

  An n-type extension region 23n is formed in a region on both sides of the gate electrode 30 above the p-type active region 14, and an n-type source / drain region 25n is provided in the region outside each extension region 23n. It is formed deeper than the region 23n and at a high concentration.

  Here, the gate insulating film 16 in both MISFETs is a hafnium oxide (HfO) -based high dielectric film containing hafnium silicon oxide (HfSiO) or oxynitride hafnium silicon (HfSiON).

  In the n-type MISFET, as will be described later, a second cap film made of lanthanum oxide (LaO) is formed on the gate insulating film 16, and the effective work function (eWF) value is obtained by subsequent thermal diffusion. Including La for adjustment. Note that in the n-type MISFET, the gate insulating film 16 does not contain La, and even if it contains it, the amount is extremely small.

  Further, as described above, in the MISFET according to the present embodiment, the metal portion of the gate electrode 30 has a two-layer structure, and the width in the gate length direction of the second metal electrode 27 of the upper layer is determined from the manufacturing method described below. The width of the lower first metal electrode 21 is larger than the width in the gate length direction.

  Hereinafter, a method of manufacturing the semiconductor device configured as described above will be described with reference to FIGS.

  First, as shown in FIG. 3A, an element isolation region 12 is selectively formed on a semiconductor substrate 11 made of silicon to form a p-type transistor region 10p and an n-type transistor region 10n. Thereafter, arsenic (As) ions or phosphorus (P) ions, which are n-type impurity ions, are implanted into the p-type transistor region 10 p in the semiconductor substrate 11 by lithography and ion implantation to form the n-type active region 13. To do. Subsequently, boron (B) ions that are p-type impurity ions are implanted into the n-type transistor region 10 n to form the p-type active region 14. The order of forming the n-type active region 13 and the p-type active region 14 is not particularly limited.

Subsequently, a base film 15 made of SiO ₂ having a thickness of about 1 nm is formed on the entire main surface of the semiconductor substrate 11. The base film 15 may be formed by a rapid thermal oxidation (RTO) method using oxygen gas or the like. Note that an RTO method using a gas species other than oxygen gas may be used, or a thermal oxidation method using a heating furnace may be used. Further, the base film 15 may be SiON instead of SiO ₂ , or may be so-called chemical oxide formed by immersing in an oxidizing chemical solution.

Subsequently, a gate insulating film forming film 16A made of a high dielectric material having a film thickness of about 1.7 nm is deposited on the base film 15 by a chemical vapor deposition (CVD) method or the like. Here, an HfSiO film having a composition ratio of Hf / (Hf + Si) of about 60% is used for the gate insulating film forming film 16A. Instead of the HfSiO film, hafnium oxide (HfO ₂ ) may be used, and furthermore, a high dielectric film in which the composition ratio value of Hf is changed from the above value may be used. Further, although the film thickness of the gate insulating film forming film 16A is 1.7 nm, it may be changed depending on the use of the semiconductor device or the capability required for the semiconductor device. Further, instead of hafnium (Hf), a high dielectric film containing other elements such as zirconium (Zr) may be used.

  Subsequently, the gate insulating film forming film 16A is made to be HfSiON by performing nitriding treatment using plasma on the gate insulating film forming film 16A made of HfSiO. Thereafter, annealing is performed in a nitrogen atmosphere at 1000 ° C., and the gate insulating film forming film 16A is baked. Here, the nitriding treatment for the gate insulating film forming film 16A is performed to such an extent that about 4 atm% of nitrogen is introduced into the gate insulating film forming film 16A. The concentration may be changed. The nitriding treatment for the gate insulating film forming film 16A may be performed after performing other treatment and immediately before the deposition of the metal electrode. Further, the baking annealing after the nitriding treatment was performed in a nitrogen atmosphere having a temperature of 1000 ° C., but the annealing temperature may be in the range of 800 ° C. to 1100 ° C. Not limited to.

  Subsequently, a first cap film forming film 17A made of AlO having a film thickness of 0.7 nm is formed on the gate insulating film forming film 16A that has been nitrided by physical vapor deposition (PVD). accumulate. Here, the PVD method is used for the first cap film forming film 17A, but an atomic layer deposition (ALD) method or a CVD method may be used. Further, the film thickness of the first cap film forming film 17A can be changed depending on the specification.

  Subsequently, an HM (hard mask) metal film 18 made of titanium nitride (TiN) having a thickness of about 5 nm is formed on the first cap film formation film 17A by a CVD method or the like.

  Next, as shown in FIG. 3B, a resist film 19 covering the p-type transistor region 10p is formed by lithography.

  Next, as shown in FIG. 3C, a portion of the HM metal film 18 formed in the n-type transistor region 10n is removed using the formed resist film 19 as a mask.

  Next, as shown in FIG. 4A, the resist film 19 is removed by thinner cleaning. Subsequently, a second cap film 20 made of LaO having a thickness of about 2 nm is deposited on the entire surface of the semiconductor substrate 11 by the PVD method. Here, the PVD method is used to form the second cap film 20, but an ALD method or a CVD method may be used. LaO is deposited about 2 nm, but can be changed depending on the specification.

  Next, as shown in FIG. 4B, the semiconductor substrate 11 on which the second cap film 20 is deposited is annealed so that the portion included in the n-type transistor region 10n in the gate insulating film formation film 16A. Spread lantern (La). The annealing temperature here is 700 ° C.

  Subsequently, as shown in FIG. 4C, the second cap film 20 remaining without being diffused in the gate insulating film forming film 16A is removed. The method for removing the second cap film 20 is not particularly limited. For example, the second cap film 20 may be cleaned for about 10 seconds using dilute hydrochloric acid (dHCl) obtained by diluting hydrochloric acid (concentration 37 mass%) 1000 times. The dilution ratio and cleaning time of hydrochloric acid may be appropriately changed according to the thickness of the second cap film 20, the heat treatment time, and the like. After removing the second cap film 20, the amount of La diffused and remaining in the gate insulating film forming film 16A is about 0.6 nm in terms of the film thickness of the second cap film 20 made of LaO. . The amount of La diffused into the gate insulating film forming film 16A can be controlled by the thickness of the second cap film 20 and the annealing temperature. That is, when the second cap film 20 is deposited thickly and the annealing temperature is lowered, the region becomes closer to the diffusion rate control, and therefore, the second cap film 20 is less affected by the deposited film thickness distribution of LaO. As a result, a relatively uniform La diffusion distribution can be obtained.

  On the other hand, the HM metal film 18 is formed on the gate insulating film forming film 16A in the p-type transistor region 10p. Accordingly, in the p-type transistor region 10p, the lanthanum (La) from the second cap film 20 diffuses only on the HM metal film 18 and does not diffuse into the gate insulating film formation film 16A. Thereby, a gate insulating film forming film 16A in which La is not diffused is formed in the p-type transistor region 10p. Even if La is contained, the amount is extremely small. Note that the annealing temperature and time may be appropriately changed according to the required effective work function (eWF) value, the composition and thickness of the gate insulating film forming film 16A, and the like.

Next, as shown in FIG. 5A, the HM metal film 18 made of TiN is removed. The removal of the HM metal film 18 may be performed by any method as long as it does not deteriorate the gate insulating film forming film 16A and can remove at least a region where La is diffused in the HM metal film 18. For example, when the HM metal film 18 is a TiN film and the second cap film 20 is a LaO film, it may be removed using hydrogen peroxide water (H ₂ O ₂ ). Alternatively, sulfuric acid / hydrogen peroxide / water mix (SPM) or ammonia hydroxide / hydrogen peroxide / water mix (APM) may be used.

  Next, as shown in FIG. 5B, the first metal electrode formation film 21A made of TiN and the dummy electrode formation film 22A made of polysilicon are sequentially formed on the entire surface of the semiconductor substrate 11 by CVD or the like. accumulate.

  Note that the first metal electrode formation film 21A and the HM metal film 18 are not limited to TiN. For example, a metal containing titanium (Ti) or tantalum (Ta) is preferable, and tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbide nitride (TaCN), or the like can be used instead of TiN. Further, the first metal electrode formation film 21A and the HM metal film 18 may be made of any material that can obtain an appropriate eWF value when combined with the first cap film formation film 17A and the second cap film 20. Other metal materials may be used.

  Next, as shown in FIG. 5C, in the p-type transistor region 10p, the dummy electrode formation film 22A and the first metal are formed by using a lithography method and a reactive ion etching (RIE) method. The electrode forming film 21A, the first cap film forming film 17A, the gate insulating film forming film 16A and the base film 15 are selectively etched and patterned. At the same time, in the n-type transistor region 10n, the dummy electrode forming film 22A, the first metal electrode forming film 21A, the gate insulating film forming film 16A, and the base film 15 are selectively etched and patterned. Thereby, in the p-type transistor region 10p, a dummy gate having the gate insulating film 16 including the base film 15 and the first cap film 17, the first metal electrode 21 made of TiN, and the dummy electrode 22 made of polysilicon. A structure is formed. Further, in the n-type transistor region 10n, a dummy gate structure including a gate insulating film 16 including a base film 15 into which La is introduced, a first metal electrode 21 made of TiN, and a dummy electrode 22 made of polysilicon. It is formed.

  Next, as shown in FIG. 6A, in the p-type transistor region 10p, for example, B ions, which are p-type impurity ions, are ion-implanted into the n-type active region 13 using the dummy electrode 22 as a mask. Thereby, p-type extension regions 23p are formed in regions on both sides of the dummy electrode 22 in the n-type active region 13. Subsequently, in the n-type transistor region 10n, for example, As ions or P ions, which are n-type impurity ions, are implanted into the p-type active region 14 using the dummy electrode 22 as a mask. As a result, n-type extension regions 23n are formed in regions on both sides of the dummy electrode 22 in the p-type active region 14. The order in which the extension regions 23p and 23n are formed is not particularly limited.

Subsequently, for example, a silicon oxide (SiO ₂ ) film is deposited on the entire surface of the semiconductor substrate 11 by a CVD method or the like, and the deposited SiO ₂ film is etched back to thereby each dummy gate structure including a gate insulating film. Sidewalls 24 made of SiO ₂ are formed on both side surfaces. Subsequently, in the p-type transistor region 10p, for example, B ions are ion-implanted into the n-type active region 13 using the dummy electrode 22 and the sidewall 24 as a mask. Thus, a p-type source / drain region 25p connected to the extension region 23p and having a high junction depth and a deep junction depth is formed in a region outside the sidewall 24 in the n-type active region 13. Subsequently, in the n-type transistor region 10n, for example, As ions or P ions are implanted into the p-type active region 14 using the dummy electrode 22 and the sidewall 24 as a mask. As a result, an n-type source / drain region 25n connected to the extension region 23n and having a high concentration and a deep junction depth is formed in a region outside the sidewall 24 in the p-type active region 14. The order of forming the source / drain regions 25p and 25n is not particularly limited.

  Subsequently, the formed extension regions 23p and 23n and source / drain regions 25p and 25n are annealed at a temperature of about 800 ° C. to activate the implanted impurity ions.

Next, as shown in FIG. 6B, TEOS (Tetra-Ethyl-Ortho-Silicate) is used as a silicon source so as to cover the dummy electrode 22 including the sidewalls 24 on the entire surface of the semiconductor substrate 11. An interlayer insulating film 26 made of silicon oxide (SiO ₂ ) is deposited. Here, a TEOS film having excellent step coverage is used for the interlayer insulating film 26, but a CVD-based SiO ₂ film other than the TEOS film may be used.

Next, as shown in FIG. 6C, the deposited interlayer insulating film 26 is polished by a chemical mechanical polishing (CMP) method or the like to expose the dummy electrode 22 made of polysilicon in each dummy gate structure. Thereafter, each dummy electrode 22 exposed from the interlayer insulating film 26 is selectively removed using, for example, ammonium hydroxide (NH ₃ liquid). As a result, a recess (gate trench) 26 a in which the first metal electrode 21 is exposed is formed in the interlayer insulating film 26. Here, the NH ₃ liquid is used to remove the dummy electrode 22, but other silicon solution such as low concentration APM may be used.

In the conventional gate last process, since the gate insulating film is exposed when the dummy electrode is removed, it is necessary to suppress film slippage of the gate insulating film. For this reason, usable chemical solutions such as NH ₃ solution are limited. However, as in the present embodiment, it is TiN constituting the first metal electrode 21 that is exposed after the dummy electrode 22 is removed. Therefore, it is possible to use a chemical solution having higher particle removability such as APM. Further, depending on the process, the dummy electrode 22 can be changed to silicon nitride (SiN) instead of polysilicon. At this time, the width of the recess 26 a formed in the interlayer insulating film 26 in the gate length direction may be larger than the width of the first metal electrode 21.

  Next, as shown in FIG. 7A, a second metal electrode formation film 27A made of TiN is deposited on the entire surface of the interlayer insulating film 26 so as to fill the recesses 26a by the CVD method or the like. Although TiN is used for the second metal electrode formation film 27A, it is not limited to TiN. For example, another metal material whose effective work function (eWF) value increases as shown in FIG. 1 due to the second deposition not subjected to the annealing treatment may be used.

  Next, as shown in FIG. 7B, the excess second metal electrode formation film 27A deposited on the interlayer insulating film 26 is polished and removed by a CMP method or the like, respectively. A MISFET having a gate electrode 30 composed of the first metal electrode 21 by the system and the second metal electrode 27 by the gate last system is obtained.

  As described above, according to the present embodiment, the high-temperature annealing for the source / drain regions 25p, 25n, etc. is completed before the second electrode formation film 27A is deposited. The film 27A can form each MISFET while maintaining a high eWF value.

  Further, in the conventional gate last process, when the p-type MISFET and the n-type MISFET are separately formed, the second metal electrode forming film 27A in one of the p-type transistor region 10p and the n-type transistor region 10n is formed. Although it is necessary to remove it again, according to the present embodiment, the process of forming the gate trench in the interlayer insulating film 26 is only required once, so that the possibility of the occurrence of defective filling of the metal material can be remarkably reduced. .

(One Modification of Embodiment)
Hereinafter, a modification of the present embodiment will be described.

  For example, in the step of removing the dummy electrode 22 shown in FIG. 6C, if the n-type transistor region 10n is masked, the n-type MISFET has the first metal electrode 21 and the dummy electrode whose eWF value is reduced by annealing. 22 forms a final gate electrode 30. On the other hand, the p-type MISFET can obtain a high eWF value by the second metal electrode 27 having a relatively thick film thickness and substantially not annealed as in the present embodiment. For this reason, the difference in the eWF value in each of the p-type and n-type MISFETs can be further increased. That is, depending on the required eWF value, a CMOS circuit can be formed without providing the cap films 17 and 20 that modulate the eWF value such as aluminum oxide (AlO) or lanthanum oxide (LaO). As a result, a simpler CMOS formation flow can be realized.

Specifically, in the p-type transistor region 10p and the n-type transistor region 10n, the gate insulating films 16 made of hafnium oxide (HfO ₂ ) or hafnium silicon oxynitride (HfSiON) with the base film 15 interposed are formed. Thereafter, a first metal electrode 21 made of TiN having a thickness of about 4 nm is formed on each gate insulating film 16. Thereafter, a dummy electrode 22 made of polysilicon is formed on each first metal electrode 21. As a result, an n-type MISFET having a MIPS structure is formed in the n-type transistor region 10n. Subsequently, in the p-type transistor region 10p, the dummy electrode 22 is replaced with a second metal electrode 27 made of TiN.

  The polysilicon required for the n-type MISFET may be formed by depositing an undoped polysilicon film and doping the deposited polysilicon film with impurities, or depositing a polysilicon film doped with impurities. May be.

  In an n-type MISFET having a MIPS structure, at least a part of the polysilicon film may be silicided. Thereby, the resistance of the first metal electrode 21 and the polysilicon electrode can be reduced.

  In the n-type MISFET, the polysilicon electrode may be made of another metal material instead of polysilicon. Furthermore, the gate electrode 30 may be configured only by the first metal electrode 21 and the second metal electrode 27 may be omitted.

  The manufacturing method of a semiconductor device according to the present invention can realize a high yield and high performance semiconductor device by avoiding complicated processes and obtaining a high effective work function (eWF) value, and uses a metal for a gate electrode. This is useful for a method of manufacturing a semiconductor device.

10 p p-type transistor region 10 n n-type transistor region 11 semiconductor substrate 12 element isolation region 13 n-type active region (semiconductor region)
14 p-type active region (semiconductor region)
15 Base film 16 Gate insulating film 16A Gate insulating film forming film 17 First cap film 17A First cap film forming film 18 HM metal film 19 Resist film 20 Second cap film 21 First metal electrode 21A First Metal electrode formation film 22 Dummy electrode 22A Dummy electrode formation film 23p P-type extension region 23n N-type extension region 24 Side wall 25p P-type source / drain region 25n N-type source / drain region 26 Interlayer insulating film 26a Recess (gate trench) )
27 Second metal electrode 27A Second metal electrode formation film 30 Gate electrode

Claims (8)

Forming a gate insulating film formation film on the semiconductor region of the first conductivity type;
Forming a first metal electrode forming film on the gate insulating film forming film;
Forming a dummy electrode formation film on the first metal electrode formation film;
A dummy electrode is formed from the dummy electrode forming film by patterning the dummy electrode forming film, the first metal electrode forming film, and the gate insulating film forming film, and the first metal electrode is formed from the first metal electrode forming film. Forming an electrode and forming a gate insulating film from the gate insulating film forming film;
A diffusion region is formed on both sides of the dummy electrode in the semiconductor region by introducing impurity ions of the second conductivity type into the semiconductor region using the dummy electrode as a mask. Applying heat treatment;
Forming an interlayer insulating film so as to cover the dummy electrode on the semiconductor region after the heat treatment;
Exposing the dummy electrode from the formed interlayer insulating film and removing the dummy electrode exposed from the interlayer insulating film;
And a step of selectively forming a second metal electrode in the recess of the interlayer insulating film from which the dummy electrode has been removed.   The method for manufacturing a semiconductor device according to claim 1, wherein the first metal electrode is made of titanium nitride.   The method for manufacturing a semiconductor device according to claim 1, wherein the second metal electrode is made of titanium nitride.   The method for manufacturing a semiconductor device according to claim 1, wherein the gate insulating film contains hafnium. Between the step of forming the gate insulating film formation film and the step of forming the first metal electrode formation film,
Forming a first cap film containing aluminum on the gate insulating film forming film;
The first metal electrode formation film is formed on the first cap film,
The method of manufacturing a semiconductor device according to claim 4, wherein the first cap film is patterned together with the first metal electrode formation film. Between the step of forming the gate insulating film formation film and the step of forming the first metal electrode formation film,
Forming a second cap film containing lanthanum on the gate insulating film forming film;
Diffusing lanthanum into the gate insulating film forming film by heating the second cap film;
The method of manufacturing a semiconductor device according to claim 4, further comprising a step of removing the second cap film after heating.   The method for manufacturing a semiconductor device according to claim 1, wherein a solution comprising ammonia-hydrogen peroxide solution is used in the step of removing the dummy electrode.   The method for manufacturing a semiconductor device according to claim 1, wherein the second metal electrode is formed to have a wider width in a gate length direction than the first metal electrode. .

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