JP2010212715A - Lead frame laminate and manufacturing method for semiconductor device - Google Patents

Lead frame laminate and manufacturing method for semiconductor device Download PDF

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JP2010212715A
JP2010212715A JP2010103891A JP2010103891A JP2010212715A JP 2010212715 A JP2010212715 A JP 2010212715A JP 2010103891 A JP2010103891 A JP 2010103891A JP 2010103891 A JP2010103891 A JP 2010103891A JP 2010212715 A JP2010212715 A JP 2010212715A
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resin
lead frame
heat
sealing
resistant sheet
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Hitoshi Takano
均 高野
Yoshihisa Furuta
喜久 古田
Toshimitsu Tachibana
俊光 橘
Norikane Nahata
憲兼 名畑
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Nitto Denko Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lead frame laminate in which terminal portions on the outer side is protruded when resin-sealed, and three-dimensional sealing effect is achieved even for such a small terminal as can not prevent resin from creeping, only by adhesive force, and also to provide a method for manufacturing a semiconductor device. <P>SOLUTION: A lead frame laminate is provided with: a lead frame 10 having terminal portions which can protrude from a resin-sealed surface when a semiconductor chip is resin-sealed; and a heat resistant sheet 20 into which each protruded side of the terminal portions 11 was embedded to a depths not less than 5 &mu;m. The heat resistant sheet 20 is provided with: a resin layer 20c which is cured after each protruded side of the terminal portions 11 has been embedded; and a base substrate layer 20d to which the resin layer 20c adhered. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、半導体チップを樹脂封止する際に封止樹脂面から突出可能な端子部を有するリードフレームに耐熱性シートを積層したリードフレーム積層物およびそれを用いた半導体装置の製造方法に関する。   The present invention relates to a lead frame laminate in which a heat-resistant sheet is laminated on a lead frame having a terminal portion that can protrude from a sealing resin surface when a semiconductor chip is resin-sealed, and a method of manufacturing a semiconductor device using the lead frame laminate.

近年、ＬＳＩの実装技術において、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ／Ｓｃａｌｅ Ｐａｃｋａｇｅ）技術が注目されている。この技術のうち、ＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄｅｄ ｐａｃｋａｇｅ）に代表されるリード端子がパッケージ内部に取り込まれた形態のパッケージについては、小型化と高集積の面で特に注目されるパッケージ形態のひとつである。このようなＱＦＮパッケージは片面だけをモールド樹脂により封止する構造であることから、反対面側へのモールド樹脂のはみ出しや廻りこみを防止するのが好ましい。   In recent years, CSP (Chip Size / Scale Package) technology has attracted attention in LSI mounting technology. Among these technologies, a package in which a lead terminal represented by a QFN (Quad Flat Non-leaded package) is incorporated in the package is one of the package forms that are particularly noted in terms of miniaturization and high integration. is there. Since such a QFN package has a structure in which only one surface is sealed with a mold resin, it is preferable to prevent the mold resin from protruding or turning around to the opposite surface side.

このため、特開２０００−２９４５８０号公報には、上記の如きＱＦＮの製造方法において、リードフレームのアウター側に粘着テープを貼り付け、この粘着テープのマスキングによるシール効果により、樹脂封止時のアウター側への樹脂漏れを防ぐ製造方法が開示されている。   For this reason, Japanese Patent Laid-Open No. 2000-294580 discloses that in the method of manufacturing QFN as described above, an adhesive tape is attached to the outer side of the lead frame, and the sealing effect by masking this adhesive tape results in the outer sealing at the time of resin sealing. A manufacturing method for preventing resin leakage to the side is disclosed.

特開２０００−２９４５８０号公報JP 2000-294580 A

しかしながら、上記の方法では、一般的なＱＦＮにおいては有効であるものの、近年の半導体の高集積化に伴い、端子が複数列に配置されたＬＬＧＡ（Ｌｅａｄ−ｆｒａｍｅ Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）パッケージ（図５参照）などでは、個々の端子のサイズが小さいため、テープの粘着力だけでモールド樹脂の廻りこみを抑えることが難しくなってきた。   However, the above method is effective in a general QFN, but with the recent high integration of semiconductors, an LLGA (Lead-frame Land Grid Array) package in which terminals are arranged in a plurality of columns (see FIG. 5). ) And the like, the size of each terminal is small, and it has become difficult to suppress the wrapping of the mold resin only by the adhesive strength of the tape.

また、配線基板への半導体装置の実装時の信頼性を高めるために、封止樹脂面から端子部分がわずかに突出している「スタンドオフ」を持つものが知られており、この突出した端子部によって、配線基板等の平面性誤差による影響を受けにくくしている。しかし、上記従来の粘着テープでは、粘着層の薄いものが好適に使用されるため、端子部を封止樹脂面から突出させるほど、端子部の突出側を埋入させることはできなかった。   In addition, in order to increase the reliability when mounting the semiconductor device on the wiring board, it is known that there is a “stand-off” in which the terminal portion slightly protrudes from the sealing resin surface. This makes it less susceptible to the effects of planarity errors such as the wiring board. However, in the said conventional adhesive tape, since the thing with a thin adhesive layer is used suitably, the protrusion side of a terminal part was not able to be embedded so that a terminal part protruded from the sealing resin surface.

つまり、上記のような、高集積化に伴ったパターンの精細化や、実装時の信頼性向上が求められていくと、従来の単なる耐熱性粘着テープでは充分な対応ができなかった。   In other words, when there is a demand for finer patterns with higher integration and improved reliability during mounting as described above, conventional simple heat-resistant adhesive tapes have not been sufficient.

そこで、本発明の目的は、樹脂封止時にアウター側の端子部を突出させることができ、しかも、粘着力だけでは樹脂の廻りこみを抑制できなかったような小さな端子に対しても、立体的なシール効果が得られるリードフレーム積層物およびそれに用いる耐熱性シート、並びにそれらを用いた半導体装置の製造方法を提供することにある。   Therefore, the object of the present invention is to allow the outer terminal portion to protrude at the time of resin sealing, and even for a small terminal that cannot suppress the resin wraparound only by adhesive force. An object of the present invention is to provide a lead frame laminate capable of providing a good sealing effect, a heat resistant sheet used therefor, and a method for manufacturing a semiconductor device using them.

上記目的は、下記の如き本発明により達成できる。
即ち、本発明のリードフレーム積層物は、半導体チップを樹脂封止する際に封止樹脂面から突出可能な端子部を有するリードフレームと、その端子部の突出側を深さ５μｍ以上で埋入させた耐熱性シートとを備え、前記耐熱性シートが、前記端子部の突出側を埋入させた後に硬化反応させた樹脂層と、その樹脂層が接着した基材層とを備えることを特徴とする。 The above object can be achieved by the present invention as described below.
That is, the lead frame laminate of the present invention embeds a lead frame having a terminal portion that can protrude from the sealing resin surface when resin-sealing a semiconductor chip and a protruding side of the terminal portion at a depth of 5 μm or more. A heat-resistant sheet, and the heat-resistant sheet includes a resin layer that is cured and reacted after embedding the protruding side of the terminal portion, and a base material layer to which the resin layer is bonded. And

他方、本発明の半導体装置の製造方法は、上記いずれかに記載のリードフレーム積層物のインナー側の端子部に半導体チップを電気的に接続した状態で、その半導体チップを封止樹脂によりインナー側から樹脂封止する工程を含むことを特徴とする。   On the other hand, in the method for manufacturing a semiconductor device of the present invention, in the state where the semiconductor chip is electrically connected to the inner terminal portion of the lead frame laminate according to any one of the above, the semiconductor chip is sealed on the inner side with a sealing resin. And a step of sealing with resin.

［作用効果］
本発明のリードフレーム積層物によると、リードフレームの端子部の突出側を深さ５μｍ以上で埋入させた耐熱性シートを積層してあるため、樹脂封止時に端子部が埋入した分に相当するスタンドオフを作成することができ、また、粘着力だけでは樹脂の廻りこみを抑制できなかったような小さな端子に対しても、立体的なシール効果により樹脂の廻りこみを効果的に抑えることができるようになる。 [Function and effect]
According to the lead frame laminate of the present invention, since the heat-resistant sheet in which the protruding side of the terminal portion of the lead frame is embedded at a depth of 5 μm or more is laminated, the terminal portion is embedded at the time of resin sealing. The corresponding stand-off can be created, and even for small terminals that could not suppress the resin sneaking with only the adhesive force, the squeeze of the resin is effectively suppressed by the three-dimensional sealing effect. Will be able to.

また、前記耐熱性シートが、前記端子部の突出側を埋入させた後に硬化反応させた樹脂層と、その樹脂層が接着した基材層とを備える場合、未硬化の状態で端子部の突出側を深さ５μｍ以上で容易に埋入させることができ、しかも硬化反応後の樹脂層が基材層に接着しているため、基材層と共に樹脂層を剥離し易くなる。   In addition, when the heat-resistant sheet includes a resin layer cured after embedding the protruding side of the terminal portion and a base material layer to which the resin layer is bonded, the terminal portion is uncured. The protruding side can be easily embedded at a depth of 5 μm or more, and since the resin layer after the curing reaction is adhered to the base material layer, the resin layer is easily peeled off together with the base material layer.

一方、本発明の半導体装置の製造方法によると、上記に記載のリードフレーム積層物のインナー側の端子部に半導体チップを電気的に接続した状態で、その半導体チップを封止樹脂によりインナー側から樹脂封止する工程を含むため、樹脂封止時にアウター側の端子部を突出させることができ、しかも、粘着力だけでは樹脂の廻りこみを抑制できなかったような小さな端子に対しても、立体的なシール効果が得られる。その結果、高集積化に伴ったパターンの精細化にも対応でき、また、「スタンドオフ」の形成によって、実装時の信頼性が向上する半導体装置を製造することができる。   On the other hand, according to the method for manufacturing a semiconductor device of the present invention, in a state where the semiconductor chip is electrically connected to the inner side terminal portion of the lead frame laminate described above, the semiconductor chip is sealed from the inner side with a sealing resin. Since the resin sealing process is included, the outer terminal part can be projected at the time of resin sealing, and even for small terminals that could not suppress the resin wrapping only with adhesive strength, Sealing effect can be obtained. As a result, it is possible to cope with the refinement of patterns accompanying high integration, and it is possible to manufacture a semiconductor device in which the reliability at the time of mounting is improved by forming a “stand-off”.

一般的な半導体装置の製造方法の例を示す工程図Process drawing showing an example of a general semiconductor device manufacturing method 本発明におけるリードフレームの一例を示す図であり、（ａ）は正面図、（ｂ）は要部拡大図、（ｃ）は樹脂封止後の状態を示す底面図It is a figure which shows an example of the lead frame in this invention, (a) is a front view, (b) is a principal part enlarged view, (c) is a bottom view which shows the state after resin sealing 本発明における樹脂封止工程の一例を示す縦断面図The longitudinal cross-sectional view which shows an example of the resin sealing process in this invention 本発明によって得られる半導体装置の一例を示す図であり、（ａ）は底面図、（ｂ）は正面視断面図It is a figure which shows an example of the semiconductor device obtained by this invention, (a) is a bottom view, (b) is front sectional drawing. 本発明によって得られる半導体装置の他の例を示す図であり、（ａ）は底面図、（ｂ）は正面視断面図It is a figure which shows the other example of the semiconductor device obtained by this invention, (a) is a bottom view, (b) is front sectional drawing. 耐熱性シートを剥離する前の図５の半導体装置を示す正面視断面図Front view sectional drawing which shows the semiconductor device of FIG. 5 before peeling a heat resistant sheet 耐熱性シートを剥離する前の半導体装置の一例を示す要部拡大した正面視断面図Front view sectional drawing which expanded the principal part which shows an example of the semiconductor device before peeling a heat resistant sheet 耐熱性シートを剥離する前の半導体装置の他の例を示す要部拡大した正面視断面図Front view sectional drawing which expanded the principal part which shows the other example of the semiconductor device before peeling a heat resistant sheet

以下、本発明の実施の形態について、図面を参照しながら説明する。まず、一般的な半導体装置の製造方法について説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a general method for manufacturing a semiconductor device will be described.

図１は、当該製造方法の一例を示す工程図である。この実施形態では、図１（ａ）〜（ｅ）に示すように、耐熱性シート２０を積層する積層工程と、半導体チップ１５の搭載工程と、ボンディングワイヤ１６による接続工程と、封止樹脂１７による封止工程と、封止された構造物２１を切断する切断工程とを含む例を示す。   FIG. 1 is a process diagram showing an example of the manufacturing method. In this embodiment, as shown in FIGS. 1A to 1E, a stacking process for stacking the heat-resistant sheets 20, a mounting process for the semiconductor chip 15, a connecting process using the bonding wires 16, and a sealing resin 17 are used. The example including the sealing process by and the cutting process which cut | disconnects the sealed structure 21 is shown.

積層工程は、図１（ａ）に示すように、開口部１１ａ及び表裏両面の端子部１１ｂを備えるリードフレーム１０のアウター側（図の下側）に、開口部１１ａを塞ぐように耐熱性シート２０を積層するものである。   In the laminating step, as shown in FIG. 1A, a heat-resistant sheet is formed so as to close the opening 11a on the outer side (the lower side of the drawing) of the lead frame 10 including the opening 11a and the terminal portions 11b on both front and back surfaces. 20 is laminated.

リードフレーム１０とは、例えば銅、銅を含む合金などの金属を素材としてＣＳＰの端子パターンが刻まれたものであり、その電気接点部分には、銀、ニッケル、パラジウム、金などの素材で被覆（めっき）されている場合もある。なお、リードフレーム１０の厚みは、５０〜３００μｍが一般的である。   The lead frame 10 is made by engraving a CSP terminal pattern made of a metal such as copper or an alloy containing copper, and the electrical contact portion is covered with a material such as silver, nickel, palladium, or gold. (Plating) may be done. The lead frame 10 generally has a thickness of 50 to 300 μm.

リードフレーム１０は、後の切断工程にて切り分けやすいよう、個々のＱＦＮの配置パターンが整然と並べられているものが好ましい。例えば図２に示すように、リードフレーム１０上に縦横のマトリックス状に配列された形状などは、マトリックスＱＦＮあるいはＭＡＰ−ＱＦＮなどと呼ばれ、もっとも好ましいリードフレーム形状のひとつである。   The lead frame 10 is preferably one in which arrangement patterns of individual QFNs are arranged in an orderly manner so that the lead frame 10 can be easily separated in a subsequent cutting step. For example, as shown in FIG. 2, a shape arranged in a vertical and horizontal matrix on the lead frame 10 is called a matrix QFN or MAP-QFN, and is one of the most preferable lead frame shapes.

図２（ａ）〜（ｂ）に示すように、リードフレーム１０のパッケージパターン領域１１には、隣接した複数の開口部１１ａに端子部１１ｂを複数配列した、ＱＦＮの基板デザインが整然と配列されている。一般的なＱＦＮの場合、各々の基板デザイン（図２（ａ）の格子で区分された領域）は、開口部１１ａの周囲に配列された端子部１１ｂと、開口部１１ａの中央に配置されるダイパッド１１ｃと、ダイパッド１１ｃを開口部１１ａの４角に支持させるダイバー１１ｄとで構成される。   As shown in FIGS. 2A to 2B, the package pattern region 11 of the lead frame 10 has a QFN substrate design in which a plurality of terminal portions 11b are arranged in a plurality of adjacent openings 11a. Yes. In the case of a general QFN, each board design (region divided by the lattice in FIG. 2A) is arranged in the center of the opening 11a and the terminal 11b arranged around the opening 11a. It consists of a die pad 11c and a diver 11d that supports the die pad 11c at the four corners of the opening 11a.

耐熱性シート２０は、開口部１１ａを塞ぐように、少なくともパッケージパターン領域１１より外側に積層され、樹脂封止される樹脂封止領域の外側の全周を含む領域に積層するのが好ましい。リードフレーム１０は、通常、樹脂封止時の位置決めを行うための、ガイドピン用孔１３を端辺近傍に有しており、それを塞がない領域に積層するのが好ましい。また、樹脂封止領域はリードフレーム１０の長手方向に複数配置されるため、それらの複数領域を渡るように連続して耐熱性シート２０を積層するのが好ましい。   The heat-resistant sheet 20 is preferably laminated at least outside the package pattern region 11 so as to close the opening 11a and in a region including the entire circumference outside the resin-sealed region to be resin-sealed. The lead frame 10 usually has a guide pin hole 13 for positioning at the time of resin sealing in the vicinity of the end side, and it is preferable that the lead frame 10 be laminated in a region where it is not blocked. In addition, since a plurality of resin-sealed regions are arranged in the longitudinal direction of the lead frame 10, it is preferable that the heat-resistant sheets 20 are continuously laminated so as to cross the plurality of regions.

本発明のリードフレーム積層物は、上記のようなリードフレーム１０が樹脂封止の際に封止樹脂面から突出可能な端子部を有すると共に、上記の耐熱性シート２０が端子部の突出側を深さ５μｍ以上で埋入させることを特徴とする。これらの点については、後に詳述する。   The lead frame laminate of the present invention has a terminal portion that can protrude from the sealing resin surface when the lead frame 10 is sealed with resin, and the heat-resistant sheet 20 has a protruding side of the terminal portion. It is embedded at a depth of 5 μm or more. These points will be described in detail later.

搭載工程は、図１（ｂ）に示すように、リードフレーム１０のダイパッド１１ｃ上に半導体チップ１５をボンディングする工程である。半導体チップ１５とは、例えば半導体集積回路部分であるシリコン・チップを指す。ダイパッド１１ｃは半導体チップ１５を固定するためのエリアであり、ダイパッド１１ｃヘのボンディング（固定）の方法は、導電性ペースト１９を使用したり、接着テープ、接着剤など各種の方法が用いられる。導電性ペーストや熱硬化性の接着剤等を用いてダイボンドする場合、一般的に１５０〜２００℃程度の温度で３０分〜９０分程度加熱キュアする。   The mounting process is a process of bonding the semiconductor chip 15 onto the die pad 11c of the lead frame 10 as shown in FIG. The semiconductor chip 15 refers to, for example, a silicon chip that is a semiconductor integrated circuit portion. The die pad 11c is an area for fixing the semiconductor chip 15, and the bonding (fixing) method to the die pad 11c uses a conductive paste 19 or various methods such as an adhesive tape and an adhesive. When die bonding is performed using a conductive paste, a thermosetting adhesive, or the like, generally heat curing is performed at a temperature of about 150 to 200 ° C. for about 30 to 90 minutes.

結線工程は、図１（ｃ）に示すように、リードフレーム１０のインナー側の端子部１１ｂ（インナーリード）と半導体チップ１５上の電極パッド１５ａとをボンディングワイヤ１６で電気的に接続する工程である。ボンディングワイヤ１６としては、例えば金線あるいはアルミ線などが用いられる。一般的には１５０〜２５０℃に加熱された状態で、超音波による振動エネルギーと印加加圧による圧着エネルギーの併用により結線される。その際、リードフレーム１０に積層した耐熱性シート２０面を真空吸引することで、ヒートブロックに確実に固定することができる。   As shown in FIG. 1 (c), the connection process is a process of electrically connecting the terminal portion 11 b (inner lead) on the inner side of the lead frame 10 and the electrode pad 15 a on the semiconductor chip 15 with a bonding wire 16. is there. For example, a gold wire or an aluminum wire is used as the bonding wire 16. In general, in a state heated to 150 to 250 ° C., the wire is connected by a combination of vibration energy by ultrasonic waves and pressure energy by applying pressure. At that time, the surface of the heat-resistant sheet 20 laminated on the lead frame 10 can be securely fixed to the heat block by vacuum suction.

封止工程は、図１（ｄ）に示すように、封止樹脂１７により半導体チップ側を片面封止する工程である。封止工程は、リードフレーム１０に搭載された半導体チップ１５やボンディングワイヤ１６を保護するために行われ、とくにエポキシ系の樹脂をはじめとした封止樹脂１７を用いて金型中で成型されるのが代表的である。その際、図３に示すように、複数のキャビティを有する上金型１８ａと下金型１８ｂからなる金型１８を用いて、複数の封止樹脂１７にて同時に封止工程が行われるのが一般的である。具体的には、例えば樹脂封止時の加熱温度は１７０〜１８０℃であり、この温度で数分間キュアされた後、更に、ポストモールドキュアが数時間行われる。なお、耐熱性シート２０はポストモールドキュアの前に剥離するのが好ましい。   The sealing step is a step of sealing one side of the semiconductor chip side with a sealing resin 17 as shown in FIG. The sealing process is performed to protect the semiconductor chip 15 and the bonding wire 16 mounted on the lead frame 10 and is molded in a mold using a sealing resin 17 including an epoxy resin in particular. Is typical. At that time, as shown in FIG. 3, a sealing process is simultaneously performed with a plurality of sealing resins 17 using a mold 18 composed of an upper mold 18a and a lower mold 18b having a plurality of cavities. It is common. Specifically, for example, the heating temperature at the time of resin sealing is 170 to 180 ° C. After curing at this temperature for several minutes, post mold curing is further performed for several hours. The heat resistant sheet 20 is preferably peeled before post mold curing.

切断工程は、図１（ｅ）に示すように、封止された構造物２１を個別の半導体装置２１ａに切断する工程である。一般的にはダイサーなどの回転切断刃を用いて封止樹脂１７の切断部１７ａをカットする切断工程が挙げられる。   The cutting step is a step of cutting the sealed structure 21 into individual semiconductor devices 21a as shown in FIG. Generally, there is a cutting step of cutting the cutting portion 17a of the sealing resin 17 using a rotary cutting blade such as a dicer.

一方、本発明のリードフレーム積層物は、半導体チップを樹脂封止する際に封止樹脂面から突出可能な端子部を有するリードフレームと、その端子部の突出側を深さ５μｍ以上で埋入させた耐熱性シートとを備えるものである。   On the other hand, the lead frame laminate of the present invention embeds a lead frame having a terminal portion that can protrude from the sealing resin surface when resin-sealing a semiconductor chip and a protruding side of the terminal portion at a depth of 5 μm or more. A heat-resistant sheet.

本発明に用いられるリードフレームは、図１〜図３に示すように、リードフレーム１０のアウター側（図の下側）面がフラットなものでもよく、その場合、図４（ａ）〜（ｂ）に示すように、端子部１１ｂの全面が封止樹脂１７面から突出（スタンドオフ）した状態となる。また、図５〜図６に示すように、リードフレーム１０のアウター側面が凸状となった端子部１１ｆ，１１ｇを有するものでもよい（ＬＬＧＡタイプ）。その場合、図６に示すように、端子部１１ｆ，１１ｇの突出側が封止樹脂１７面から突出（スタンドオフ）した状態となる。なお、内周側の端子部１１ｆと外周側の端子部１１ｇとは、リードフレーム１０の開口部１１ａに対して順次交互に配列されている。   As shown in FIGS. 1 to 3, the lead frame used in the present invention may have a flat outer side (lower side) surface of the lead frame 10, in which case FIGS. ), The entire surface of the terminal portion 11b protrudes (stands off) from the surface of the sealing resin 17. Moreover, as shown in FIGS. 5-6, you may have the terminal parts 11f and 11g which the outer side surface of the lead frame 10 became convex shape (LLGA type). In this case, as shown in FIG. 6, the protruding side of the terminal portions 11 f and 11 g protrudes (stands off) from the surface of the sealing resin 17. Note that the inner peripheral terminal portions 11 f and the outer peripheral terminal portions 11 g are sequentially and alternately arranged with respect to the opening 11 a of the lead frame 10.

本発明における耐熱性シートは、少なくともモールド樹脂による封止の工程でかかる加熱に対して耐えるだけの耐熱性を有していればよく、モールド樹脂による封止工程は一般的に１７５℃前後の温度がかかることから、このような温度条件下での著しい収縮といった変形、あるいは流動や分解などシートそのものが破壊を生じない耐熱性を持っている必要性がある。さらに好ましくは、リードフレームとの合わせる作業性を考慮した場合、ワイヤボンディング工程以前、あるいは半導体チップの搭載工程以前にあらかじめリードフレームと合わせておくことも考えられるため、それぞれの工程に対してもかかる温度に十分耐える熱特性を有していることがさらに好ましい。   The heat-resistant sheet in the present invention only needs to have heat resistance sufficient to withstand such heating at least in the sealing step with the mold resin, and the sealing step with the mold resin is generally performed at a temperature of about 175 ° C. Therefore, it is necessary to have heat resistance such that the sheet itself does not break, such as deformation such as significant shrinkage under such temperature conditions, or flow and decomposition. More preferably, when considering the workability with the lead frame, it may be possible to pre-fit with the lead frame before the wire bonding process or before the semiconductor chip mounting process. More preferably, it has a thermal characteristic that can sufficiently withstand the temperature.

なお、本発明のリードフレーム積層物とは、粘着あるいは接着テープのように貼り合わせるタイプだけでなく、成型金型中などでリードフレームとシートを重ねて単に密着させている場合なども含まれる。   The lead frame laminate of the present invention includes not only a type of bonding such as an adhesive or an adhesive tape, but also a case where the lead frame and the sheet are simply stuck together in a molding die or the like.

本発明の特徴は、図６に示すように、上記のごとき積層状態で、リードフレーム１０の端子部１１ｆ，１１ｇの突出側を深さ５μｍ以上で耐熱性シート２０に埋入させたことにある。すなわち、リードフレーム１０の端子部１１ｆ，１１ｇのアウター側の最表面に単に粘着テープがついているだけでなく、リードフレームの端子部１１ｆ，１１ｇと立体的な接触を得ることで、テープの粘着力だけでは抑えにくかった小型の端子部分に関しても立体的にシールする形とすることで、樹脂の廻りこみをよく抑えることが出来る。なお、埋入するとは、端子部１１ｆ，１１ｇなど一部分だけが埋入していてもよく、この場合の５μｍ以上というのは最大埋入深さを意味している。   The feature of the present invention is that, as shown in FIG. 6, the protruding side of the terminal portions 11f and 11g of the lead frame 10 is embedded in the heat-resistant sheet 20 at a depth of 5 μm or more in the laminated state as described above. . That is, not only the adhesive tape is attached to the outermost surface of the terminal portions 11f and 11g of the lead frame 10 but also the three-dimensional contact with the terminal portions 11f and 11g of the lead frame, whereby the adhesive strength of the tape is obtained. Even with small terminal parts that were difficult to suppress by itself, it is possible to suppress the resin wrapping well by adopting a three-dimensional seal. The term “embedding” may mean that only a part of the terminal portions 11f, 11g, etc. is buried, and in this case, 5 μm or more means the maximum embedding depth.

また、耐熱性シート２０に埋入している分だけ、封止樹脂１７による封止が行われないことから、結果的にスタンドオフを形成することとなり、半導体装置の基板等への実装信頼性も向上する。この場合のスタンドオフは少なくとも５μｍ以上、好ましくは１０〜５０μｍ程度がもっとも効果的である。従って、耐熱性シート２０に埋入する深さも、１０〜５０μｍが好ましい。   Further, since sealing with the sealing resin 17 is not performed by the amount embedded in the heat resistant sheet 20, a standoff is formed as a result, and mounting reliability of the semiconductor device on the substrate or the like is increased. Will also improve. In this case, the stand-off is most effective at least 5 μm or more, preferably about 10 to 50 μm. Therefore, the depth embedded in the heat resistant sheet 20 is also preferably 10 to 50 μm.

具体的な埋入の方法は、特に限定されるものではないが、たとえば、
（１）耐熱性シートを構成する部材の一部または全部が変形しやすい構造を備えており、リードフレームと合わせた際にその密着力によって埋入させる方法、
（２）耐熱性シートを構成する一部が、積層時において未硬化あるいは軟化状態でリードフレームを積層して埋入させ、後に樹脂封止あるいはその後のシート剥離に耐える剛性強度に硬化させる方法、
（３）耐熱性シートとリードフレームを合わせた後、耐熱性シート側が膨張変形してリードフレームを取り込む方法などが挙げられる。 The specific embedding method is not particularly limited. For example,
(1) A method in which part or all of the members constituting the heat-resistant sheet has a structure that is easily deformed, and is embedded by its adhesion when combined with the lead frame,
(2) A method in which a part of the heat-resistant sheet is laminated and embedded in an uncured or softened state at the time of lamination, and then cured to a rigid strength that can withstand resin sealing or subsequent sheet peeling,
(3) After the heat-resistant sheet and the lead frame are combined, the heat-resistant sheet side is expanded and deformed to take in the lead frame.

上記（１）の方法としては、例えば多孔質、発泡体などのクッション素材を配置するものが挙げられる。好ましくは、耐熱性樹脂からなる多孔質層を備える耐熱性シートを用いる方法であり、封止工程で封止樹脂が多孔質層に含浸されるのを防止する上で、図７に示すように、多孔質層２０ｂの封止する側の表面に非多孔質層２０ａを設けたものが更に好ましい。   As a method of said (1), what arrange | positions cushion materials, such as a porous and a foam, is mentioned, for example. Preferably, it is a method using a heat-resistant sheet comprising a porous layer made of a heat-resistant resin, and in order to prevent the porous resin from being impregnated with the sealing resin in the sealing step, as shown in FIG. More preferably, the porous layer 20b is provided with a non-porous layer 20a on the surface to be sealed.

多孔質層を形成する耐熱性樹脂としては、ポリテトラフルオロエチレン（ＰＴＦＥ）、エチレン−テトラフルオロエチレン共重合体（ＥＴＦＥ）、テトラフルオロエチレン−パーフルオロアルキルビニルエーテル共重合体（ＰＦＡ）、テトラフルオロエチレン−ヘキサフルオロプロピレン共重合体（ＦＥＰ）等のフッ素樹脂、又はポリイミド、ポリエステル、ポリアミド、特に芳香族ポリアミド、ポリアミドイミド、ポリエーテルイミド、ポリエーテルサルホン等が挙げられる。また、多孔質層は、湿式凝固法、乾式凝固法、延伸法など種々の製膜法にて形成することができる。   Examples of the heat resistant resin for forming the porous layer include polytetrafluoroethylene (PTFE), ethylene-tetrafluoroethylene copolymer (ETFE), tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer (PFA), and tetrafluoroethylene. -Fluororesin such as hexafluoropropylene copolymer (FEP), or polyimide, polyester, polyamide, especially aromatic polyamide, polyamideimide, polyetherimide, polyethersulfone and the like. The porous layer can be formed by various film forming methods such as a wet coagulation method, a dry coagulation method, and a stretching method.

また、多孔質層の空孔率は、好適な埋入深さを得る上での変形のしやすさから、少なくとも３０％以上、更に取扱い性なども考慮すると、４０〜８０％程度であることがよい。また、多孔質層の厚みは、同様の理由から、１０〜５００μｍが好ましい。   In addition, the porosity of the porous layer is at least 30% or more from the viewpoint of ease of deformation for obtaining a suitable embedding depth, and is also about 40 to 80% in consideration of handling properties. Is good. The thickness of the porous layer is preferably 10 to 500 μm for the same reason.

非多孔質層を設ける場合の材質としては、上記と同様の耐熱性樹脂などが挙げられるが、封止樹脂との離型性の点から、フッ素樹脂、例えばポリテトラフルオロエチレン（ＰＴＦＥ）、エチレン−テトラフルオロエチレン共重合体（ＥＴＦＥ）、テトラフルオロエチレン−パーフルオロアルキルビニルエーテル共重合体（ＰＦＡ）、テトラフルオロエチレン−ヘキサフルオロプロピレン共重合体（ＦＥＰ）等が好適なものとして挙げられる。また、端子部の埋入を好適にする上で、非多孔質層の厚みは５〜５０μｍが好ましい。非多孔質層を多孔質層と積層一体化する方法は、全面に接着剤等や、熱ラミネートして貼り合わせる他、部分的に端部のみ接着させて実質的に重ねられた状態であってもよい。   Examples of the material for providing the non-porous layer include the same heat-resistant resin as described above. From the viewpoint of releasability from the sealing resin, fluororesin such as polytetrafluoroethylene (PTFE), ethylene Preferred examples include -tetrafluoroethylene copolymer (ETFE), tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer (PFA), tetrafluoroethylene-hexafluoropropylene copolymer (FEP), and the like. Moreover, when making embedding of a terminal part suitable, the thickness of a non-porous layer has preferable 5-50 micrometers. The method of laminating and integrating the non-porous layer with the porous layer is a state in which the entire surface is substantially overlapped with adhesive or the like, or heat laminated and bonded partially only to the end portion. Also good.

上記（２）の方法の場合、図８に示すように、耐熱性シート２０が、端子部１１ｆ，１１ｇの突出側を埋入させた後に硬化反応させた樹脂層２０ｃと、その樹脂層２０ｃが接着した基材層２０ｄとを備えるものとなる。樹脂層２０ｃは、ホットメルト型接着剤のように加熱状態で軟化する樹脂層でもよいが、端子部の突出側を埋入させた後に硬化反応によりある程度硬化する粘着剤又は接着剤からなる樹脂層が好ましい。当該樹脂層２０ｃとしては、ＵＶ架橋性樹脂、熱架橋性樹脂などを樹脂成分とするものが挙げられ、アクリル系の粘着剤、シリコーン系の粘着剤などが好ましい。   In the case of the above method (2), as shown in FIG. 8, the heat resistant sheet 20 has a resin layer 20 c that has undergone a curing reaction after embedding the protruding sides of the terminal portions 11 f and 11 g, and the resin layer 20 c includes The substrate layer 20d is adhered. The resin layer 20c may be a resin layer that softens in a heated state like a hot melt adhesive, but a resin layer made of a pressure-sensitive adhesive or adhesive that cures to some extent by a curing reaction after embedding the protruding side of the terminal portion. Is preferred. Examples of the resin layer 20c include those having a UV-crosslinkable resin, a heat-crosslinkable resin, or the like as a resin component, and an acrylic pressure-sensitive adhesive or a silicone-based pressure-sensitive adhesive is preferable.

但し、本発明では、樹脂封止後に耐熱性シートを剥離する必要があり、その際に接着力が高過ぎると、半導体装置を破損するおそれがあるため、上記の樹脂層が、金属及び封止樹脂との接着力が適度に小さいことが好ましい。かかる観点から、当該樹脂層としては、アクリル系又はシリコーン系の粘着剤とＵＶ硬化型の架橋剤を混合して用いることが、硬化前の粘度と硬化後の強度を任意に調整しやすいので好ましい。なお、樹脂層の厚みは、端子部の埋入深さ以上となる５μｍ以上であればよいが、硬化反応後の樹脂層のクッション性（弾性）が高くなる材質の場合には、端子部の埋入深さに合わせて、厚さ１０〜５０μｍが好ましい。   However, in the present invention, it is necessary to peel off the heat-resistant sheet after resin sealing, and if the adhesive force is too high, the semiconductor device may be damaged. It is preferable that the adhesive strength with the resin is moderately small. From this point of view, it is preferable to use a mixture of an acrylic or silicone adhesive and a UV curable crosslinking agent as the resin layer, because it is easy to arbitrarily adjust the viscosity before curing and the strength after curing. . The thickness of the resin layer may be 5 μm or more which is equal to or greater than the embedding depth of the terminal portion. However, in the case of a material that increases the cushioning property (elasticity) of the resin layer after the curing reaction, The thickness is preferably 10 to 50 μm according to the embedding depth.

基材層としては、アルミニウム箔などの金属箔や、耐熱性樹脂フィルムが使用でき、耐熱性樹脂フィルムとしては、耐熱性の高いポリイミドフィルムやアラミドフィルムの他、ポリエチレンテレフタレート（ＰＥＴ）フィルム、ポリエチレンナフタレート（ＰＥＮ）フィルム、ポリエーテルサルフォン（ＰＥＳ）フィルム、ポリエーテルイミド（ＰＥＩ）フィルム、ポリサルフォン（ＰＳＦ）フィルム、ポリフェニレンサルファイド（ＰＰＳ）フィルム、ポリアリレート（ＰＡＲ）フィルム、又は液晶ポリマー（ＬＣＰ）フィルムなどが挙げられる。基材層の厚みは、耐熱性シートの引き剥がし時に、破断を生じくくする上で、１０〜１００μｍが好ましく、２０〜５０μｍがより好ましい。   As the base material layer, a metal foil such as an aluminum foil or a heat-resistant resin film can be used. As the heat-resistant resin film, in addition to a highly heat-resistant polyimide film or aramid film, a polyethylene terephthalate (PET) film or a polyethylene naphthalate film is used. Phthalate (PEN) film, polyethersulfone (PES) film, polyetherimide (PEI) film, polysulfone (PSF) film, polyphenylene sulfide (PPS) film, polyarylate (PAR) film, or liquid crystal polymer (LCP) film Etc. The thickness of the base material layer is preferably 10 to 100 μm and more preferably 20 to 50 μm in order to prevent breakage when the heat-resistant sheet is peeled off.

また、封止樹脂面から突出させる端子部のアウター側面を平坦化（面一）する上で、端子部のアウター側面の少なくとも一部が、基材層の表面に接当した状態で樹脂層に埋入していることが好ましい。   In addition, when flattening the outer side surface of the terminal portion that protrudes from the sealing resin surface, the resin layer is in a state where at least a part of the outer side surface of the terminal portion is in contact with the surface of the base material layer. It is preferable that it is embedded.

上記（３）の方法において、積層後に膨張変形する材料としては、加熱等により発泡増量して不可逆的に厚みが増加する熱発泡体シートや、それを基材層に形成したものなどが挙げられる。   In the method of (3) above, examples of the material that expands and deforms after lamination include a thermal foam sheet in which the foam is increased by heating or the like and the thickness is irreversibly increased, or a material formed on the base material layer. .

一方、本発明の半導体装置の製造方法は、以上のようなリードフレーム積層物のインナー側の端子部に半導体チップを電気的に接続した状態で、その半導体チップを封止樹脂によりインナー側から樹脂封止する工程を含むものである。具体的には、図１に示すように、耐熱性シート２０を積層する積層工程と、半導体チップ１５の搭載工程と、ボンディングワイヤ１６による接続工程と、封止樹脂１７による封止工程と、封止された構造物２１を切断する切断工程とを含むものが例示できる。   On the other hand, in the method for manufacturing a semiconductor device of the present invention, in the state where the semiconductor chip is electrically connected to the terminal portion on the inner side of the lead frame laminate as described above, the semiconductor chip is resinated from the inner side with a sealing resin. It includes a step of sealing. Specifically, as shown in FIG. 1, a stacking process for stacking the heat-resistant sheet 20, a mounting process for the semiconductor chip 15, a connecting process using a bonding wire 16, a sealing process using a sealing resin 17, and a sealing process. The thing including the cutting process which cut | disconnects the stopped structure 21 can be illustrated.

〔別の実施形態〕
（１）前述の実施形態では、ダイパッドを有するリードフレームを用いた半導体装置の製造方法の例を示したが、ダイパッドを有しないリードフレームを用いてもよい。また、端子部の配置形状なども何れでもよい。またリードフレームは、少なくとも端子部が金属製であればよく、他の部分は耐熱性樹脂やセラミックス等で形成されていてもよい。 [Another embodiment]
(1) In the above-described embodiment, an example of a method for manufacturing a semiconductor device using a lead frame having a die pad has been described. However, a lead frame having no die pad may be used. Further, the terminal portion may be arranged in any shape. The lead frame only needs to have at least a terminal portion made of metal, and the other portion may be formed of a heat resistant resin, ceramics, or the like.

（２）前述の実施形態では、ボンディングワイヤにて接続工程を行う例を示したが、例えば半導体チップの下側に設けた電極パッドと端子部との間で、はんだ等のソルダーによる接続を行ってもよい。これは、第２実施形態についても同様である。 (2) In the above-described embodiment, the example in which the connection process is performed using the bonding wire has been described. For example, the connection between the electrode pad provided on the lower side of the semiconductor chip and the terminal portion is performed using solder such as solder. May be. The same applies to the second embodiment.

（３）前述の実施形態では、複数の半導体チップ１５を同じキャビティ内で一括封止する例を示したが、液状の封止樹脂を用いて、ポッティング後に硬化させてもよい。また、１つの半導体チップのみをキャビティ内で個別封止してもよい。個別封止の場合、封止樹脂を切断する工程が不要となる。 (3) In the above-described embodiment, an example in which a plurality of semiconductor chips 15 are collectively sealed in the same cavity has been described. However, liquid sealing resin may be used and cured after potting. Further, only one semiconductor chip may be individually sealed in the cavity. In the case of individual sealing, a step of cutting the sealing resin is not necessary.

以下、本発明の構成と効果を具体的に示す実施例等について説明する。   Examples and the like specifically showing the configuration and effects of the present invention will be described below.

実施例１
ＰＴＦＥファインパウダー（ダイキン（株）製ポリフロンＦ−１０４）に液状潤滑剤２０ｗｔ％を加えたペースト状の混和物を予備成形し、ペースト押出により丸棒状に成型した。成形物を厚み０．２ｍｍに圧延し液状潤滑剤を除去後、二軸に延伸して厚さ：４０μｍ，気孔率：５５％のＰＴＦＥ多孔質シートを得た。次いで、厚さ１０μｍのＰＴＦＥフィルム上に厚さ約２μｍのＦＥＰ層をキャスティングした基材フィルムに、上記多孔質シートを加熱ラミネートして貼り合わせ、耐熱性シートを得た。 Example 1
A paste-like mixture obtained by adding 20 wt% of a liquid lubricant to PTFE fine powder (Polyflon F-104 manufactured by Daikin Co., Ltd.) was preformed and formed into a round bar shape by paste extrusion. The molded product was rolled to a thickness of 0.2 mm to remove the liquid lubricant and then stretched biaxially to obtain a PTFE porous sheet having a thickness of 40 μm and a porosity of 55%. Subsequently, the porous sheet was laminated by heating to a base film obtained by casting an FEP layer having a thickness of about 2 μm on a PTFE film having a thickness of 10 μm to obtain a heat-resistant sheet.

この耐熱製シートのＰＴＦＥキャスティングフィルム側を、端子部分に銀めっきが施された一辺が９Ｐｉｎ×２列配列タイプのＬＬＧＡが３個×３個に配列された銅製のリードフレームのアウター側に圧着した。その際、リード端子を初めとしたパターン部分のＰＴＦＥ多孔質部分が潰れて，ＰＴＦＥキャスティングフィルムが変形し、結果的に耐熱性シートへ３０〜４０μｍ程度リードフレームの端子部が食い込んだ状態となった（図７参照）。   The PTFE casting film side of this heat-resistant sheet was pressure-bonded to the outer side of a copper lead frame in which 3 × 3 rows of 9-pin × 2-row LLGA with silver plating on the terminal portion were arranged . At that time, the PTFE porous portion of the pattern portion including the lead terminal was crushed, the PTFE casting film was deformed, and as a result, the terminal portion of the lead frame was bitten into the heat resistant sheet by about 30 to 40 μm. (See FIG. 7).

このリードフレームのダイパッド部分に半導体チップをエポキシフェノール系の銀ペーストを用いて接着し、１８０℃にて１時間ほどキュアすることで固定した。つぎに、リードフレームは耐熱性シート側から真空吸引する形で２００℃に加熱したヒートブロックに固定し、さらにリードフレームの周辺部分をウインドクランパーにて押さえて固定した。これらを、（日本アビオニクス製）の６０ＫＨｚワイヤボンダーを用いての２５μｍの金線（田中貴金属製ＧＬＤ−２５）にてワイヤボンディングを行った。   The semiconductor chip was bonded to the die pad portion of the lead frame using an epoxyphenol-based silver paste and fixed by curing at 180 ° C. for about 1 hour. Next, the lead frame was fixed to a heat block heated to 200 ° C. by vacuum suction from the heat-resistant sheet side, and further, the peripheral portion of the lead frame was pressed and fixed with a wind clamper. These were wire-bonded with a 25 μm gold wire (GLD-25, Tanaka Kikinzoku) using a 60 KHz wire bonder (manufactured by Nippon Avionics).

さらにエポキシ系モールド樹脂（日東電工製ＨＣ−３００）により、これらをモールドマシン（ＴＯＷＡ製Ｍｏｄｅｌ−Ｙ−ｓｅｒｉｓｅ）を用いて、１７５℃で、プレヒート４０秒、インジェクション時間１１．5 秒、キュア時間１２０秒にてモールドした後、耐熱性シートを剥離した。なお、さらに１７５℃にて３時間ほどポストモールドキュアを行って樹脂を十分に硬化させた後、ダイサーによって切断して、個々のＬＬＧＡタイプ半導体装置を得た。   Furthermore, with epoxy mold resin (HC-300 manufactured by Nitto Denko), these were used at 175 ° C. using a molding machine (Model-Y-series manufactured by TOWA), preheating 40 seconds, injection time 11.5 seconds, cure time 120 After molding in seconds, the heat-resistant sheet was peeled off. Further, after post-curing at 175 ° C. for about 3 hours to sufficiently cure the resin, the resin was cut by a dicer to obtain individual LLGA type semiconductor devices.

このようにして得られたＬＬＧＡは、樹脂のはみ出しもなく、また各リード端子部分におよそ２０μｍのスタンドオフを作成することができた。   The LLGA thus obtained did not protrude from the resin, and was able to produce a standoff of about 20 μm at each lead terminal portion.

実施例２
アクリル酸エステル（２−エチルヘキシルアクリレート）８０重量部にアクリル酸２０重量部と光開始剤（チバガイギー製『イルガキュア１８４』）を０．５重量部混合したＵＶ硬化型粘着剤を、厚さ５０μｍのＦＴＦＥ製フィルムに約３０〜３５μｍの厚さで塗布した。この粘着層側に実施例１と同様のリードフレームを載せて積層し、その端子部のアウター側が基材フィルムに接当した状態（図８参照、埋入深さ約３５μｍ）、高圧水銀灯にて紫外線を照射し、粘着剤を充分硬化させることで貼り合わせを行った。 Example 2
FTFE having a thickness of 50 μm was prepared by mixing a UV curable adhesive prepared by mixing 80 parts by weight of acrylic ester (2-ethylhexyl acrylate) with 0.5 parts by weight of 20 parts by weight of acrylic acid and “Irgacure 184” manufactured by Ciba Geigy. The film was applied to a thickness of about 30 to 35 μm. A lead frame similar to that of Example 1 was placed on the adhesive layer side and laminated, and the outer side of the terminal portion was in contact with the base film (see FIG. 8, depth of embedding about 35 μm), using a high pressure mercury lamp. Bonding was performed by irradiating ultraviolet rays and sufficiently curing the adhesive.

以下、実施例１と同様に処理したところ、得られたＬＬＧＡは、樹脂のはみ出しもなく、また各リード端子部分に３５μｍ程度のスタンドオフを作成することができた。更に、樹脂封止後の耐熱性シートの剥離性も良好であった。   Thereafter, the same treatment as in Example 1 was carried out. As a result, the obtained LLGA did not protrude from the resin, and a standoff of about 35 μm could be formed in each lead terminal portion. Furthermore, the peelability of the heat-resistant sheet after resin sealing was also good.

比較例１
２５μｍポリイミドフィルム（東レデュポン製カプトン１００Ｈ）を基材として、シリコーン系粘着材（東レダウコーニング製ＳＤ−４５８７Ｌ）を用いた厚さ５μｍの粘着層を設けた耐熱性粘着テープを作成した。 Comparative Example 1
Using a 25 μm polyimide film (Toray DuPont Kapton 100H) as a base material, a heat-resistant adhesive tape provided with a 5 μm thick adhesive layer using a silicone-based adhesive material (SD-487L manufactured by Toray Dow Corning) was prepared.

このテープを実施例１の耐熱性シートと同様にリードフレームに貼り合わせた（実質的に埋入せず）以外は、実施例１と同様に処理したが、端子部分への樹脂の廻りこみを充分に抑えることができず、約６０％以上の端子にフラッシュバリが認められた。また、スタンドオフも実質的にほとんど確認できなかった。   The tape was processed in the same manner as in Example 1 except that the tape was bonded to the lead frame in the same manner as in the heat-resistant sheet of Example 1 (substantially not embedded), but the resin wraps around the terminal portion. The flash burrs were observed at about 60% or more of the terminals. Moreover, virtually no standoffs were confirmed.

１０ リードフレーム
１１ａ 開口部
１１ｂ 端子部
１１ｃ ダイパッド
１１ｆ〜ｇ 端子部
１５ 半導体チップ
１５ａ 電極パッド
１６ ボンディングワイヤ
１７ 封止樹脂
２０ 耐熱性シート
２０ａ 非多孔質層
２０ｂ 多孔質層
２０ｃ 樹脂層
２０ｄ 基材層
２１ 封止された構造物
２１ａ 半導体装置 DESCRIPTION OF SYMBOLS 10 Lead frame 11a Opening part 11b Terminal part 11c Die pad 11f-g Terminal part 15 Semiconductor chip 15a Electrode pad 16 Bonding wire 17 Sealing resin 20 Heat resistant sheet 20a Non-porous layer 20b Porous layer 20c Resin layer 20d Base material layer 21 Sealed structure 21a Semiconductor device

Claims (2)

半導体チップを樹脂封止する際に封止樹脂面から突出可能な端子部を有するリードフレームと、その端子部の突出側を深さ５μｍ以上で埋入させた耐熱性シートとを備え、
前記耐熱性シートが、前記端子部の突出側を埋入させた後に硬化反応させた樹脂層と、その樹脂層が接着した基材層とを備えるリードフレーム積層物。 A lead frame having a terminal portion that can protrude from the sealing resin surface when the semiconductor chip is resin-sealed, and a heat-resistant sheet in which the protruding side of the terminal portion is embedded at a depth of 5 μm or more,
A lead frame laminate comprising a resin layer in which the heat-resistant sheet has been subjected to a curing reaction after embedding the protruding side of the terminal portion, and a base material layer to which the resin layer is adhered. 請求項１に記載のリードフレーム積層物のインナー側の端子部に半導体チップを電気的に接続した状態で、その半導体チップを封止樹脂によりインナー側から樹脂封止する工程を含む半導体装置の製造方法。   A manufacturing method of a semiconductor device including a step of resin-sealing the semiconductor chip from the inner side with a sealing resin in a state where the semiconductor chip is electrically connected to the terminal portion on the inner side of the lead frame laminate according to claim 1. Method.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014531340A (en) * 2011-09-06 2014-11-27 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ COMPRESSION TOOL FOR PRODUCING SILICON MEMBER AND METHOD FOR PRODUCING SILICONE MEMBER

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982741A (en) * 1995-09-19 1997-03-28 Seiko Epson Corp Chip carrier structure and its manufacture
JPH09246427A (en) * 1996-03-12 1997-09-19 Dainippon Printing Co Ltd Surface packaged semiconductor device and its manufacturing method
JP2000294579A (en) * 1999-04-06 2000-10-20 Nitto Denko Corp Resin sealing method of semiconductor chip and release film used therefor
JP2000307045A (en) * 1999-04-23 2000-11-02 Matsushita Electronics Industry Corp Lead frame and manufacture of resin sealed semiconductor device using it
JP2001024001A (en) * 1999-07-12 2001-01-26 Matsushita Electronics Industry Corp Manufacture of resin-encapsulated semiconductor device and lead frame

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982741A (en) * 1995-09-19 1997-03-28 Seiko Epson Corp Chip carrier structure and its manufacture
JPH09246427A (en) * 1996-03-12 1997-09-19 Dainippon Printing Co Ltd Surface packaged semiconductor device and its manufacturing method
JP2000294579A (en) * 1999-04-06 2000-10-20 Nitto Denko Corp Resin sealing method of semiconductor chip and release film used therefor
JP2000307045A (en) * 1999-04-23 2000-11-02 Matsushita Electronics Industry Corp Lead frame and manufacture of resin sealed semiconductor device using it
JP2001024001A (en) * 1999-07-12 2001-01-26 Matsushita Electronics Industry Corp Manufacture of resin-encapsulated semiconductor device and lead frame

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014531340A (en) * 2011-09-06 2014-11-27 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ COMPRESSION TOOL FOR PRODUCING SILICON MEMBER AND METHOD FOR PRODUCING SILICONE MEMBER

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