JP5275159B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP5275159B2
JP5275159B2 JP2009164868A JP2009164868A JP5275159B2 JP 5275159 B2 JP5275159 B2 JP 5275159B2 JP 2009164868 A JP2009164868 A JP 2009164868A JP 2009164868 A JP2009164868 A JP 2009164868A JP 5275159 B2 JP5275159 B2 JP 5275159B2
Authority
JP
Japan
Prior art keywords
adhesive tape
heat
sealing
semiconductor chip
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2009164868A
Other languages
Japanese (ja)
Other versions
JP2009239308A (en
Inventor
康雄 中塚
伸明 丸岡
喜久 古田
均 高野
憲兼 名畑
貞利 種ケ嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP2009164868A priority Critical patent/JP5275159B2/en
Publication of JP2009239308A publication Critical patent/JP2009239308A/en
Application granted granted Critical
Publication of JP5275159B2 publication Critical patent/JP5275159B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Adhesive Tapes (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thermosetting type die-bonding film suppressing the growth of a void on a boundary between the die-bonding film and an adherend, even in an exposure for a long time at a high temperature, and being capable of improving a reliability on the bonding of the adherend and a semiconductor chip. <P>SOLUTION: A manufacturing method for a semiconductor device at least contains a loading process bonding the semiconductor chip on a die pad for a metallic lead frame laminating a heat-resistant adhesive tape on the outer-pad side and a connecting process electrically connecting the front end of the terminal section of the lead frame and an electrode pad on the semiconductor chip. The manufacturing method for the semiconductor device, at least contains a sealing process one-surface sealing the semiconductor-chip side by a sealing resin and a cutting process cutting a sealed structure into discrete semiconductor device, and in the sealing process, the heat-resistant adhesive tape is peeled and heated, after a heating for a prescribed time. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、耐熱性粘着テープを貼り合わせた金属製のリードフレームを用いる半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device using a metal lead frame bonded with a heat-resistant adhesive tape.

近年、ＬＳＩの実装技術において、ＣＳＰ（Ｃｈｉｐ Ｓｉｚｅ／Ｓｃａｌｅ Ｐａｃｋａｇｅ）技術が注目されている。この技術のうち、ＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ−ｌｅａｄｅｄ ｐａｃｋａｇｅ）に代表されるリード端子がパッケージ内部に取り込まれた形態のパッケージについては、小型化と高集積の面で特に注目されるパッケージ形態のひとつである。このようなＱＦＮの製造方法のなかでも、近年では複数のＱＦＮ用チップをリードフレームのパッケージパターン領域のダイパッド上に整然と配列し、金型のキャビティ内で、封止樹脂にて一括封止したのち、切断によって個別のＱＦＮ構造物に切り分けることにより、リードフレーム面積あたりの生産性を飛躍的に向上させる製造方法が、特に注目されている。   In recent years, CSP (Chip Size / Scale Package) technology has attracted attention in LSI mounting technology. Among these technologies, a package in which a lead terminal represented by a QFN (Quad Flat Non-leaded package) is incorporated in the package is one of the package forms that are particularly noted in terms of miniaturization and high integration. is there. Among such QFN manufacturing methods, in recent years, a plurality of QFN chips are regularly arranged on a die pad in a package pattern region of a lead frame, and then collectively sealed with a sealing resin in a mold cavity. A manufacturing method that dramatically improves the productivity per lead frame area by cutting into individual QFN structures by cutting has attracted particular attention.

このような、複数の半導体チップを一括封止するＱＦＮの製造方法においては、樹脂封止時のモールド金型によってクランプされる領域はパッケージパターン領域より更に外側に広がった樹脂封止領域の外側だけである。従って、パッケージパターン領域、特にその中央部においては、アウターリード面をモールド金型に十分な圧力で押さえることができず、封止樹脂がアウターリード側に漏れ出すことを抑えることが非常に難しく、ＱＦＮの端子等が樹脂で被覆されるという問題が生じ易い。   In such a QFN manufacturing method that collectively seals a plurality of semiconductor chips, the region clamped by the molding die at the time of resin sealing is only outside the resin sealing region that spreads further outside the package pattern region. It is. Therefore, in the package pattern region, particularly in the center thereof, the outer lead surface cannot be pressed against the mold with sufficient pressure, and it is very difficult to suppress the sealing resin from leaking to the outer lead side. The problem of QFN terminals and the like being covered with resin is likely to occur.

このため、上記の如きＱＦＮの製造方法に対しては、リードフレームのアウターリード側に粘着テープを貼り付け、この粘着テープの自着力（マスキング）を利用したシール効果により、樹脂封止時のアウターリード側への樹脂漏れを防ぐ製造方法が特に効果的と考えられる。   For this reason, in the QFN manufacturing method as described above, an adhesive tape is attached to the outer lead side of the lead frame, and the sealing effect using the self-adhesive force (masking) of this adhesive tape allows the outer sealing at the time of resin sealing. A manufacturing method that prevents resin leakage to the lead side is considered to be particularly effective.

このような製造方法において、リードフレーム上に半導体チップを搭載した後、あるいはワイヤボンディングを実施した後から耐熱性粘着テープの貼り合せを行うことは、ハンドリングの面で実質的に困難であることから、耐熱性粘着テープは最初の段階でリードフレームのアウターパット面に貼り合わせられ、その後、半導体チップの搭載工程やワイヤボンディングの工程を経て、封止樹脂による封止工程まで貼り合わせられることが望ましい。したがって、耐熱性粘着テープとしては、単に封止樹脂の漏れ出しを防止するだけでなく、半導体チップの搭載工程に耐える高度な耐熱性や、ワイヤボンデイング工程における繊細な操作性に支障をきたさないなど、これらのすべての工程を満足する特性が要求される。   In such a manufacturing method, it is substantially difficult to handle the heat-resistant adhesive tape after mounting a semiconductor chip on a lead frame or after performing wire bonding. In addition, it is desirable that the heat-resistant adhesive tape is bonded to the outer pad surface of the lead frame in the first stage, and then bonded to the sealing process with the sealing resin through the semiconductor chip mounting process and the wire bonding process. . Therefore, as a heat-resistant adhesive tape, not only does it prevent leakage of the sealing resin, but it does not interfere with the high heat resistance that can withstand the mounting process of the semiconductor chip and the delicate operability in the wire bonding process. Therefore, characteristics satisfying all these steps are required.

しかしながら、樹脂漏れを防ぐ目的から高度な粘着性を重要視するあまり一般の耐熱性粘着テープを利用すると、粘着剤が高い弾性であるため、実際にはワイヤボンディングができなくなってしまうなど、一連の製造工程を経ていく中で相反する必要特性を同時に満足することが困難である。   However, if a general heat-resistant adhesive tape that emphasizes high adhesiveness for the purpose of preventing resin leakage is used, the adhesive is highly elastic, and in practice, wire bonding cannot be performed. It is difficult to satisfy the conflicting required characteristics at the same time through the manufacturing process.

一方、リードフレームを用いる代わりに、半導体チップを配置する開口部とその外側の表面に配置される端子部とその端子部の裏側面に配置されるアウターパッドとを有する配線樹脂基板を用いて、前記開口部に半導体チップを配置してワイヤボンデイング工程や封止樹脂による封止工程を行うことで、半導体装置を製造する方法も知られている。そして、この製法では、リードフレームより厚みが大きい配線樹脂基板を用いているにも係わらず、リードフレームを用いる場合と同様に、樹脂封止時のアウターリード側への樹脂漏れが生じることが判明した。また、配線樹脂基板を用いているため、ワイヤボンデイング工程における耐熱性粘着テープの粘着剤層の影響が、リードフレームを用いる場合と異なることが判明した。   On the other hand, instead of using the lead frame, using a wiring resin substrate having an opening for arranging the semiconductor chip, a terminal portion arranged on the outer surface thereof, and an outer pad arranged on the back side surface of the terminal portion, There is also known a method of manufacturing a semiconductor device by disposing a semiconductor chip in the opening and performing a wire bonding process or a sealing process with a sealing resin. And in this manufacturing method, it turns out that the resin leakage to the outer lead side at the time of resin sealing occurs as in the case of using the lead frame, even though the wiring resin substrate having a thickness larger than that of the lead frame is used. did. Moreover, since the wiring resin substrate was used, it turned out that the influence of the adhesive layer of the heat resistant adhesive tape in a wire bonding process differs from the case where a lead frame is used.

そこで、本発明の目的は、耐熱性粘着テープにより封止工程での樹脂漏れを好適に防止しながら、しかも貼着したテープが一連の工程で支障を来たしにくい半導体装置の製造方法を提供することにある。   Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a tape that has been adhered is less likely to cause trouble in a series of steps while suitably preventing resin leakage in a sealing step with a heat-resistant adhesive tape. It is in.

本発明者らは、上記目的を達成すべく、耐熱性粘着テープの物性、材料、厚み等について鋭意研究したところ、特定の線熱膨張係数を有する基材層と、特定の厚さを有する粘着剤層とからなる耐熱性粘着テープを用いることにより、上記目的を達成できることを見出し、本発明を完成するに至った。   In order to achieve the above object, the present inventors have conducted intensive research on the physical properties, materials, thickness, etc. of the heat-resistant adhesive tape, and found that the substrate layer has a specific linear thermal expansion coefficient and the adhesive having a specific thickness. The present inventors have found that the above object can be achieved by using a heat-resistant pressure-sensitive adhesive tape comprising an agent layer, and have completed the present invention.

即ち、本発明の半導体装置の製造方法は、アウターパッド側に耐熱性粘着テープを貼り合わせた金属製のリードフレームのダイパッド上に半導体チップをボンディングする搭載工程と、前記リードフレームの端子部先端と前記半導体チップ上の電極パッドとをボンディングワイヤで電気的に接続する結線工程と、封止樹脂により半導体チップ側を片面封止する封止工程と、封止された構造物を個別の半導体装置に切断する切断工程とを、少なくとも含み、前記封止工程は、所定時間の加熱の後、前記耐熱性粘着テープを剥離し、その後さらに加熱する工程であることを特徴とする。
前記耐熱性粘着テープは、５０〜２５０℃における線熱膨張係数１. ０×１０−５〜３. ０×１０−５／Ｋの基材層と、厚さ２μｍ以上１０μｍ以下の粘着剤層とから構成されており、前記粘着剤層の２００℃における貯蔵弾性率が５．０×１０３Ｎ／ｃｍ２以上であることが好ましい。 That is, the semiconductor device manufacturing method of the present invention includes a mounting step of bonding a semiconductor chip on a die pad of a metal lead frame in which a heat-resistant adhesive tape is bonded to the outer pad side, and a terminal portion tip of the lead frame; A wiring process for electrically connecting the electrode pads on the semiconductor chip with a bonding wire, a sealing process for sealing one side of the semiconductor chip with a sealing resin, and the sealed structure in an individual semiconductor device A cutting step for cutting, and the sealing step is a step of peeling the heat-resistant adhesive tape after heating for a predetermined time, and further heating.
The heat resistant adhesive tape comprises a base material layer having a linear thermal expansion coefficient of 1.0 × 10 −5 to 3.0 × 10 −5 / K at 50 to 250 ° C., and an adhesive layer having a thickness of 2 μm to 10 μm. It is preferable that the storage elastic modulus at 200 ° C. of the pressure-sensitive adhesive layer is 5.0 × 10 3 N / cm 2 or more.

また、本発明の半導体装置の製造方法は、半導体チップを配置する開口部とその外側の表面に配置される端子部とその端子部の裏側面に配置されるアウターパッドとを有する配線樹脂基板の前記アウターパッド側に耐熱性粘着テープを貼り合わせる貼着工程と、前記開口部に半導体チップを配置する搭載工程と、前記配線樹脂基板の端子部と前記半導体チップ上の電極パッドとをボンディングワイヤで電気的に接続する結線工程と、封止樹脂により半導体チップ側を片面封止する封止工程と、封止された構造物を個別の半導体装置に切断する切断工程とを、少なくとも含み、前記封止工程は、所定時間の加熱の後、前記耐熱性粘着テープを剥離し、その後さらに加熱する工程であることを特徴とする。
前記耐熱性粘着テープは、５０〜２５０℃における線熱膨張係数０．８×１０−５〜５．６×１０−５／Ｋの基材層と、厚さ２μｍ以上５０μｍ以下の粘着剤層とから構成されており、前記粘着剤層の２００℃における貯蔵弾性率が５．０×１０３Ｎ／ｃｍ２以上であることが好ましい。 The method for manufacturing a semiconductor device according to the present invention includes a wiring resin substrate having an opening for arranging a semiconductor chip, a terminal portion arranged on the outer surface thereof, and an outer pad arranged on the back side surface of the terminal portion. A bonding process of bonding a heat-resistant adhesive tape to the outer pad side, a mounting process of placing a semiconductor chip in the opening, a terminal portion of the wiring resin substrate, and an electrode pad on the semiconductor chip with bonding wires The sealing step includes at least a wiring step for electrical connection, a sealing step for sealing one side of the semiconductor chip with a sealing resin, and a cutting step for cutting the sealed structure into individual semiconductor devices. The stopping step is a step of peeling the heat-resistant adhesive tape after heating for a predetermined time and then further heating.
The heat-resistant adhesive tape comprises a base material layer having a linear thermal expansion coefficient of 0.8 × 10 −5 to 5.6 × 10 −5 / K at 50 to 250 ° C., and an adhesive layer having a thickness of 2 μm or more and 50 μm or less. It is preferable that the storage elastic modulus at 200 ° C. of the pressure-sensitive adhesive layer is 5.0 × 10 3 N / cm 2 or more.

上記において、前記基材層が、ポリエチレンテレフタレート（ＰＥＴ) フィルム、ポリエチレンナフタレート（ＰＥＮ）フィルム、ポリエーテルサルフォン（ＰＥＳ）フィルム、ポリエーテルイミド（ＰＥＩ）フィルム、ポリサルフォン（ＰＳＦ）フィルム、ポリフェニレンサルファイド（ＰＰＳ）フィルム、ポリエーテルエーテルケトン（ＰＥＥＫ）フィルム、ポリアリレート（ＰＡＲ）フィルム、アラミドフィルム、ポリイミドフィルム、又は液晶ポリマー（ＬＣＰ）フィルムからなることが好ましい。特に、金属製のリードフレームを用いる場合、前記基材層がポリイミド材料からなることが好ましい。   In the above, the base material layer comprises a polyethylene terephthalate (PET) film, a polyethylene naphthalate (PEN) film, a polyethersulfone (PES) film, a polyetherimide (PEI) film, a polysulfone (PSF) film, a polyphenylene sulfide ( It is preferably composed of a PPS) film, a polyetheretherketone (PEEK) film, a polyarylate (PAR) film, an aramid film, a polyimide film, or a liquid crystal polymer (LCP) film. In particular, when a metal lead frame is used, the base material layer is preferably made of a polyimide material.

また、前記粘着剤層がシリコーン系粘着剤からなることが好ましく、前記粘着剤層の２００℃における貯蔵弾性率が５．０×１０3 Ｎ／ｃｍ2 以上であることが好ましい。 Moreover, it is preferable that the said adhesive layer consists of silicone type adhesives, and it is preferable that the storage elastic modulus in 200 degreeC of the said adhesive layer is 5.0 * 10 < 3 > N / cm < 2 > or more.

更に、前記耐熱性粘着テープは、ＪＩＳ Ｃ２１０７に準拠した２００℃加熱後の粘着力が０．０５〜４．０Ｎ／１９ｍｍ幅であることが好ましい。   Furthermore, it is preferable that the heat resistant adhesive tape has an adhesive strength after heating at 200 ° C. according to JIS C2107 of 0.05 to 4.0 N / 19 mm width.

［作用効果］
本発明によると、耐熱性粘着テープの基材層の線熱膨張係数が金属のそれに近いため、熱膨張によるソリや剥がれが生じにくく、高いシール効果が維持できるため、封止工程での樹脂漏れを好適に防止することができる。また粘着剤層の厚みが適切であるため、絶対的な変形量が抑えられることから、粘着機能そのものを著しく損なうことなく、粘着剤層全体としてのクッション性をわずかにとどめることが可能になる。このため、実施例の結果が示すように、耐熱性粘着テープにより封止工程での樹脂漏れを好適に防止しながら、しかも貼着したテープが一連の工程で支障を来たしにくいものとなる。 [Function and effect]
According to the present invention, since the linear thermal expansion coefficient of the base material layer of the heat-resistant adhesive tape is close to that of metal, warpage and peeling due to thermal expansion are unlikely to occur, and a high sealing effect can be maintained. Can be suitably prevented. Further, since the thickness of the pressure-sensitive adhesive layer is appropriate, the amount of absolute deformation can be suppressed, so that the cushioning property of the whole pressure-sensitive adhesive layer can be kept slightly without significantly deteriorating the pressure-sensitive adhesive function itself. For this reason, as the result of an Example shows, while sticking the resin suitably in a sealing process with a heat resistant adhesive tape suitably, the stuck tape becomes difficult to cause trouble in a series of processes.

また、リードフレームの代わりに、半導体チップを配置する開口部とその外側の表面に配置される端子部とその端子部の裏側面に配置されるアウターパッドとを有する配線樹脂基板を用いて上記工程を行う場合、上記と同様に耐熱性粘着テープの基材層の線熱膨張係数を配線樹脂基板に近づけることができると共に、配線樹脂基板との関係で粘着剤層の厚みが適切となるため、上記と同様の作用効果を得ることができる。   Further, instead of the lead frame, the above-described process is performed using a wiring resin substrate having an opening for arranging the semiconductor chip, a terminal portion arranged on the outer surface thereof, and an outer pad arranged on the back side surface of the terminal portion. In the same manner as described above, the linear thermal expansion coefficient of the base layer of the heat-resistant adhesive tape can be brought close to the wiring resin substrate, and the thickness of the pressure-sensitive adhesive layer becomes appropriate in relation to the wiring resin substrate. The same effect as described above can be obtained.

前記基材層がポリイミド材料からなる場合、耐熱性が高いことに加えて、線熱膨張係数が金属製のリードフレームと殆ど同じで、しかも加工性やハンドリング性も良好なため、本発明における基材層として最も好ましい材料となる。前記他の樹脂フィルムを用いる場合も、配線樹脂基板の材質に応じて同様の効果が得られる。   When the base material layer is made of a polyimide material, in addition to high heat resistance, the linear thermal expansion coefficient is almost the same as that of a metal lead frame, and the workability and handling properties are also good. This is the most preferable material for the material layer. Even when the other resin film is used, the same effect can be obtained according to the material of the wiring resin substrate.

前記粘着剤層がシリコーン系粘着剤からなる場合、耐熱性が高いことに加えて、２００℃における貯蔵弾性率や２００℃加熱後の粘着力が適切な値となりやすく、本発明における粘着剤として最も好ましい材料となる。   When the pressure-sensitive adhesive layer is made of a silicone-based pressure-sensitive adhesive, in addition to high heat resistance, the storage elastic modulus at 200 ° C. and the pressure-sensitive adhesive force after heating at 200 ° C. are likely to be appropriate values. Preferred material.

前記粘着剤層の２００℃における貯蔵弾性率が５．０×１０3 Ｎ／ｃｍ2 以上である場合、材料自体の弾性率が適切なため、粘着剤層の厚みが比較的厚くても、より確実に好適なワイヤボンディングが可能になる。 When the storage elastic modulus at 200 ° C. of the pressure-sensitive adhesive layer is 5.0 × 10 3 N / cm 2 or more, since the elastic modulus of the material itself is appropriate, even if the thickness of the pressure-sensitive adhesive layer is relatively thick, Certainly suitable wire bonding becomes possible.

更に、前記耐熱性粘着テープは、ＪＩＳ Ｃ２１０７に準拠した２００℃加熱後の粘着力が０．０５〜４．０Ｎ／１９ｍｍ幅である場合、封止工程での樹脂漏れ防止に必要な粘着力が得られると共に、封止工程後の引き剥がしが容易になり、封止樹脂の破損も生じなくなる。   Furthermore, when the adhesive strength after heating at 200 ° C. in accordance with JIS C2107 is 0.05 to 4.0 N / 19 mm width, the heat resistant adhesive tape has an adhesive strength necessary for preventing resin leakage in the sealing process. In addition to being obtained, it is easy to peel off after the sealing step, and the sealing resin is not damaged.

本発明の半導体装置の製造方法の一例を示す工程図である。It is process drawing which shows an example of the manufacturing method of the semiconductor device of this invention. 本発明におけるリードフレームの一例を示す図であり、（ａ）は正面図、（ｂ）は要部拡大図、（ｃ）は樹脂封止後の状態を示す底面図である。It is a figure which shows an example of the lead frame in this invention, (a) is a front view, (b) is a principal part enlarged view, (c) is a bottom view which shows the state after resin sealing. 本発明における樹脂封止工程の一例を示す縦断面図である。It is a longitudinal cross-sectional view which shows an example of the resin sealing process in this invention. 本発明の半導体装置の製造方法の他の例を示す工程図である。It is process drawing which shows the other example of the manufacturing method of the semiconductor device of this invention.

以下、本発明の実施の形態について、図面を参照しながら説明する。図１は、本発明の半導体装置の製造方法の一例の工程図である。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a process chart of an example of a method for manufacturing a semiconductor device of the present invention.

本発明の半導体装置の製造方法は、図１（ａ）〜（ｅ）に示すように、半導体チップ１５の搭載工程と、ボンディングワイヤ１６による結線工程と、封止樹脂１７による封止工程と、封止された構造物２１を切断する切断工程とを少なくとも含むものである。   1A to 1E, the semiconductor device manufacturing method of the present invention includes a semiconductor chip 15 mounting step, a bonding step using a bonding wire 16, and a sealing step using a sealing resin 17. A cutting step of cutting the sealed structure 21 at least.

搭載工程は、図１（ａ）〜（ｂ）に示すように、アウターパッド側（図の下側）に耐熱性粘着テープ２０を貼り合わせた金属製のリードフレーム１０のダイパッド１１ｃ上に半導体チップ１５をボンディングする工程である。   As shown in FIGS. 1A to 1B, the mounting process is performed by placing a semiconductor chip on a die pad 11c of a metal lead frame 10 in which a heat-resistant adhesive tape 20 is bonded to the outer pad side (lower side of the figure). 15 is a step of bonding 15.

リードフレーム１０とは、例えば銅などの金属を素材としてＱＦＮの端子パターンが刻まれたものであり、その電気接点部分には、銀，ニッケル，パラジウム，金などのなどの素材で被覆（めっき）されている場合もある。リードフレーム１０の厚みは、１００〜３００μｍが一般的である。   The lead frame 10 is made by engraving a terminal pattern of QFN using, for example, a metal such as copper, and the electrical contact portion is coated (plated) with a material such as silver, nickel, palladium, or gold. Sometimes it is. The thickness of the lead frame 10 is generally 100 to 300 μm.

リードフレーム１０は、後の切断工程にて切り分けやすいよう、個々のＱＦＮの配置パターンが整然と並べられているものが好ましい。例えば図２に示すように、リードフレーム１０上に縦横のマトリックス状に配列された形状などは、マトリックスＱＦＮあるいはＭＡＰ−ＱＦＮなどと呼ばれ、もっとも好ましいリードフレーム形状のひとつである。   The lead frame 10 is preferably one in which arrangement patterns of individual QFNs are arranged in an orderly manner so that the lead frame 10 can be easily separated in a subsequent cutting step. For example, as shown in FIG. 2, a shape arranged in a vertical and horizontal matrix on the lead frame 10 is called a matrix QFN or MAP-QFN, and is one of the most preferable lead frame shapes.

図２（ａ）〜（ｂ）に示すように、リードフレーム１０のパッケージパターン領域１１には、隣接した複数の開口１１ａに端子部１１ｂを複数配列した、ＱＦＮの基板デザインが整然と配列されている。一般的なＱＦＮの場合、各々の基板デザイン（図２（ａ）の格子で区分された領域）は、開口１１ａの周囲に配列された、アウターリード面を下側に有する端子部１１ｂと、開口１１ａの中央に配置されるダイパッド１１ｃと、ダイパッド１１ｃを開口１１ａの４角に支持させるダイバー１１ｄとで構成される。   As shown in FIGS. 2A to 2B, the QFN substrate design in which a plurality of terminal portions 11b are arranged in a plurality of adjacent openings 11a is arranged in the package pattern region 11 of the lead frame 10 in an orderly manner. . In the case of a general QFN, each board design (region divided by the lattice in FIG. 2A) is arranged around the opening 11a, the terminal portion 11b having the outer lead surface on the lower side, and the opening The die pad 11c is arranged at the center of 11a, and the diver 11d supports the die pad 11c at the four corners of the opening 11a.

耐熱性粘着テープ２０は、少なくともパッケージパターン領域１１より外側に貼着され、樹脂封止される樹脂封止領域の外側の全周を含む領域に貼着するのが好ましい。リードフレーム１０は、通常、樹脂封止時の位置決めを行うための、ガイドピン用孔１３を端辺近傍に有しており、それを塞がない領域に貼着するのが好ましい。また、樹脂封止領域はリードフレーム１０の長手方向に複数配置されるため、それらの複数領域を渡るように連続して粘着テープ２０を貼着するのが好ましい。   It is preferable that the heat-resistant adhesive tape 20 is attached at least outside the package pattern region 11 and attached to a region including the entire circumference outside the resin-sealed region to be resin-sealed. The lead frame 10 usually has a guide pin hole 13 in the vicinity of the end side for positioning at the time of resin sealing, and it is preferable that the lead frame 10 is adhered to a region where it is not blocked. In addition, since a plurality of resin sealing regions are arranged in the longitudinal direction of the lead frame 10, it is preferable to continuously adhere the adhesive tape 20 across the plurality of regions.

上記のようなリードフレーム１０上に、半導体チップ１５、すなわち半導体集積回路部分であるシリコンウエハ・チップが搭載される。リードフレーム１０上にはこの半導体チップ１５を固定するためダイパッド１１ｃと呼ばれる固定エリアが設けられており、このダイパッド１１ｃヘのボンディング（固定）の方法は導電性ペースト１９を使用したり、接着テープ、接着剤など各種の方法が用いられる。導電性ペーストや熱硬化性の接着剤等を用いてダイボンドする場合、一般的に１５０〜２００℃程度の温度で３０分〜９０分程度加熱キュアする。   On the lead frame 10 as described above, a semiconductor chip 15, that is, a silicon wafer chip which is a semiconductor integrated circuit portion is mounted. A fixing area called a die pad 11c is provided on the lead frame 10 to fix the semiconductor chip 15. A bonding (fixing) method to the die pad 11c uses a conductive paste 19, an adhesive tape, Various methods such as an adhesive are used. When die bonding is performed using a conductive paste, a thermosetting adhesive, or the like, generally heat curing is performed at a temperature of about 150 to 200 ° C. for about 30 to 90 minutes.

結線工程は、図１（ｃ）に示すように、リードフレーム１０の端子部１１ｂ（インナーリード）の先端と半導体チップ１５上の電極パッド１５ａとをボンディングワイヤ１６で電気的に接続する工程である。ボンディングワイヤ１６としては、例えば金線あるいはアルミ線などが用いられる。一般的には１５０〜２５０℃に加熱された状態で、超音波による振動エネルギーと印加加圧による圧着エネルギーの併用により結線される。その際、リードフレーム１０に貼着した耐熱性粘着テープ２０面を真空吸引することで、ヒートブロックに確実に固定することができる。   As shown in FIG. 1C, the connection process is a process of electrically connecting the tips of the terminal portions 11b (inner leads) of the lead frame 10 and the electrode pads 15a on the semiconductor chip 15 with bonding wires 16. . For example, a gold wire or an aluminum wire is used as the bonding wire 16. In general, in a state heated to 150 to 250 ° C., the wire is connected by a combination of vibration energy by ultrasonic waves and pressure energy by applying pressure. At that time, the surface of the heat-resistant adhesive tape 20 adhered to the lead frame 10 can be securely fixed to the heat block by vacuum suction.

封止工程は、図１（ｄ）に示すように、封止樹脂１７により半導体チップ側を片面封止する工程である。封止工程は、リードフレーム１０に搭載された半導体チップ１５やボンディングワイヤ１６を保護するために行われ、とくにエポキシ系の樹脂をはじめとした封止樹脂１７を用いて金型中で成型されるのが代表的である。その際、図３に示すように、複数のキャビティを有する上金型１８ａと下金型１８ｂからなる金型１８を用いて、複数の封止樹脂１７にて同時に封止工程が行われるのが一般的である。具体的には、例えば樹脂封止時の加熱温度は１７０〜１８０℃であり、この温度で数分間キュアされた後、更に、ポストモールドキュアが数時間行われる。なお、耐熱性粘着テープ２０はポストモールドキュアの前に剥離するのが好ましい。   The sealing step is a step of sealing one side of the semiconductor chip side with a sealing resin 17 as shown in FIG. The sealing process is performed to protect the semiconductor chip 15 and the bonding wire 16 mounted on the lead frame 10 and is molded in a mold using a sealing resin 17 including an epoxy resin in particular. Is typical. At that time, as shown in FIG. 3, a sealing process is simultaneously performed with a plurality of sealing resins 17 using a mold 18 composed of an upper mold 18a and a lower mold 18b having a plurality of cavities. It is common. Specifically, for example, the heating temperature at the time of resin sealing is 170 to 180 ° C. After curing at this temperature for several minutes, post mold curing is further performed for several hours. The heat resistant adhesive tape 20 is preferably peeled before post mold curing.

切断工程は、図１（ｅ）に示すように、封止された構造物２１を個別の半導体装置２１ａに切断する工程である。一般的にはダイサーなどの回転切断刃を用いて封止樹脂１７の切断部１７ａをカットする切断工程が挙げられる。   The cutting step is a step of cutting the sealed structure 21 into individual semiconductor devices 21a as shown in FIG. Generally, there is a cutting step of cutting the cutting portion 17a of the sealing resin 17 using a rotary cutting blade such as a dicer.

本発明では、上述のような製造工程に用いられる耐熱性粘着テープ２０が、５０〜２５０℃における線熱膨張係数１. ０×１０-5〜３. ０×１０-5／Ｋの基材層と、厚さ１０μｍ以下の粘着剤層とから構成されていることを特徴とする。耐熱性粘着テープ２０は、あらかじめリードフレーム１０に貼着されていることから、前述の製造工程において加熱されることになる。たとえば、半導体チップ１５をダイボンドする場合、一般的に１５０〜２００℃程度の温度で３０分〜９０分程度加熱キュアする。ワイヤボンディングを行う場合は、例えば１６０〜２３０℃程度の温度で行われるが、一枚のリードフレームからたくさんの半導体装置を製造する場合は、すべての半導体装置に対するボンディングが終了するまでの時間として、リードフレーム１枚あたり１時間以上を要することも考えられる。さらに、樹脂封止する場合も、樹脂が十分に溶融している温度である必要性から１７５℃程度の温度をかけることになる。したがって、こういった加熱条件に対して、これらの耐熱性を満足する耐熱性粘着テープである必要がある。 In the present invention, the heat-resistant pressure-sensitive adhesive tape 20 used in the manufacturing process as described above is a base material layer having a linear thermal expansion coefficient of 1.0 × 10 −5 to 3.0 × 10 −5 / K at 50 to 250 ° C. And an adhesive layer having a thickness of 10 μm or less. Since the heat-resistant adhesive tape 20 is attached to the lead frame 10 in advance, it is heated in the manufacturing process described above. For example, when the semiconductor chip 15 is die-bonded, it is generally heated and cured at a temperature of about 150 to 200 ° C. for about 30 to 90 minutes. When performing wire bonding, for example, it is performed at a temperature of about 160 to 230 ° C., but when many semiconductor devices are manufactured from one lead frame, the time until bonding for all the semiconductor devices is completed, It can be considered that one lead frame or more is required for one hour or more. Further, in the case of resin sealing, a temperature of about 175 ° C. is applied because the resin needs to be sufficiently melted. Therefore, the heat-resistant pressure-sensitive adhesive tape needs to satisfy these heat resistances under such heating conditions.

耐熱性粘着テープ２０が貼り合わされるリードフレーム１０は、前述のように銅をはじめとした金属素材であることから、線熱膨張係数として１．８〜１．９×１０-5／Ｋ程度であることが一般的である。したがって、これらに貼り合わされる耐熱性粘着テープ２０の線熱膨張係数が、リードフレームとあまりに大きく違っていては、両者が貼り合わせられた状態で加熱されたとき、両者の熱膨張の差異からひずみを生じることになり、結果的に耐熱性粘着テープにしわやはがれを生じてしまう。そのため、耐熱性粘着テープを構成する基材部分の線熱膨張係数としても、リードフレーム素材に近い１. ０×１０-5〜３. ０×１０-5／Ｋの基材層を採用するが、好ましくは線熱膨張係数が１．５×１０-5〜２．５×１０-5／Ｋ以下である。 Since the lead frame 10 to which the heat-resistant adhesive tape 20 is bonded is a metal material such as copper as described above, the linear thermal expansion coefficient is about 1.8 to 1.9 × 10 −5 / K. It is common to be. Therefore, if the linear thermal expansion coefficient of the heat-resistant adhesive tape 20 to be bonded to these is too much different from that of the lead frame, when heated in a state in which both are bonded, distortion is caused by the difference in thermal expansion between the two. As a result, the heat-resistant adhesive tape is wrinkled and peeled off. Therefore, a base layer of 1.0 × 10 −5 to 3.0 × 10 −5 / K close to the lead frame material is adopted as the linear thermal expansion coefficient of the base portion constituting the heat resistant adhesive tape. The linear thermal expansion coefficient is preferably 1.5 × 10 −5 to 2.5 × 10 −5 / K or less.

このような基材としては、アルミなどの金属箔もあげられるが、線熱膨張係数２．０×１０-5〜２．４×１０-5／Ｋ程度のポリイミド材料は加工性やハンドリング性も高く、もっとも好ましい素材のひとつである。ここで、線熱膨張係数は、ＡＳＴＭ Ｄ６９６に準拠して、ＴＭＡ（サーモ・メカニカル・アナリシス）により測定される値である。 Examples of such a base material include a metal foil such as aluminum, but a polyimide material having a linear thermal expansion coefficient of about 2.0 × 10 −5 to 2.4 × 10 −5 / K has processability and handling properties. It is one of the most preferred materials. Here, the linear thermal expansion coefficient is a value measured by TMA (thermo-mechanical analysis) in accordance with ASTM D696.

また、ＰＥＴフィルム、ＰＥＮフィルム、ＰＥＳフィルム、ＰＥＩフィルム、ＰＳＦフィルム、ＰＥＥＫフィルム、ＰＰＳフィルム、ＰＡＲフィルム、アラミドフィルム、ＬＣＰフィルムの中から、線熱膨張係数が１. ０×１０-5 〜３. ０×１０-5 ／Ｋのものを選択してもよい。 In addition, the coefficient of linear thermal expansion is 1.0 × 10 −5 to 3. out of PET film, PEN film, PES film, PEI film, PSF film, PEEK film, PPS film, PAR film, aramid film, and LCP film. You may select the thing of 0x10 < -5 > / K.

耐熱性粘着テープ２０の基材層の厚みは、折れや裂けを防止し、好適なハンドリング性に鑑みて５〜２５０μｍが好ましい。   The thickness of the base material layer of the heat resistant pressure-sensitive adhesive tape 20 is preferably 5 to 250 μm in view of suitable handling properties, preventing breakage and tearing.

また、粘着テープ２０を構成する粘着剤層は、その粘着機能の面からある程度の弾性が必要であるが、粘着剤層全体としてあまりに柔らかい場合は、ワイヤボンディング時にボンディングワイヤを接続しようとしても、粘着テープを貼りあわせたリードフレームを十分に固定しておくことが粘着剤層の弾性力によって阻害され、結果的に加圧による圧着エネルギーを緩和してしまい、ボンディング不良が発生してしまう。   In addition, the pressure-sensitive adhesive layer constituting the pressure-sensitive adhesive tape 20 needs to have a certain degree of elasticity in terms of its pressure-sensitive adhesive function, but if the pressure-sensitive adhesive layer as a whole is too soft, even if an attempt is made to connect a bonding wire during wire bonding, the pressure-sensitive adhesive layer Sufficiently fixing the lead frame to which the tape is bonded is hindered by the elastic force of the pressure-sensitive adhesive layer. As a result, the pressure-bonding energy due to pressurization is alleviated, resulting in bonding failure.

このようなボンディング不良を引き起こさず、かつ封止工程では樹脂漏れを防止できる十分な粘着力を確保する、いわば相反する性能を確保するために、本発明では粘着剤層の厚みを１０μｍ以下、より好ましくは２〜５μｍの薄層にする。これにより、絶対的な変形量が抑えられることから、粘着機能そのものを著しく損なうことなく、粘着剤層全体としてのクッション性をわずかにとどめることが可能になる。さらに好ましくは、２００℃における粘着剤層の貯蔵弾性率が５．０×１０3 Ｎ／ｃｍ2 以上であれば、粘着剤層の厚みが比較的厚くても、より確実に好適なワイヤボンディングが可能になる。ここで、貯蔵弾性率はＡＳＴＭ ＳＴＰ８４６に準拠して、粘弾性スペクトロメーターによって測定される値である。 In order to ensure sufficient adhesive strength that does not cause such bonding failure and can prevent resin leakage in the sealing process, in other words, in order to ensure conflicting performance, in the present invention, the thickness of the pressure-sensitive adhesive layer is 10 μm or less. Preferably, it is a thin layer of 2 to 5 μm. Thereby, since the absolute deformation amount can be suppressed, the cushioning property as the whole pressure-sensitive adhesive layer can be kept slightly without significantly deteriorating the adhesive function itself. More preferably, if the storage elastic modulus of the pressure-sensitive adhesive layer at 200 ° C. is 5.0 × 10 3 N / cm 2 or more, even if the thickness of the pressure-sensitive adhesive layer is relatively thick, more suitable wire bonding can be achieved more reliably. It becomes possible. Here, the storage elastic modulus is a value measured by a viscoelastic spectrometer based on ASTM STP846.

一方、耐熱性粘着テープは、封止工程後の任意の段階ではがされることになるが、あまりに強粘着力をもった粘着テープであっては引き剥がしが困難となるだけでなく、場合によっては引き剥がしのための応力によって、モールドした樹脂の剥離や破損を招く恐れもある。したがって、封止樹脂のはみ出しを抑える粘着力以上に強粘着であることはむしろ好ましくない。たとえば、ステンレス板に貼り合わせた状態で２００℃にて１時間加熱後の粘着力が０．０５〜４．０Ｎ／１９ｍｍ幅、好ましくは０．１〜２．０Ｎ／１９ｍｍ幅である。ここで、粘着力はＪＩＳ Ｃ２１０７に準拠して測定される値である。   On the other hand, the heat-resistant adhesive tape will be peeled off at any stage after the sealing process, but it is not only difficult to peel off with an adhesive tape with too strong adhesive force, but in some cases May cause peeling or breakage of the molded resin due to the stress for peeling. Therefore, it is rather unfavorable that the adhesive strength is stronger than the adhesive strength that suppresses the protrusion of the sealing resin. For example, the adhesive strength after heating at 200 ° C. for 1 hour in a state of being bonded to a stainless steel plate is 0.05 to 4.0 N / 19 mm width, preferably 0.1 to 2.0 N / 19 mm width. Here, the adhesive strength is a value measured according to JIS C2107.

上記のような各物性を有する粘着剤としては、耐熱性も考慮して、シリコーン系粘着剤が好ましい。   As the pressure-sensitive adhesive having the above physical properties, a silicone pressure-sensitive adhesive is preferable in consideration of heat resistance.

〔他の実施形態〕
前述の実施形態では、リードフレームを用いた半導体装置の製造方法の例を示したが、以下のように、配線樹脂基板を用いて、その開口部に半導体チップを配置してワイヤボンデイング工程や封止樹脂による封止工程を行うことで、半導体装置を製造してもよい。 [Other Embodiments]
In the above-described embodiment, an example of a method for manufacturing a semiconductor device using a lead frame has been described. However, as described below, a wiring resin substrate is used and a semiconductor chip is disposed in the opening to perform a wire bonding process or sealing. You may manufacture a semiconductor device by performing the sealing process by a stop resin.

即ち、図４（ｄ１）〜（ｄ３）に示すように、半導体チップ１５を配置する開口部２８ｃとその外側の表面に配置される端子部２８ａとその端子部２８ａの裏側面に配置されるアウターパッド２８ｂとを有する配線樹脂基板２８を用いてもよい。なお、図４（ｄ１）〜（ｄ３）は、図１（ｄ）に対応するものであり、半導体チップ１５が封止樹脂１７により封止された状態を示している。   That is, as shown in FIGS. 4D1 to 4D3, the opening 28c in which the semiconductor chip 15 is disposed, the terminal portion 28a disposed on the outer surface thereof, and the outer disposed on the back side surface of the terminal portion 28a. A wiring resin substrate 28 having pads 28b may be used. 4D1 to 4D3 correspond to FIG. 1D and show a state in which the semiconductor chip 15 is sealed with the sealing resin 17.

配線樹脂基板２８の端子部２８ａとアウターパッド２８ｂとはビアホール内の導電材料や適当な配線回路等により導電接続されているが、その構造、形状、材質等は何れでもよい。配線樹脂基板２８の樹脂材料としては、熱硬化性樹脂が通常用いられ、例えばエポキシ樹脂、フェノール樹脂、ＢＴ樹脂、ポリイミド樹脂等が挙げられる。   The terminal portion 28a and the outer pad 28b of the wiring resin substrate 28 are conductively connected by a conductive material in the via hole, an appropriate wiring circuit, or the like, but any structure, shape, material, etc. may be used. As the resin material of the wiring resin substrate 28, a thermosetting resin is usually used, and examples thereof include an epoxy resin, a phenol resin, a BT resin, and a polyimide resin.

まず、この配線樹脂基板２８に対し、そのアウターパッド２８ｂ側に耐熱性粘着テープ２０を貼り合わせる貼着工程を行う。耐熱性粘着テープ２０は、５０〜２５０℃における線熱膨張係数０．８×１０-5 〜５．６×１０-5 ／Ｋの基材層と、厚さ５０μｍ以下の粘着剤層とから構成され、好ましくは線熱膨張係数１．０×１０-5 〜３．０×１０-5 ／Ｋ、粘着剤層の厚さ２〜１０μｍである。耐熱性粘着テープ２０の他の点については、前述の実施形態と同様である。 First, an adhering step is performed for adhering the heat-resistant adhesive tape 20 to the wiring resin substrate 28 on the outer pad 28b side. The heat-resistant adhesive tape 20 is composed of a base material layer having a linear thermal expansion coefficient of 0.8 × 10 −5 to 5.6 × 10 −5 / K at 50 to 250 ° C., and an adhesive layer having a thickness of 50 μm or less. Preferably, the coefficient of linear thermal expansion is 1.0 × 10 −5 to 3.0 × 10 −5 / K, and the thickness of the pressure-sensitive adhesive layer is 2 to 10 μm. About the other point of the heat resistant adhesive tape 20, it is the same as that of the above-mentioned embodiment.

このような基材層としては、ＰＥＴフィルム、ＰＥＮフィルム、ＰＥＳフィルム、ＰＥＩフィルム、ＰＳＦフィルム、ＰＰＳフィルム、ＰＡＲフィルム、アラミドフィルム、ポリイミドフィルム、ＬＣＰフィルムが挙げられる。但し、配線樹脂基板２８の樹脂材料と線熱膨張係数が近いものを用いるのが好ましい。なお、耐熱性粘着テープ２０の他の点については、前述の実施形態と同様である。   Examples of such a base material layer include PET film, PEN film, PES film, PEI film, PSF film, PPS film, PAR film, aramid film, polyimide film, and LCP film. However, it is preferable to use a material having a linear thermal expansion coefficient close to that of the resin material of the wiring resin substrate 28. The other points of the heat resistant adhesive tape 20 are the same as those in the above-described embodiment.

次いで、開口部２８ｃに半導体チップ１５を配置する搭載工程を行う。半導体チップ１５の配置は、耐熱性粘着テープ２０の粘着剤層に直接貼り付けたり、銀ペーストを用いた接着等により行うことができる。   Next, a mounting process for disposing the semiconductor chip 15 in the opening 28c is performed. The semiconductor chip 15 can be arranged by directly attaching it to the pressure-sensitive adhesive layer of the heat-resistant pressure-sensitive adhesive tape 20, or by bonding using a silver paste.

次いで、配線樹脂基板２８の端子部２８ａと半導体チップ１５上の電極パッド１５ａとをボンディングワイヤ１６で電気的に接続する結線工程を行う。この結線工程と、以降の封止工程、切断工程も前述の実施形態と同様である。   Next, a connection process is performed in which the terminal portions 28 a of the wiring resin substrate 28 and the electrode pads 15 a on the semiconductor chip 15 are electrically connected by the bonding wires 16. This connection process and the subsequent sealing process and cutting process are also the same as in the above-described embodiment.

但し、前述の実施形態では、複数の半導体チップ１５を同じキャビティ内で一括封止する例を示したが（図４（ｄ３）に相当する）、図４（ｄ１）に示すように液状の封止樹脂１７ａを用いて、ポッティング後に硬化させてもよい。また、図４（ｄ２）に示すように、１つの半導体チップ１５のみをキャビティ内で個別封止してもよい。これらの封止形態は、リードフレームを用いた半導体装置の製造方法にも適用できる。   However, in the above-described embodiment, an example in which a plurality of semiconductor chips 15 are collectively sealed in the same cavity has been shown (corresponding to FIG. 4 (d3)), but as shown in FIG. You may make it harden | cure after potting using the stop resin 17a. Further, as shown in FIG. 4 (d2), only one semiconductor chip 15 may be individually sealed in the cavity. These sealing forms can also be applied to a method for manufacturing a semiconductor device using a lead frame.

液状封止樹脂を用いる場合、樹脂硬化温度が低い（例えば１００〜１２０℃）ために、耐熱性粘着テープの基材層として、ポリイミドフィルムやアラミドフィルム以外の耐熱性のやや低い高分子フィルム，例えばＰＥＴフィルム、ＰＥＮフィルム、ＰＥＳフィルム、ＰＥＩフィルム、ＰＳＦフィルム、ＰＥＥＫフィルム、ＰＰＳフィルム、ＰＡＲフィルム、ＬＣＰフィルムを用いることができる。   When using a liquid sealing resin, since the resin curing temperature is low (for example, 100 to 120 ° C.), as a base material layer of a heat resistant adhesive tape, a polymer film having a slightly low heat resistance other than a polyimide film or an aramid film, for example, A PET film, a PEN film, a PES film, a PEI film, a PSF film, a PEEK film, a PPS film, a PAR film, and an LCP film can be used.

以下、本発明の構成と効果を具体的に示す実施例等について説明する。   Examples and the like specifically showing the configuration and effects of the present invention will be described below.

実施例１
２５μｍ厚のポリイミドフィルム（東レデュポン製カプトン１００Ｈ、線熱膨張係数２．２×１０-5／Ｋ）を基材として、シリコーン系粘着剤（東レダウコーニング製ＳＤ−４５８７Ｌ、貯蔵弾性率１．１×１０4 Ｎ／ｃｍ2 ）を用いた厚さ５μｍの粘着剤層を設けた耐熱性粘着テープを作成した。なお、このテープの粘着力は２００℃加熱後１．０Ｎ／１９ｍｍ幅程度であった。この耐熱性粘着テープを、端子部に銀めっきが施された一辺１６ＰｉｎタイプのＱＦＮが４個×４個に配列された銅製のリードフレームのアウターパット側に貼り合わせた。このリードフレームのダイパッド部分に半導体チップをエポキシフェノール系の銀ぺーストを用いて接着し、１８０℃にて１時間ほどキュアすることで固定した。 Example 1
25 μm thick polyimide film (Toray DuPont Kapton 100H, linear thermal expansion coefficient 2.2 × 10 −5 / K) as a base material, silicone-based adhesive (Toray Dow Corning SD-4587L, storage modulus 1.1 A heat-resistant pressure-sensitive adhesive tape provided with a pressure-sensitive adhesive layer having a thickness of 5 μm using × 10 4 N / cm 2 ) was prepared. The adhesive strength of this tape was about 1.0 N / 19 mm width after heating at 200 ° C. This heat-resistant adhesive tape was bonded to the outer pad side of a copper lead frame in which 4 × 4 16-pin side QFNs with silver plating on the terminal portions were arranged. The semiconductor chip was bonded to the die pad portion of the lead frame using an epoxy phenol-based silver paste and fixed by curing at 180 ° C. for about 1 hour.

つぎに、リードフレームは耐熱性粘着テープ側から真空吸引する形で２００℃に加熱したヒートブロックに固定し、さらにリードフレームの周辺部分をウインドクランパーにて押さえて固定した。これらを、６０ＫＨｚワイヤボンダー（日本アビオニクス製）を用いてφ２５μｍの金線（田中貴金属製ＧＬＤ−２５）にて下記の条件でワイヤボンディングを行った。なお、すべてのボンディングを完了するのに約１時間を要した。   Next, the lead frame was fixed to a heat block heated to 200 ° C. by vacuum suction from the heat resistant adhesive tape side, and further, the periphery of the lead frame was fixed by pressing with a wind clamper. These were wire-bonded using a 60 KHz wire bonder (manufactured by Nippon Avionics) with a φ25 μm gold wire (Tanaka Kikinzoku GLD-25) under the following conditions. It took about 1 hour to complete all bonding.

ファーストボンディング加圧：３０ｇ
ファーストボンディング超音波強度：２５ｍＷ
ファーストボンディング印加時間：１００ｍｓｅｃ
セカンドボンディング加圧：２００ｇ
セカンドボンディング超音波強度：５０ｍＷ
セカンドボンディング印加時間：５０ｍｓｅｃ
さらにエポキシ系封止樹脂（日東電工製ＨＣ−３００）により、これらをモールドマシン（ＴＯＷＡ製Ｍｏｄｅｌ−Ｙ−ｓｅｒｉｓｅ）を用いて、１７５℃で、プレヒート４０秒、インジェクション時間１１．５秒、キュア時間１２０秒にてモールドした後、耐熱性テープを剥離した。なお、さらに１７５℃にて３時間ほどポストモールドキュアを行って樹脂を十分に硬化させた後、ダイサーによって切断して、個々のＱＦＮタイプ半導体装置を得た。 First bonding pressure: 30g
First bonding ultrasonic intensity: 25mW
First bonding application time: 100 msec
Second bonding pressure: 200g
Second bonding ultrasonic intensity: 50mW
Second bonding application time: 50 msec
Furthermore, using an epoxy-based sealing resin (HC-300 manufactured by Nitto Denko), using a mold machine (Model-Y-series manufactured by TOWA), preheating 40 seconds, injection time 11.5 seconds, and curing time at 175 ° C. After molding in 120 seconds, the heat-resistant tape was peeled off. Further, after post-curing at 175 ° C. for about 3 hours to sufficiently cure the resin, it was cut with a dicer to obtain individual QFN type semiconductor devices.

このようにして得られたＱＦＮは、樹脂のはみ出しもなく、またワイヤボンディングなどの各工程も阻害なく実施することができた。   The QFN thus obtained did not protrude from the resin, and each process such as wire bonding could be carried out without hindrance.

比較例１
テープの基材層に高密度ポリエチレンフィルム（２５μｍ；線熱膨張係数１５×１０-5／Ｋ）を用いた他は、実施例１と同様に検討を行った。しかしながら、半導体チップを搭載する際のキュア加熱をおこなった時点で、テープに激しいしわと部分的な剥離が生じ、モールド時には樹脂のはみ出しをまったく抑えることができなかった。 Comparative Example 1
The examination was performed in the same manner as in Example 1 except that a high-density polyethylene film (25 μm; linear thermal expansion coefficient 15 × 10 −5 / K) was used for the base material layer of the tape. However, at the time of curing heating when mounting the semiconductor chip, severe wrinkles and partial peeling occurred on the tape, and it was not possible to suppress the protrusion of the resin at the time of molding.

比較例２
テープの粘着剤層の厚さを５０μｍにした他は、実施例１と同様に検討を行った。なお、このテープの粘着力は２００℃加熱後５．５Ｎ／１９ｍｍ幅程度であった。その結果、ワイヤボンディングを実施したが、テープのクッション性によってセカンドボンディングのほとんどが十分に結線されておらず、ボンディング不良が多発していた。また、さらに封止工程を行った後で、テープを剥がそうとした際、その応力でリードフレームが変形し、一部の封止樹脂に剥離を生じてしまった。 Comparative Example 2
The examination was performed in the same manner as in Example 1 except that the thickness of the adhesive layer of the tape was 50 μm. The adhesive strength of this tape was about 5.5 N / 19 mm width after heating at 200 ° C. As a result, although wire bonding was carried out, most of the second bonding was not sufficiently connected due to the cushioning property of the tape, resulting in frequent bonding failures. Further, when the tape was to be peeled off after further sealing process, the lead frame was deformed by the stress, and part of the sealing resin was peeled off.

比較例３
粘着剤層（厚み３０μｍ）として、２００℃における貯蔵弾性率が５×１０2 Ｎ／ｃｍ2 程度のゴム系粘着剤を使用したほかは、実施例１と同様の検討を行った。しかしながら、ワイヤボンディングを実施したところ、テープのクッション性によってほとんどが結線されておらず、ボンディング不良が多発していた。 Comparative Example 3
As the pressure-sensitive adhesive layer (thickness 30 μm), the same examination as in Example 1 was performed except that a rubber-based pressure-sensitive adhesive having a storage elastic modulus at 200 ° C. of about 5 × 10 2 N / cm 2 was used. However, when wire bonding was performed, most of the wires were not connected due to the cushioning property of the tape, resulting in frequent bonding failures.

実施例２
耐熱性粘着テープとして、シリコーン系粘着材（東レダウコーニング製ＳＤ−４５８７Ｌ、貯蔵弾性率１．１×１０4 Ｎ／ｃｍ2 ）を用いた厚さ５μｍの粘着層を設けたテープを作成した。基材は２５μｍ厚さのポリエーテルイミド（ＰＥＩ）フィルム（住友ベークライト（株）製、商品名ＦＳ−１４００、線熱膨張係数５．６×１０-5 ／Ｋ）を用いた。なお、この粘着テープの粘着力は２００℃加熱後１．０Ｎ／１９ｍｍ幅程度であった。 Example 2
As a heat-resistant adhesive tape, a tape provided with an adhesive layer having a thickness of 5 μm using a silicone-based adhesive material (SD-4587L manufactured by Toray Dow Corning, storage elastic modulus 1.1 × 10 4 N / cm 2 ) was prepared. As the substrate, a polyetherimide (PEI) film (manufactured by Sumitomo Bakelite Co., Ltd., trade name FS-1400, linear thermal expansion coefficient 5.6 × 10 −5 / K) having a thickness of 25 μm was used. The adhesive strength of this adhesive tape was about 1.0 N / 19 mm width after heating at 200 ° C.

貼着工程として、まず半導体チップが配置されるための開口部が設けられた配線樹脂基板（ガラスエポキシ基板、ＦＲ−４）に、本粘着テープを貼り合せた。次に露出した粘着テープの粘着層面に半導体チップを貼り合せ、回路基板と半導体チップをボンディングワイヤーで結線した（条件は実施例１と同じ）。その後、液状封止樹脂材料（エポキシ樹脂：日本エイブルスティック株式会社製のＡｍｉｃｏｎ Ｊ９０５−３）をポッティングし、１２０℃で６０分間、大気オーブン炉内で保持して硬化させた。硬化後、本粘着テープを剥離し、後工程（例えば、はんだめっき，はんだボール搭載）に供した。   As an attaching step, first, the adhesive tape was attached to a wiring resin substrate (glass epoxy substrate, FR-4) provided with an opening for placing a semiconductor chip. Next, a semiconductor chip was bonded to the exposed adhesive layer surface of the adhesive tape, and the circuit board and the semiconductor chip were connected with a bonding wire (conditions are the same as in Example 1). Thereafter, a liquid encapsulating resin material (epoxy resin: Amicon J905-3 manufactured by Nippon Able Stick Co., Ltd.) was potted, and held and cured in an atmospheric oven furnace at 120 ° C. for 60 minutes. After curing, the pressure-sensitive adhesive tape was peeled off and subjected to a subsequent process (for example, solder plating, solder ball mounting).

このようにして得られた片面樹脂封止半導体装置は、問題となる樹脂のはみ出しも無く、またワイヤーボンディングなどの各工程も問題なく、良好な特性を示した。上記のように、硬化温度の低い液状封止樹脂材料を選択することによって、ポリエーテルイミド（ＰＥＩ）フィルム以外の耐熱性高分子フィルムを使用することができる。   The single-sided resin-encapsulated semiconductor device thus obtained did not have a problem of protruding resin, and had no problems in each process such as wire bonding, and exhibited good characteristics. As described above, a heat-resistant polymer film other than a polyetherimide (PEI) film can be used by selecting a liquid sealing resin material having a low curing temperature.

実施例３
ポリイミドフィルム以外の基材として、２５μｍ厚さのアラミドフィルム（帝人株式会社製，商品名テクノーラ：線熱膨張係数２．１×１０-5 ／Ｋ）を基材として、シリコーン系粘着材（東レダウコーニング製ＳＤ−４５８７Ｌ、貯蔵弾性率１．１×１０4 Ｎ／ｃｍ2 ）を用いた厚さ５μｍの粘着層を設けた耐熱性粘着テープを作成した。なお、この粘着テープの粘着力は２００℃加熱後１．０Ｎ／１９ｍｍ幅程度であった。 Example 3
As a base material other than the polyimide film, a 25 μm-thick aramid film (manufactured by Teijin Ltd., trade name Technora: linear thermal expansion coefficient 2.1 × 10 −5 / K) is used as a base material, and a silicone-based adhesive (Toray Dow) A heat resistant adhesive tape provided with an adhesive layer having a thickness of 5 μm using Corning SD-4587L, storage elastic modulus 1.1 × 10 4 N / cm 2 ) was prepared. The adhesive strength of this adhesive tape was about 1.0 N / 19 mm width after heating at 200 ° C.

貼着工程として、まず半導体チップが配置されるための開口部が設けられた配線樹脂基板（ガラスエポキシ基板、ＦＲ−４）に、本粘着テ−プを貼り合せた。次に露出した粘着テープの粘着層面に半導体チップをエポキシ系の銀ペースト（樹脂成分：エポキシ樹脂、日本エイブルスティック（株）製のＡｍｉｃｏｎ Ｃ９９０Ｊ）を用いて接着し、１５０℃にて１時間、大気オーブン炉でキュアすることで固定した。その後、回路基板を粘着テープ側から真空吸引する形で、２００℃に加熱したヒートブロック上に固定した。これらを、（日本アビオニクス製）の６０ＫＨｚワイヤボンダーを用いてφ２５μｍの金線（田中貴金属製ＧＬＤ−２５）にてワイヤボンディング（条件は実施例１と同じ）を行ない、回路基板と半導体チップを結線した。   As the attaching step, first, the adhesive tape was attached to a wiring resin substrate (glass epoxy substrate, FR-4) provided with an opening for placing a semiconductor chip. Next, the semiconductor chip was adhered to the exposed adhesive layer surface of the adhesive tape using an epoxy-based silver paste (resin component: epoxy resin, Amicon C990J manufactured by Nippon Able Stick Co., Ltd.), and the atmosphere at 150 ° C. for 1 hour. It was fixed by curing in an oven furnace. Thereafter, the circuit board was fixed on a heat block heated to 200 ° C. by vacuum suction from the adhesive tape side. These are wire-bonded (with the same conditions as in Example 1) using a φ25 μm gold wire (GLD-25 made by Tanaka Kikinzoku) using a 60 KHz wire bonder (manufactured by Nippon Avionics) to connect the circuit board and the semiconductor chip. did.

さらにエポキシ系モールド樹脂（日東電工製ＨＣ−３００）により、これらをモールドマシン（ＴＯＷＡ製Ｍｏｄｅｌ−Ｙ−シリーズ）を用いて、１７５℃でプレヒート40秒、インジェクション時間１１．５秒、キュア時間１２０秒にてモールドした後、本粘着テープを剥離した。その後１７５℃にて３時間ほどポストモールドキュアを行って樹脂を十分に硬化させた後、ダイサーによって切断して、半導体装置を得た。   Furthermore, with epoxy mold resin (HC-300 manufactured by Nitto Denko), these were preheated at 175 ° C. for 40 seconds, injection time 11.5 seconds, and cure time 120 seconds using a mold machine (Model WA-TOY manufactured by TOWA). Then, the adhesive tape was peeled off. Thereafter, post-mold curing was performed at 175 ° C. for about 3 hours to sufficiently cure the resin, and then cut with a dicer to obtain a semiconductor device.

このようにして得られた片面樹脂封止半導体装置は、問題となる樹脂のはみ出しも無く、またワイヤーボンディングなどの各工程も問題なく、良好な特性を示した。実施例３では配線樹脂基板を用いたが、金属リードフレームでも同じ効果を得ることができる。   The single-sided resin-encapsulated semiconductor device thus obtained did not have a problem of protruding resin, and had no problems in each process such as wire bonding, and exhibited good characteristics. Although the wiring resin substrate is used in the third embodiment, the same effect can be obtained with a metal lead frame.

１０ リードフレーム
１１ａ 開口
１１ｂ 端子部
１１ｃ ダイパッド
１５ 半導体チップ
１５ａ 電極パッド
１６ ボンディングワイヤ
１７ 封止樹脂
２０ 粘着テープ
２１ 封止された構造物
２１ａ 半導体装置
２８ 配線樹脂基板
２８ａ 端子部
２８ｂ アウターパッド
２８ｃ 開口部 DESCRIPTION OF SYMBOLS 10 Lead frame 11a Opening 11b Terminal part 11c Die pad 15 Semiconductor chip 15a Electrode pad 16 Bonding wire 17 Sealing resin 20 Adhesive tape 21 Sealed structure 21a Semiconductor device 28 Wiring resin substrate 28a Terminal part 28b Outer pad 28c Opening part

Claims (4)

アウターパッド側に耐熱性粘着テープを貼り合わせた金属製のリードフレームのダイパッド上に半導体チップをボンディングする搭載工程と、
前記リードフレームの端子部先端と前記半導体チップ上の電極パッドとをボンディングワイヤで電気的に接続する結線工程と、
封止樹脂により半導体チップ側を片面封止する封止工程と、
封止された構造物を個別の半導体装置に切断する切断工程と
を、少なくとも含み、
前記耐熱性粘着テープは、５０〜２５０℃における線熱膨張係数１.０×１０ -5 〜３.０×１０ -5 ／Ｋの基材層と、厚さ１０μｍ以下の粘着剤層とから構成されており、
前記耐熱性粘着テープは、前記リードフレームに形成されている開口を少なくとも覆うように前記リードフレームのアウターパッド側に貼り合わせられており、
前記封止工程は、所定時間の加熱の後、前記耐熱性粘着テープを剥離し、その後さらに加熱する工程であることを特徴とする半導体装置の製造方法。 A mounting step of bonding a semiconductor chip on a die pad of a metal lead frame in which a heat-resistant adhesive tape is bonded to the outer pad side;
A wire connection step for electrically connecting a terminal portion tip of the lead frame and an electrode pad on the semiconductor chip with a bonding wire;
A sealing step of sealing one side of the semiconductor chip side with a sealing resin;
A cutting step of cutting the sealed structure into individual semiconductor devices,
The heat-resistant adhesive tape is composed of a base material layer having a linear thermal expansion coefficient of 1.0 × 10 −5 to 3.0 × 10 −5 / K at 50 to 250 ° C., and an adhesive layer having a thickness of 10 μm or less. Has been
The heat resistant adhesive tape is bonded to the outer pad side of the lead frame so as to cover at least the opening formed in the lead frame,
The method of manufacturing a semiconductor device, wherein the sealing step is a step of peeling the heat-resistant adhesive tape after heating for a predetermined time, and further heating. 前記粘着剤層の２００℃における貯蔵弾性率が５．０×１０３Ｎ／ｃｍ２以上であることを特徴とする請求項１に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 1, a storage elastic modulus at 200 ° C. before Symbol pressure-sensitive adhesive layer, characterized in that it is 5.0 × 10 3 N / cm 2 or more. 半導体チップを配置する開口部とその外側の表面に配置される端子部とその端子部の裏側面に配置されるアウターパッドとを有する配線樹脂基板の前記アウターパッド側に耐熱性粘着テープを貼り合わせる貼着工程と、
前記開口部に半導体チップを配置する搭載工程と、
前記配線樹脂基板の端子部と前記半導体チップ上の電極パッドとをボンディングワイヤで電気的に接続する結線工程と、
封止樹脂により半導体チップ側を片面封止する封止工程と、
封止された構造物を個別の半導体装置に切断する切断工程と
を、少なくとも含み、
前記耐熱性粘着テープは、５０〜２５０℃における線熱膨張係数０．８×１０ −５ 〜５．６×１０ −５ ／Ｋの基材層と、厚さ５０μｍ以下の粘着剤層とから構成されており、
前記耐熱性粘着テープは、前記配線樹脂基板に形成されている開口を少なくとも覆うように前記配線樹脂基板のアウターパッド側に貼り合わせられており、
前記封止工程は、所定時間の加熱の後、前記耐熱性粘着テープを剥離し、その後さらに加熱する工程であることを特徴とする半導体装置の製造方法。 A heat-resistant adhesive tape is bonded to the outer pad side of the wiring resin substrate having an opening for arranging the semiconductor chip, a terminal portion arranged on the outer surface thereof, and an outer pad arranged on the back side surface of the terminal portion. A sticking process;
A mounting step of disposing a semiconductor chip in the opening;
A wiring step of electrically connecting the terminal portion of the wiring resin substrate and the electrode pad on the semiconductor chip with a bonding wire;
A sealing step of sealing one side of the semiconductor chip side with a sealing resin;
A cutting step of cutting the sealed structure into individual semiconductor devices,
The heat-resistant adhesive tape is composed of a base material layer having a linear thermal expansion coefficient of 0.8 × 10 −5 to 5.6 × 10 −5 / K at 50 to 250 ° C. and an adhesive layer having a thickness of 50 μm or less. Has been
The heat-resistant adhesive tape is bonded to the outer pad side of the wiring resin substrate so as to cover at least the opening formed in the wiring resin substrate,
The method of manufacturing a semiconductor device, wherein the sealing step is a step of peeling the heat-resistant adhesive tape after heating for a predetermined time, and further heating. 前記粘着剤層の２００℃における貯蔵弾性率が５．０×１０３Ｎ／ｃｍ２以上であることを特徴とする請求項３に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 3, the storage elastic modulus at 200 ° C. before Symbol pressure-sensitive adhesive layer, characterized in that it is 5.0 × 10 3 N / cm 2 or more.
JP2009164868A 2000-10-02 2009-07-13 Manufacturing method of semiconductor device Expired - Lifetime JP5275159B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009164868A JP5275159B2 (en) 2000-10-02 2009-07-13 Manufacturing method of semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000302227 2000-10-02
JP2000302227 2000-10-02
JP2009164868A JP5275159B2 (en) 2000-10-02 2009-07-13 Manufacturing method of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2001020395A Division JP4357754B2 (en) 2000-10-02 2001-01-29 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2009239308A JP2009239308A (en) 2009-10-15
JP5275159B2 true JP5275159B2 (en) 2013-08-28

Family

ID=41252812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009164868A Expired - Lifetime JP5275159B2 (en) 2000-10-02 2009-07-13 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP5275159B2 (en)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130778A (en) * 1993-11-05 1995-05-19 Toshiba Corp Apparatus and method for manufacture of semiconductor device
JPH08157599A (en) * 1994-10-07 1996-06-18 Unitika Ltd Polyamic acid solution and polyimide film or polyimide-coated article produced therefrom
JPH098179A (en) * 1995-06-15 1997-01-10 Toshiba Corp Resin-sealing semiconductor device, its manufacture, resin sheet for semiconductor sealing and resin composition of semiconductor sealing
JPH09246427A (en) * 1996-03-12 1997-09-19 Dainippon Printing Co Ltd Surface packaged semiconductor device and its manufacturing method
JP4127884B2 (en) * 1997-11-28 2008-07-30 株式会社ルネサステクノロジ Semiconductor device
JP3961672B2 (en) * 1998-06-12 2007-08-22 リンテック株式会社 Manufacturing method of resin-encapsulated chip body
JP3478139B2 (en) * 1998-09-02 2003-12-15 松下電器産業株式会社 Lead frame manufacturing method
JP4357754B2 (en) * 2000-10-02 2009-11-04 日東電工株式会社 Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP2009239308A (en) 2009-10-15

Similar Documents

Publication Publication Date Title
JP5551568B2 (en) Resin-sealing adhesive tape and method for manufacturing resin-sealed semiconductor device using the same
JP3849978B2 (en) Semiconductor device manufacturing method and heat-resistant adhesive tape used therefor
JP4397653B2 (en) Adhesive sheet for semiconductor device manufacturing
KR20050076771A (en) Process for producing semiconductor devices, and heat resistant adhesive tape used in this process
JP4125668B2 (en) Manufacturing method of semiconductor device
JP4357754B2 (en) Manufacturing method of semiconductor device
JP5548077B2 (en) Resin-sealing adhesive tape and method for manufacturing resin-sealed semiconductor device
JP5366781B2 (en) Resin-sealing heat-resistant adhesive tape and method for producing resin-sealed semiconductor device using the same
JP2006318999A (en) Adhesive film for manufacturing semiconductor device
JP3934041B2 (en) Semiconductor device manufacturing method and heat-resistant adhesive tape used therefor
JP5275159B2 (en) Manufacturing method of semiconductor device
JP2002226797A (en) Heat resistant adhesive tape and method for manufacturing semiconductor device
JP4507380B2 (en) Manufacturing method of semiconductor device and lead frame laminate used therefor
JP5160575B2 (en) Semiconductor device manufacturing method and heat-resistant adhesive tape used therefor
JP3976311B2 (en) Lead frame manufacturing method
JP4526714B2 (en) Lead frame laminate and method for manufacturing semiconductor device
JP2012182392A (en) Semiconductor device manufacturing method
JP2009044010A (en) Manufacturing method of semiconductor device
JP2002226794A (en) Heat-resistant pressure-sensitive adhesive tape and method of manufacturing semiconductor device
JP2002226795A (en) Heat-resistant pressure-sensitive adhesive tape and method of manufacturing semiconductor device
JP2002110884A (en) Lead frame laminate
JP2003179092A (en) Method of manufacturing semiconductor device and wire bonding apparatus used in the same
JP2002222822A (en) Method for manufacturing semiconductor device
KR101923736B1 (en) Pressure-sensitive adhesive tape for resin encapsulation and method for producing resin encapsulation type semiconductor device
JP2001015667A (en) Lead frame, resin sealed semiconductor device using the same, and its manufacture

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090714

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120420

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120604

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120622

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130514

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130515

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5275159

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term