JP4140963B2 - Manufacturing method of semiconductor device, adhesive tape used in the method, and semiconductor device manufactured by the method - Google Patents

Manufacturing method of semiconductor device, adhesive tape used in the method, and semiconductor device manufactured by the method Download PDF

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JP4140963B2
JP4140963B2 JP2003374364A JP2003374364A JP4140963B2 JP 4140963 B2 JP4140963 B2 JP 4140963B2 JP 2003374364 A JP2003374364 A JP 2003374364A JP 2003374364 A JP2003374364 A JP 2003374364A JP 4140963 B2 JP4140963 B2 JP 4140963B2
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adhesive
layer
adhesive tape
semiconductor device
resin
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JP2005142207A (en
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知加雄 池永
洋 島崎
和人 細川
卓司 桶結
桂介 吉川
和弘 池村
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Dai Nippon Printing Co Ltd
Nitto Denko Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

本発明は、表面実装型の半導体装置の技術分野に属し、詳しくは、リードレス構造をした表面実装型の半導体装置の製造方法に関し、またその方法に用いられる半導体装置製造用の接着テープに関し、さらにはその方法により得られる半導体装置に関する。   The present invention belongs to the technical field of surface-mount semiconductor devices, and in particular, relates to a method for manufacturing a surface-mount semiconductor device having a leadless structure, and to an adhesive tape for manufacturing a semiconductor device used in the method, Further, the present invention relates to a semiconductor device obtained by the method.

一般に、半導体装置はその構成部材の一つに金属製のリードフレームを用いているが、多ピン化を実現するためには、リードフレームにおけるリードのピッチを微細化することが要求される。ところが、これに伴ってリード自体の幅を小さくすると、リードの強度が下がり、リードの曲がり等による短絡現象が生じてしまう。したがって、リードのピッチを確保するためにパッケージを大型化することが余儀なくされていた。このように、リードフレームを用いた半導体装置はパッケージサイズが大きくかつ厚くなる。そのため、リードフレームの影響のない、いわゆるリードレス構造をした表面実装型の半導体装置が提案されている(例えば、特許文献1、特許文献2参照。)。
特開平9−252014号公報 特開2001−210743号公報
In general, a semiconductor device uses a metal lead frame as one of its constituent members. However, in order to realize a large number of pins, it is required to reduce the lead pitch in the lead frame. However, if the width of the lead itself is reduced accordingly, the strength of the lead is lowered, and a short circuit phenomenon due to bending of the lead occurs. Therefore, the package has to be enlarged in order to ensure the lead pitch. Thus, a semiconductor device using a lead frame has a large package size and a large thickness. For this reason, a surface-mount type semiconductor device having a so-called leadless structure without the influence of a lead frame has been proposed (see, for example, Patent Document 1 and Patent Document 2).
Japanese Patent Laid-Open No. 9-252014 JP 2001-210743 A

特許文献1に記載された半導体装置を図7に示す。この半導体装置の製造方法は、まず、基材101にベース基板としての金属箔を貼り付け、所定部分に金属箔を残すように当該金属箔のエッチングを行った後、半導体素子102と同等の大きさを有する金属箔103a(ダイパッド)の上に接着剤104を用いて半導体素子102を固着し、さらに、ワイヤー105によって半導体素子102と金属箔103bとの電気的接続を行い、金型を用いて封止樹脂106でトランスファモールドする(図7(a))。そして最後に、成形された封止樹脂106を基材101から分離することによって半導体素子102をパッケージとして完成している(図7(b))。しかしながら、このようにベース基板に金属箔を使用すると、基材との分離は機械的に行うことになるが、金属箔は曲がりにくいためその分離の際に封止後の半導体装置に機械的な負荷を加えることになる。   The semiconductor device described in Patent Document 1 is shown in FIG. In this semiconductor device manufacturing method, first, a metal foil as a base substrate is attached to the base material 101, the metal foil is etched so as to leave the metal foil in a predetermined portion, and then the size equivalent to that of the semiconductor element 102 is obtained. The semiconductor element 102 is fixed on the metal foil 103a (die pad) having a thickness by using an adhesive 104, and the semiconductor element 102 and the metal foil 103b are electrically connected by a wire 105, and a mold is used. Transfer molding is performed with the sealing resin 106 (FIG. 7A). Finally, the molded sealing resin 106 is separated from the base material 101 to complete the semiconductor element 102 as a package (FIG. 7B). However, when the metal foil is used for the base substrate in this manner, the separation from the base material is mechanically performed. However, since the metal foil is difficult to bend, the semiconductor device after sealing is mechanically separated during the separation. It will add a load.

また、特許文献1に記載の製造方法では、金属箔のエッチング工程及び封止樹脂のモールド工程において基材と金属箔が充分密着していることが要求され、一方、モールド工程後は基材と封止樹脂、基材と金属箔は容易に分離できることが要求される。このように、基材と金属箔は、密着特性において相反する特性が要求される。すなわち、エッチングに使用する薬品に対しては耐久性が、モールド工程での高温下及び封止樹脂が金型内を流れる時に加わる圧力下においては半導体素子がずれることがないような耐久性が必要であるにもかかわらず、モールド後には基材と封止樹脂、基材と金属箔が容易に分離できることが要求される。ところが、基材として例示されている、テフロン(登録商標)材料、シリコーン材料あるいはテフロン(登録商標)コーティングした金属等ではこのような密着特性を満足することが到底できない。   Moreover, in the manufacturing method described in Patent Document 1, it is required that the base material and the metal foil are sufficiently adhered in the etching process of the metal foil and the molding process of the sealing resin. The sealing resin, the base material and the metal foil are required to be easily separated. Thus, the base material and the metal foil are required to have contradictory properties in adhesion properties. In other words, durability against chemicals used for etching is required, and durability is required so that the semiconductor element does not shift under high temperature in the molding process and pressure applied when the sealing resin flows in the mold. However, it is required that the base material and the sealing resin, and the base material and the metal foil can be easily separated after molding. However, the Teflon (registered trademark) material, the silicone material, the Teflon (registered trademark) coated metal, and the like exemplified as the base material cannot satisfy such adhesion characteristics.

特許文献2に記載された半導体装置を図8に示す。この半導体装置は次の方法により製造される。まず、基材となる金属板に枡目状の凹溝201aを形成した金属板201を得る。次いで、半導体素子202を接着剤203にて金属板201に固着し、その後に設計上必要な場所にワイヤーボンディングしてワイヤー204を形成し、封止樹脂205でトランスファーモールドする(図8(a))。次いで、金属板201の裏面側を少なくとも1/2の厚さ以上に研磨し、さらには設計に即した寸法に封止樹脂205とともに金属板201を切断して半導体装置を得る(図8(b))。しかし、この製造方法では、金属板を機械的な研磨方法あるいはエッチング等による化学的な研磨方法にて除去する必要があることから、環境上もコスト的にも、また製品に与えるダメージの点からもあまり良好な方法とはいえない。   A semiconductor device described in Patent Document 2 is shown in FIG. This semiconductor device is manufactured by the following method. First, a metal plate 201 in which a grid-like concave groove 201a is formed on a metal plate to be a base material is obtained. Next, the semiconductor element 202 is fixed to the metal plate 201 with an adhesive 203, and then wire bonding is performed at a place necessary for design to form a wire 204, and transfer molding is performed with a sealing resin 205 (FIG. 8A). ). Next, the back surface side of the metal plate 201 is polished to a thickness of at least 1/2 or more, and the metal plate 201 is cut together with the sealing resin 205 to a size according to the design to obtain a semiconductor device (FIG. 8B). )). However, in this manufacturing method, it is necessary to remove the metal plate by a mechanical polishing method or a chemical polishing method such as etching. Therefore, from the viewpoint of damage to the product in terms of environment and cost. However, it is not a very good method.

また、本発明の接着テープは、上記の製造方法に用いられる接着テープであって、金属基材層の上に第一接着剤層、樹脂基材層、第二接着剤層が順次積層された多層構造で、そのうちの第一接着剤層が加熱により接着力を失う性質を有するとともに第二接着剤層が熱硬化型接着剤からなり、100〜150℃における硬化前の弾性率が0.1MPa以下で、200℃における硬化後の弾性率が0.1MPa以上であることを特徴とする。 The adhesive tape of the present invention is an adhesive tape used in the above manufacturing method, and a first adhesive layer, a resin base layer, and a second adhesive layer are sequentially laminated on the metal base layer. a multilayer structure, together with the first adhesive layer of which is perforated the property of losing the adhesive force by heating, the second adhesive layer consists of thermosetting adhesive, elastic modulus before curing at 100 to 150 ° C. is 0 .1MPa below, the elastic modulus after curing at 200 ° C. is characterized der Rukoto least 0.1 MPa.

本発明は、このような問題点に鑑みてなされたものであり、その目的とするところは、薄型化が可能なリードレス構造で、強度的にも優れた表面実装型の半導体装置の製造方法を提供し、併せてその方法に用いられる半導体装置製造用の接着テープを提供し、さらにはその方法により得られる半導体装置を提供することにある。   The present invention has been made in view of such problems, and an object of the present invention is to provide a method for manufacturing a surface-mount type semiconductor device having a leadless structure capable of being thinned and excellent in strength. In addition, an adhesive tape for manufacturing a semiconductor device used in the method is provided, and a semiconductor device obtained by the method is provided.

上記の目的を達成するため、本発明の半導体装置の製造方法は、接着テープにおける接着面上に部分的に複数の導電部を少なくとも形成する基板作成工程、電極が形成されている少なくとも1つの半導体素子を電極が形成されていない側が基板側となるように前記基板上に固着し、複数の導電部の上側と半導体素子の上側にある電極とをワイヤーにより電気的に接続する半導体素子搭載工程、半導体素子とワイヤーと導電部とを封止樹脂で封止して接着テープ上に半導体装置を形成する樹脂封止工程、半導体装置から接着テープを分離する接着テープ除去工程、ダイサーカット又はパンチングにより個片化する切断工程からなる半導体装置の製造方法であって、
前記接着テープとして、金属基材層の上に第一接着剤層、樹脂基材層、第二接着剤層が順次積層された多層構造で、そのうちの第一接着剤層が加熱により接着力を失う性質を有する接着テープを使用し、
前記接着テープ除去工程では、所定の温度に加温することにより、接着テープにおける第一接着剤層の接着力を消失せしめて金属基材層を剥離させてから、樹脂基材層を第一接着剤層及び第二接着剤層と共に折返し剥離するようにしたことを特徴とする。
In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes a substrate forming step in which at least a plurality of conductive portions are partially formed on an adhesive surface of an adhesive tape, and at least one semiconductor in which electrodes are formed. A semiconductor element mounting step in which the element is fixed on the substrate so that the side on which no electrode is formed is the substrate side, and the upper side of the plurality of conductive portions and the electrode on the upper side of the semiconductor element are electrically connected by wires; The semiconductor element, the wire, and the conductive part are sealed with a sealing resin to form a semiconductor device on the adhesive tape, the adhesive tape is removed from the semiconductor device, the adhesive tape is removed, and the individual is cut by punching or punching. A method for manufacturing a semiconductor device comprising a cutting step for singulation,
The adhesive tape has a multilayer structure in which a first adhesive layer, a resin base layer, and a second adhesive layer are sequentially laminated on a metal base layer, and the first adhesive layer of which has an adhesive force by heating. Use adhesive tape with the property of losing,
In the adhesive tape removing step, by heating to a predetermined temperature, the adhesive strength of the first adhesive layer in the adhesive tape is lost and the metal base material layer is peeled off, and then the resin base material layer is first bonded. The adhesive layer and the second adhesive layer are folded back and peeled off.

また、本発明の接着テープは、上記の製造方法に用いられる接着テープであって、金属基材層の上に第一接着剤層、樹脂基材層、第二接着剤層が順次積層された多層構造で、そのうちの第一接着剤層が加熱により接着力を失う性質を有することを特徴とする。   The adhesive tape of the present invention is an adhesive tape used in the above manufacturing method, and a first adhesive layer, a resin base layer, and a second adhesive layer are sequentially laminated on the metal base layer. The first adhesive layer has a property of losing adhesive force by heating in a multilayer structure.

そして、上記接着テープは、第一の接着剤層が、加熱により接着力を失う性質として加熱発泡剥離機能を有する形態を採ることができる。   And the said adhesive tape can take the form which a 1st adhesive bond layer has a heating foam peeling function as a property which loses adhesive force by heating.

また、上記接着テープは、金属基材層と樹脂基材層の200℃における弾性率が共に1.0GPa以上であり、かつ第一接着剤層及び第二接着剤層の200℃における弾性率が0.1MPa以上であることが好ましい。 In the adhesive tape, both the metal base material layer and the resin base material layer have an elastic modulus at 200 ° C. of 1.0 GPa or more, and the first adhesive layer and the second adhesive layer have an elastic modulus at 200 ° C. It is preferably 0.1 MPa or more.

また、上記接着テープは、第二接着剤層の熱硬化型接着剤が、エポキシ樹脂、エポキシ硬化剤、弾性体を必須成分として含有することが好ましい。 In the adhesive tape, it is preferable that the thermosetting adhesive of the second adhesive layer contains an epoxy resin, an epoxy curing agent, and an elastic body as essential components.

また、本発明の半導体装置は、半導体素子の上側にある電極と複数の導電部の上側とがそれぞれワイヤーで電気的に接続され、半導体素子の電極が形成されていない下側と導電部のワイヤーに接続していない下側とが裏面に露出した状態で半導体素子とワイヤーと導電部とが封止樹脂で封止されてなるリードレス構造の半導体装置であって、上記の製造方法によって製造される。   Further, in the semiconductor device of the present invention, the electrode on the upper side of the semiconductor element and the upper side of the plurality of conductive portions are electrically connected by wires, respectively, and the lower side where the electrode of the semiconductor element is not formed and the wire of the conductive portion A semiconductor device having a leadless structure in which a semiconductor element, a wire, and a conductive portion are sealed with a sealing resin in a state where a lower side that is not connected to the back is exposed on the back surface, and is manufactured by the above-described manufacturing method. The

本発明の半導体装置の製造方法によれば、リードフレームを用いないリードレス構造であって、半導体素子の下には何も存在しないという徹底した薄型化を図った半導体装置を製造することができ、また、半導体素子の位置ズレがなく、低コストであり、しかも、製造工程でのダメージが少ない半導体装置を得ることができる。   According to the method for manufacturing a semiconductor device of the present invention, it is possible to manufacture a semiconductor device that has a leadless structure that does not use a lead frame and that is thoroughly thinned so that nothing exists under the semiconductor element. In addition, there can be obtained a semiconductor device in which there is no positional deviation of the semiconductor element, the cost is low, and the damage in the manufacturing process is small.

本発明の接着テープは、金属基材層の上に第一接着剤層、樹脂基材層、第二接着剤層が順次積層された多層構造で、そのうちの第一接着剤層が加熱により接着力を失う性質を有するので、半導体装置から接着テープを分離する接着テープ除去工程において、所定の温度に加温することにより、接着テープにおける第一接着剤層の接着力を消失せしめて金属基材層を剥離させてから、樹脂基材層を第一接着剤層及び第二接着剤層と共に折返し剥離することによって、端子に欠損を生じたりチップ破損や封止樹脂割れといった半導体装置へのダメージを与えたりすることなく、端子と第二接着剤、封止樹脂と第二接着剤を軽い力で容易に剥離することができる。   The adhesive tape of the present invention has a multilayer structure in which a first adhesive layer, a resin base layer, and a second adhesive layer are sequentially laminated on a metal base layer, and the first adhesive layer is bonded by heating. Since it has the property of losing its strength, the adhesive strength of the first adhesive layer in the adhesive tape disappears by heating to a predetermined temperature in the adhesive tape removing process for separating the adhesive tape from the semiconductor device, and the metal substrate After the layer is peeled off, the resin base material layer is folded back together with the first adhesive layer and the second adhesive layer to cause damage to the semiconductor device such as chipping of the terminal or chip damage or sealing resin cracking. Without giving, the terminal and the second adhesive, the sealing resin and the second adhesive can be easily peeled off with a light force.

図1〜図3は本発明に係る半導体装置の製造方法を示す工程図であり、同図により以下に製造の手順を説明する。   1 to 3 are process diagrams showing a method of manufacturing a semiconductor device according to the present invention, and the manufacturing procedure will be described below with reference to FIG.

まず、図1(a)に示すように、金属基材層51の上に第一接着剤層52、樹脂基材層53、第二接着剤層54を順次積層した多層構造の接着テープ50を準備する。この接着テープ50における第一接着剤層52は、加熱により接着力を失う性質の接着剤により形成されている。このような接着テープ50は、樹脂基材層53におけるそれぞれの面に別の接着剤を塗布して第一接着剤層52と第二接着剤層54を形成し、これに金属基材層51を貼り合わせることで作製される。そして、図1(b)に示すように、接着テープ50における第二接着剤層54上に部分的に複数の導電部20を形成して基板を作製する。なお、導電部20は図示の如く上下にそれぞれ張出部分20aを有しているが、このような導電部20を形成する基板作成工程については後述する。また、導電部20に加えてダイパッドを形成する形態も採りえる。   First, as shown in FIG. 1A, an adhesive tape 50 having a multilayer structure in which a first adhesive layer 52, a resin base layer 53, and a second adhesive layer 54 are sequentially laminated on a metal base layer 51 is formed. prepare. The first adhesive layer 52 in the adhesive tape 50 is formed of an adhesive having a property of losing adhesive force by heating. In such an adhesive tape 50, another adhesive is applied to each surface of the resin base layer 53 to form a first adhesive layer 52 and a second adhesive layer 54, and a metal base layer 51 is formed thereon. It is produced by sticking together. And as shown in FIG.1 (b), the some electroconductive part 20 is partially formed on the 2nd adhesive bond layer 54 in the adhesive tape 50, and a board | substrate is produced. In addition, although the electroconductive part 20 has the overhang | projection part 20a respectively up and down like illustration, the board | substrate preparation process which forms such an electroconductive part 20 is mentioned later. Further, a form in which a die pad is formed in addition to the conductive portion 20 can be adopted.

導電部20を形成した時点での接着テープ50、すなわち基板の平面図を模式的に示したのが図4である。半導体素子の電極数に対応した導電部20が接着テープ50上に複数個形成されているが、複数個の導電部20は全て電気的に独立している。   FIG. 4 schematically shows a plan view of the adhesive tape 50, that is, the substrate when the conductive portion 20 is formed. A plurality of conductive portions 20 corresponding to the number of electrodes of the semiconductor element are formed on the adhesive tape 50, but the plurality of conductive portions 20 are all electrically independent.

次に、図1(c)に示すように、電極11が形成されている半導体素子10を電極が形成されていない側が基板側となるように基板上の所定位置に第二接着剤層54を介して固着し、複数の導電部20と半導体素子10の電極11とをワイヤー30により電気的に接続する。なお、チップサイズが小さくて接着テープ50による固着力が不十分な場合は、銀ペースト、ダイアタッチフィルム等の市販のダイアタッチ材にて半導体素子10を接着テープ50上にしっかりと固着するようにしても構わない。この場合でもダイパッドは不要であるため、従来の半導体装置と比較して厚み100〜200μmの薄型化が可能である。また、ダイパッドを作製した場合でも、従来のパッケージに比較して50〜100μmの薄型化が可能である。   Next, as shown in FIG. 1C, the second adhesive layer 54 is formed at a predetermined position on the substrate so that the semiconductor element 10 on which the electrode 11 is formed is on the substrate side. The plurality of conductive portions 20 and the electrodes 11 of the semiconductor element 10 are electrically connected by wires 30. If the chip size is small and the adhesive force by the adhesive tape 50 is insufficient, the semiconductor element 10 is firmly fixed on the adhesive tape 50 with a commercially available die attach material such as silver paste or die attach film. It doesn't matter. Even in this case, since the die pad is unnecessary, the thickness can be reduced to 100 to 200 μm as compared with the conventional semiconductor device. Even when a die pad is manufactured, it can be reduced in thickness by 50 to 100 μm as compared with a conventional package.

次いで、図1(d)に示すように、半導体素子10とワイヤー30と導電部20とを封止樹脂40で封止して接着テープ50上に半導体装置を形成する。封止樹脂40による封止は、通常のトランスファーモールド法により金型を用いて行う。なお、モールド後には、必要に応じて封止樹脂40の後硬化加熱を行うようにする。後硬化加熱は、後述する接着テープ50の分離前であっても後であっても構わない。   Next, as shown in FIG. 1D, the semiconductor element 10, the wire 30, and the conductive portion 20 are sealed with a sealing resin 40 to form a semiconductor device on the adhesive tape 50. Sealing with the sealing resin 40 is performed using a mold by a normal transfer molding method. Note that after molding, post-curing heating of the sealing resin 40 is performed as necessary. The post-curing heating may be before or after separation of the adhesive tape 50 described later.

続いて、半導体装置から接着テープを分離する。この場合、図2に示すように、まず所定の温度に加温することにより第一接着剤層52の接着力を消失せしめ、易剥離状態にして金属基材層51を除去する。ここで、第一接着剤層52に用いる接着剤の種類によっては封止樹脂のモールド時にかかる熱で金属基材層51を分離することも可能である。その後、樹脂基材層53を第一接着剤層52及び第二接着剤層54と共に折返し剥離することにより、図3に示す半導体装置を得る。 Subsequently, the adhesive tape is separated from the semiconductor device. In this case, as shown in FIG. 2, by heating to a predetermined temperature allowed lost adhesion of the Ichise' Chakuzaiso 52, to remove the metal base layer 51 in the easy peeling state. Here, depending on the type of adhesive used for the first adhesive layer 52, the metal base layer 51 can be separated by heat applied during molding of the sealing resin. Thereafter, the resin base material layer 53 is folded and peeled together with the first adhesive layer 52 and the second adhesive layer 54 to obtain the semiconductor device shown in FIG.

この図3に示す半導体装置は、半導体素子10の上側にある複数の電極11と複数の導電部20の上部とがそれぞれワイヤー30で電気的に接続され、半導体素子10とワイヤー30と導電部20とが外部環境から保護するために封止樹脂40で封止されている。そして、半導体素子10の電極11が形成されていない下側と導電部20のワイヤー30に接続していない下側とが封止樹脂40と同一面上に位置した状態で封止樹脂40の裏面に露出している。このように、本発明の製造方法で得られる半導体装置は、半導体素子10の下面と導電部20の下面とが封止樹脂40の表面に露出する構造で、ダイパッドや半導体素子固着用の接着剤層を有しないリードレス構造である。しかも、この半導体装置では、導電部20が上下に張出部分20aを有した形状をしており、その張出部分20aが封止樹脂40の中でアンカー効果を発揮するので、導電部20と封止樹脂40との接合強度が高いものになっている。   In the semiconductor device shown in FIG. 3, the plurality of electrodes 11 on the upper side of the semiconductor element 10 and the upper parts of the plurality of conductive portions 20 are electrically connected by wires 30, respectively. Are sealed with a sealing resin 40 to protect them from the external environment. And the back surface of the sealing resin 40 in a state where the lower side where the electrode 11 of the semiconductor element 10 is not formed and the lower side which is not connected to the wire 30 of the conductive portion 20 are located on the same surface as the sealing resin 40 Is exposed. As described above, the semiconductor device obtained by the manufacturing method of the present invention has a structure in which the lower surface of the semiconductor element 10 and the lower surface of the conductive portion 20 are exposed on the surface of the sealing resin 40, and the adhesive for fixing the die pad or the semiconductor element. It is a leadless structure without a layer. In addition, in this semiconductor device, the conductive portion 20 has a shape having a protruding portion 20a in the vertical direction, and the protruding portion 20a exhibits an anchor effect in the sealing resin 40. The bonding strength with the sealing resin 40 is high.

従来の半導体装置では、ダイパッドの厚みが約100〜200μm、半導体素子固着用の接着剤層の厚みは約10〜50μmである。そのため、半導体素子の厚さ及び半導体素子上を覆う封止樹脂の厚みが同じ場合、本発明によれば、ダイパッドがない構成では110〜250μm程度の薄型化が可能となり、ダイパッドのある構成でも10〜50μm程度の薄型化が可能となる。   In the conventional semiconductor device, the thickness of the die pad is about 100 to 200 μm, and the thickness of the adhesive layer for fixing the semiconductor element is about 10 to 50 μm. Therefore, in the case where the thickness of the semiconductor element and the thickness of the sealing resin covering the semiconductor element are the same, according to the present invention, it is possible to reduce the thickness to about 110 to 250 μm in the configuration without the die pad. Thinning of about ˜50 μm is possible.

本発明の半導体装置の製造方法における基板作成工程、すなわち接着テープ50における第二接着剤層52上に部分的に導電部20を形成する手順を図5に示す。この基板作成工程を説明すると次のようである。   FIG. 5 shows a substrate forming step in the method for manufacturing a semiconductor device of the present invention, that is, a procedure for partially forming the conductive portion 20 on the second adhesive layer 52 in the adhesive tape 50. This substrate creation process will be described as follows.

まず、導電部の素材として銅又は銅合金からなる金属箔を準備する。この金属箔としては強度の観点から厚さが0.01〜0.1mmのものを使用する。そして、その金属箔の両面にドライフィルムレジストを貼り、図5(a)に示すように、フォトリソグラフィー法により導電部の形状とは逆のパターンで金属箔60の両面のドライフィルムレジスト61をそれぞれパターニングする。   First, a metal foil made of copper or a copper alloy is prepared as a material for the conductive part. As this metal foil, one having a thickness of 0.01 to 0.1 mm is used from the viewpoint of strength. Then, dry film resists are pasted on both surfaces of the metal foil, and as shown in FIG. 5A, the dry film resists 61 on both surfaces of the metal foil 60 are respectively formed in a pattern opposite to the shape of the conductive part by photolithography. Pattern.

次いで、図5(b)に示すように、ドライフィルムレジスト61をマスクとして、銅の拡散バリア層62としてのニッケルめっきと貴金属めっき層63を導電部の形状に部分めっきした後、図5(c)に示すように、ドライフィルムレジスト61を除去する。ここで、貴金属めっき層63に用いる貴金属としては少なくともAu、Ag、Pt、Pdのいずれか若しくはこれらの組合せとする。   Next, as shown in FIG. 5B, using the dry film resist 61 as a mask, the nickel plating as the copper diffusion barrier layer 62 and the noble metal plating layer 63 are partially plated in the shape of the conductive portion, and then the FIG. The dry film resist 61 is removed as shown in FIG. Here, the noble metal used for the noble metal plating layer 63 is at least one of Au, Ag, Pt, and Pd, or a combination thereof.

続いて、図5(d)に示すように、拡散バリア層62と貴金属めっき層63が形成された金属箔60を接着テープ50の接着剤層52側に貼り付け、この貼り付けた状態で、図5(e)に示すように、貴金属めっき層63をレジストとして金属箔60をエッチングし導電部20を独立させ、さらにプレス加工により接着テープ50の外形加工を行う。そして、貴金属めっき層63をレジストとして金属箔60をエッチングし導電部20を独立させる工程で、金属箔60の側面をもエッチングすることにより、金属箔60の上下に貴金属とニッケルからなる張出部分20aを設けた形状とする。   Subsequently, as shown in FIG. 5 (d), the metal foil 60 on which the diffusion barrier layer 62 and the noble metal plating layer 63 are formed is attached to the adhesive layer 52 side of the adhesive tape 50, and in this attached state, As shown in FIG. 5E, the metal foil 60 is etched using the noble metal plating layer 63 as a resist to make the conductive portion 20 independent, and the outer shape of the adhesive tape 50 is further processed by pressing. Then, in the process of etching the metal foil 60 using the noble metal plating layer 63 as a resist to make the conductive portion 20 independent, the side surfaces of the metal foil 60 are also etched, so that the overhang portions made of noble metal and nickel are formed above and below the metal foil 60. The shape is provided with 20a.

このように、図5の工程図は、上下両面に張出部分を有するタイプの導電部を形成する場合を示しているが、金属箔の機能面(上面)にのみに張出部分20を有する導電部20を形成する場合は、金属箔の機能面にのみ拡散バリア層と貴金属メッキ層を施し、メッキしていない側の面で金属箔を接着テープに貼り付け、この貼り付け状態で金属箔のエッチングを行うようにする。これにより、機能面のみに張出部分を有する導電部を独立させることができる。   As described above, the process diagram of FIG. 5 shows a case where a conductive portion of a type having protruding portions on both upper and lower surfaces is formed, but the protruding portion 20 is provided only on the functional surface (upper surface) of the metal foil. When the conductive portion 20 is formed, the diffusion barrier layer and the noble metal plating layer are applied only to the functional surface of the metal foil, and the metal foil is attached to the adhesive tape on the non-plated side, and the metal foil is attached in this attached state. Etching is performed. Thereby, the electroconductive part which has an overhang | projection part only in a functional surface can be made independent.

なお、本発明の半導体装置の製造方法は、半導体装置を複数個まとめて製造するのが実用的である。図6にその例を示す。図6(a)は、接着テープ50の平面図を模式的に示した説明図であり、接着テープ50の上面には1つの半導体素子を固着する領域とその周囲に形成された導電部を1つのブロック70として表し、そのブロック70が枡目状に多数形成されている。一方、図6(b)は1つのブロック70の拡大図であり、半導体素子固着領域71の周囲に導電部20が必要な数だけ形成されている。   Note that it is practical that the semiconductor device manufacturing method of the present invention manufactures a plurality of semiconductor devices together. An example is shown in FIG. FIG. 6A is an explanatory view schematically showing a plan view of the adhesive tape 50. On the upper surface of the adhesive tape 50, a region for fixing one semiconductor element and a conductive portion formed in the periphery of the region are shown. It is represented as one block 70, and a large number of the blocks 70 are formed in a grid shape. On the other hand, FIG. 6B is an enlarged view of one block 70, and the necessary number of conductive portions 20 are formed around the semiconductor element fixing region 71.

図6(a)において、例えば、接着テープ50の幅(W)が500mm幅であり、所定の工程を経て接着テープ50の上に複数個のブロック70が形成され、連続的にロールに巻かれた基材が作製される。このようにして得られた幅500mmの接着テープ50を、次の半導体素子搭載工程、樹脂封止工程に必要なブロック数になるように適宜切断して使用される。このように複数個の半導体素子を一括して樹脂封止する場合には、樹脂封止後に接着テープを分離してから、ダイサーカット又はパンチングで所定の寸法に切断して個片化することで半導体装置を得ることになる。   In FIG. 6A, for example, the width (W) of the adhesive tape 50 is 500 mm, and a plurality of blocks 70 are formed on the adhesive tape 50 through a predetermined process and continuously wound on a roll. A substrate is produced. The adhesive tape 50 having a width of 500 mm obtained in this manner is used after being appropriately cut so as to have the number of blocks necessary for the next semiconductor element mounting step and resin sealing step. In this way, when a plurality of semiconductor elements are encapsulated in a resin, the adhesive tape is separated after the resin is encapsulated, and then cut into a predetermined size by dicer cutting or punching. A semiconductor device is obtained.

本発明の半導体装置の製造方法に用いる接着テープは、樹脂封止工程が完了するまで半導体素子10や導電部20を確実に固着し、かつ半導体装置から分離する際には、端子にダメージを与えることなく、容易に剥離できるものが好ましい。このような条件を満たす接着テープ50は、前述のように金属基材層51の上に第一接着剤層52、樹脂基材層53、第二接着剤層54を順次積層した多層構造になっている。   The adhesive tape used in the method for manufacturing a semiconductor device according to the present invention securely fixes the semiconductor element 10 and the conductive part 20 until the resin sealing process is completed, and damages the terminals when separated from the semiconductor device. Those that can be easily peeled off are preferred. The adhesive tape 50 satisfying such conditions has a multilayer structure in which the first adhesive layer 52, the resin base layer 53, and the second adhesive layer 54 are sequentially laminated on the metal base layer 51 as described above. ing.

ワイヤーボンディング等が施される半導体素子搭載工程においては、温度は略150〜200℃程度の高温条件におかれる。そのため、接着テープ50を構成する各層にはこれに耐えうる耐熱性が求められる。かかる観点から、金属基材層51及び樹脂基材層53としては、200℃における弾性率が1.0GPa以上、好ましくは10Gpa以上のものが好適に用いられるが、通常は1.0GPa〜1000GPa程度であるのが好ましい。また、第一接着剤層52及び第二接着剤層54としては、弾性率が0.1MPa以上、好ましくは0.5MPa以上、さらに好ましくは1MPa以上のものが好適に用いられるが、通常は0.1MPa〜100MPa程度であるのが好ましい。かかる弾性率の第一接着剤層52及び第二接着剤層54は、半導体素子搭載工程等において軟化・流動を起こしにくく、より安定した結線が可能である。なお、弾性率の測定は詳しくは実施例に記載の方法による。   In the semiconductor element mounting process in which wire bonding or the like is performed, the temperature is set to a high temperature condition of about 150 to 200 ° C. Therefore, each layer constituting the adhesive tape 50 is required to have heat resistance that can withstand this. From this viewpoint, as the metal base material layer 51 and the resin base material layer 53, those having an elastic modulus at 200 ° C. of 1.0 GPa or more, preferably 10 GPa or more are preferably used, but usually about 1.0 GPa to 1000 GPa. Is preferred. Further, as the first adhesive layer 52 and the second adhesive layer 54, those having an elastic modulus of 0.1 MPa or more, preferably 0.5 MPa or more, more preferably 1 MPa or more are preferably used. It is preferably about 1 MPa to 100 MPa. The first adhesive layer 52 and the second adhesive layer 54 having such elastic modulus are less likely to soften and flow in a semiconductor element mounting process or the like, and can be connected more stably. The elastic modulus is measured in detail by the method described in the examples.

接着テープ50の金属基材層51は、搬送時の取扱い性、モールド時のソリ等を考慮すると金属箔を用いるのが好ましい。このような金属箔としては、SUS箔、Ni箔、Al箔、銅箔、銅合金箔等が挙げられるが、安価に入手可能なこと及び種類の豊富さからして銅、銅合金より選択するのが好ましい。また、このような金属基材層51となる金属箔は、第一接着剤層52との投錨性を確保するため、片面を粗化処理を施したものが好ましい。粗化処理の手法としては、従来公知のサンドブラスト等の物理的な粗化手法、或いはエッチング等の化学的な粗化手法のいずれでも可能である。この金属基材層51の厚みは12〜200μm程度、好ましくは50〜150μmである。   The metal base layer 51 of the adhesive tape 50 is preferably a metal foil in consideration of handling at the time of conveyance, warping at the time of molding, and the like. Examples of such metal foil include SUS foil, Ni foil, Al foil, copper foil, copper alloy foil, and the like, but it is selected from copper and copper alloy because of its availability at low cost and variety. Is preferred. Moreover, in order to ensure anchoring property with the first adhesive layer 52, it is preferable that the metal foil to be the metal base layer 51 is subjected to roughening treatment on one side. As a roughening treatment method, a conventionally known physical roughening method such as sandblasting or a chemical roughening method such as etching can be used. The thickness of the metal substrate layer 51 is about 12 to 200 μm, preferably 50 to 150 μm.

接着テープ50の第一接着剤層52としては、アクリル系粘着剤が好ましく、アクリル系粘着剤層の易剥離性をさらに向上させるために、加熱発泡により剥離性の機能を発現し向上させる添加剤を加えることができる。この加熱発泡剥離機能を付与しうる添加剤としては、例えば熱膨張性微粒子が挙げられる。この熱膨張性微粒子としては、ブタン、プロパン、ペンタンなどの如き低沸点の適宜のガス発泡性成分をカプセル化した熱膨張性マイクロカプセルを用いることができる。第一接着剤層52の厚みに関しては特に制限するものではないが、通常1〜50μm程度、好ましくは5〜20μmである。   As the first adhesive layer 52 of the adhesive tape 50, an acrylic pressure-sensitive adhesive is preferable. In order to further improve the easy peelability of the acrylic pressure-sensitive adhesive layer, an additive that expresses and improves a peelable function by heating foaming. Can be added. Examples of the additive capable of imparting the heating foam peeling function include thermally expandable fine particles. As the thermally expandable fine particles, thermally expandable microcapsules encapsulating appropriate gas foaming components having a low boiling point such as butane, propane and pentane can be used. Although it does not restrict | limit in particular regarding the thickness of the 1st adhesive bond layer 52, Usually, about 1-50 micrometers, Preferably it is 5-20 micrometers.

接着テープ50の樹脂基材層53は、その樹脂材料を特に限定するものではないが、耐熱性の観点から、ポリイミド、液晶ポリマー、PEEK、PEK、PES等が好適に用いられる。この樹脂基材層53の厚みは12〜100μm程度、好ましくは25〜50μmである。   Although the resin base material layer 53 of the adhesive tape 50 does not specifically limit the resin material, polyimide, liquid crystal polymer, PEEK, PEK, PES, or the like is preferably used from the viewpoint of heat resistance. The resin base material layer 53 has a thickness of about 12 to 100 μm, preferably 25 to 50 μm.

接着テープ50の第二接着剤層54は、樹脂封止工程が完了するまで半導体素子10や導電部20を確実に固着し、かつ半導体装置から分離する際には容易に剥離できるものが好ましく、この接着剤としては、エポキシ樹脂、エポキシ硬化剤、弾性体を必須成分として含有する熱硬化接着剤を用いるのが好ましい。熱硬化接着剤の場合、通常、基材の貼り合わせは、未硬化のいわゆるBステージ状態、すなわち150℃以下の比較的低温にて貼り合わせを行うことができ、かつ貼り合わせ後に硬化させることにより弾性率を向上し耐熱性を向上させることができる。この第二接着剤層54の厚みに関しては特に制限するものではないが、通常1〜50μm程度、好ましくは5〜20μmである。 The second adhesive layer 54 of the adhesive tape 50 is preferably one that securely fixes the semiconductor element 10 or the conductive part 20 until the resin sealing step is completed, and can be easily peeled when separated from the semiconductor device, as the adhesive, an epoxy resin, an epoxy curing agent, to use a thermosetting adhesive containing an elastic body as an essential component preferable. For thermosetting adhesive, usually, bonding of the base material, it is cured after the so-called B-stage of the uncured, i.e. can perform bonding at a relatively low temperature of 0.99 ° C. or less, and bonding Thus, the elastic modulus can be improved and the heat resistance can be improved. The thickness of the second adhesive layer 54 is not particularly limited, but is usually about 1 to 50 μm, preferably 5 to 20 μm.

ここで、エポキシ樹脂としては、グリシジルアミン型エポキシ樹脂、ビスフェールF型エポキシ樹脂、ビスフェールA型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビフェニル型エポキシ樹脂、ナフタレン型エポキシ樹脂、脂肪族エポキシ樹脂、脂環族エポキシ樹脂、複素環式エポキシ樹脂、スピロ環含有エポキシ樹脂、ハロゲン化エポキシ樹脂等が挙げられ、これらを単独もしくは2種以上混合して用いることができる。そして、エポキシ硬化剤としては、各種イミダゾール系化合物及びその誘導体、アミン系化合物、ジシアンジアミド、ヒドラジン化合物、フェノール樹脂等が挙げられ、これらを単独もしくは2種以上混合して用いることができる。また、弾性体としては、アクリル樹脂、アクリロニトリルブタジエン共重合体、フェノキシ樹脂、ポリアミド樹脂等が挙げられ、これらを単独もしくは2種以上混合して用いることができる。   Here, as the epoxy resin, glycidylamine type epoxy resin, bisphenol F type epoxy resin, bisphenol A type epoxy resin, phenol novolac type epoxy resin, cresol novolac type epoxy resin, biphenyl type epoxy resin, naphthalene type epoxy resin, Aliphatic epoxy resins, alicyclic epoxy resins, heterocyclic epoxy resins, spiro ring-containing epoxy resins, halogenated epoxy resins and the like can be mentioned, and these can be used alone or in combination of two or more. Examples of the epoxy curing agent include various imidazole compounds and derivatives thereof, amine compounds, dicyandiamide, hydrazine compounds, and phenol resins, and these can be used alone or in combination of two or more. Examples of the elastic body include acrylic resin, acrylonitrile butadiene copolymer, phenoxy resin, polyamide resin, and the like, and these can be used alone or in combination of two or more.

また、第二接着剤層54の金属箔に対する接着力は、0.1〜15N/20mmであることが好ましい。さらには0.3〜15N/20mmであるのが好ましい。ここで、接着力は導電部の大きさによって前記範囲内で適宜選択することができる。すなわち、導電部のサイズが大きい場合は接着力は比較的小さく、導電部のサイズが小さい場合は接着力は大きく設定することが好ましい。この接着力を有する接着テープは、適度の接着力を有し、基板作成工程〜半導体素子搭載工程においては接着剤層に固着した導電部のズレが起こりにくい。また接着テープ除去工程においては、半導体装置からの接着テープの分離性が良好であり、半導体装置へのダメージを少なくすることができる。なお、接着力の測定は詳しくは実施例に記載に方法による。   Moreover, it is preferable that the adhesive force with respect to the metal foil of the 2nd adhesive bond layer 54 is 0.1-15N / 20mm. Furthermore, it is preferable that it is 0.3-15N / 20mm. Here, the adhesive force can be appropriately selected within the above range depending on the size of the conductive portion. That is, when the size of the conductive portion is large, the adhesive force is relatively small, and when the size of the conductive portion is small, the adhesive force is preferably set large. The adhesive tape having this adhesive force has an appropriate adhesive force, and the conductive portion fixed to the adhesive layer is unlikely to shift in the substrate preparation process to the semiconductor element mounting process. In the adhesive tape removing step, the separation of the adhesive tape from the semiconductor device is good, and damage to the semiconductor device can be reduced. In addition, the measurement of adhesive force is based on the method as described in an Example in detail.

また、接着テープ50には、必要に応じて帯電防止機能を付与することができる。接着テープ50に帯電防止機能を付与するには、少なくとも一つの層に帯電防止剤、導電性フィラーを混合する方法がある。また、各層の界面や、金属基材層51の裏面に帯電防止剤を塗布する方法がある。この帯電防止機能を付与することにより、接着テープを半導体装置から分離する際に発生する静電気を抑制することができる。   The adhesive tape 50 can be provided with an antistatic function as necessary. In order to impart an antistatic function to the adhesive tape 50, there is a method of mixing an antistatic agent and a conductive filler in at least one layer. Further, there is a method of applying an antistatic agent to the interface of each layer or the back surface of the metal substrate layer 51. By providing this antistatic function, static electricity generated when the adhesive tape is separated from the semiconductor device can be suppressed.

帯電防止剤としては、帯電防止機能を有するものであれば特に制限はない。具体例としては、例えば、アクリル系両性、アクリル系カチオン、無水マレイン酸−スチレン系アニオン等の界面活性剤等が使用できる。帯電防止層用の材料としては、具体的には、ボンディップPA、ボンディップPX、ボンディップP(コニシ社製)等が挙げられる。また、導電性フィラーとしては、慣用のものを使用でき、例えば、Ni、Fe、Cr、Co、Al、Sb、Mo、Cu、Ag、Pt、Au等の金属、これらの合金又は酸化物、カーボンブラックなどのカーボンなどが例示できる。これらは単独で又は2種以上を組み合わせて使用できる。導電性フィラーは、粉体状、繊維状の何れであってもよい。その他、接着テープ中には老化防止剤、顔料、可塑剤、充填剤、粘着付与剤等の従来公知の各種添加物を添加することができる。   The antistatic agent is not particularly limited as long as it has an antistatic function. Specific examples include surfactants such as acrylic amphoteric, acrylic cation, maleic anhydride-styrene anion, and the like. Specific examples of the material for the antistatic layer include Bondip PA, Bondip PX, Bondip P (manufactured by Konishi Co., Ltd.), and the like. Moreover, as a conductive filler, a conventional thing can be used, for example, metals, such as Ni, Fe, Cr, Co, Al, Sb, Mo, Cu, Ag, Pt, Au, these alloys or oxides, carbon Examples thereof include carbon such as black. These can be used alone or in combination of two or more. The conductive filler may be powdery or fibrous. In addition, various conventionally known additives such as anti-aging agents, pigments, plasticizers, fillers and tackifiers can be added to the adhesive tape.

〔接着テープの作製〕
先ず、ビスフェノールA型エポキシ樹脂(ジャパンエポキシレジン社製「エビコート1002」)100重量部、アクリロニトリルブタジエン共重合体(日本ゼオン社製「ニッポール1072J」)35重量部、フェノール樹脂(荒川化学社製「P−180」)4重量部、イミダゾール(四国ファイン社製「C11Z」)2重量部を、メチルエチルケトン350重量部に溶解し、接着剤溶液を得た。これを厚さ25μmのポリイミド基材(宇部興産製「ユーピレックスS」)の片面に塗布した後、150℃で3分間乾燥させることにより、樹脂基材層の片面に厚さ15μmの第二接着剤層を形成した。この第二接着剤層の硬化前の100℃での弾性率は2.5×10-3Pa、硬化後の200℃での弾性率は4.3MPaであった。
[Production of adhesive tape]
First, 100 parts by weight of a bisphenol A type epoxy resin (“Ebicoat 1002” manufactured by Japan Epoxy Resin), 35 parts by weight of an acrylonitrile butadiene copolymer (“Nippol 1072J” manufactured by Nippon Zeon), phenol resin (“P” manufactured by Arakawa Chemical Co., Ltd.) -180 ") 4 parts by weight and 2 parts by weight of imidazole (" C11Z "manufactured by Shikoku Fine Co., Ltd.) were dissolved in 350 parts by weight of methyl ethyl ketone to obtain an adhesive solution. This is applied to one side of a 25 μm thick polyimide base material (“UPILEX S” manufactured by Ube Industries), and then dried at 150 ° C. for 3 minutes, whereby a second adhesive having a thickness of 15 μm is applied to one side of the resin base material layer. A layer was formed. The elastic modulus at 100 ° C. before curing of the second adhesive layer was 2.5 × 10 −3 Pa, and the elastic modulus at 200 ° C. after curing was 4.3 MPa.

次に、アクリル酸エチル50重量部とアクリル酸ブチル50重量部とアクリル酸2−ヒドロキシエチル1重量部の共重合体(重量平均分子量約60万)からなるベースポリマー100部、ポリウレタン系架橋剤5部、及び熱膨張性微粒子(平均粒径15μm、比重1.01)30部を添加混合したトルエン溶液を作製した。これを上記ポリイミド基材の反対面に塗布した後、150℃で3分間乾燥させることにより、樹脂基材層のもう一方の面に厚さ15μmの第一接着剤層を形成した。この第一接着剤層の硬化前の100℃での弾性率は2.5×10-3Pa、硬化後の200℃での弾性率は4.3MPaであった。これにより、樹脂基材層の両面にそれぞれ第一接着剤層と第二接着剤層を有する両面テープが作製された。 Next, 100 parts of a base polymer comprising 50 parts by weight of ethyl acrylate, 50 parts by weight of butyl acrylate and 1 part by weight of 2-hydroxyethyl acrylate (weight average molecular weight of about 600,000), polyurethane-based crosslinking agent 5 And a toluene solution in which 30 parts of thermally expandable fine particles (average particle size 15 μm, specific gravity 1.01) were added and mixed. After this was applied to the opposite surface of the polyimide substrate, it was dried at 150 ° C. for 3 minutes to form a first adhesive layer having a thickness of 15 μm on the other surface of the resin substrate layer. The elastic modulus at 100 ° C. before curing of the first adhesive layer was 2.5 × 10 −3 Pa, and the elastic modulus at 200 ° C. after curing was 4.3 MPa. Thereby, the double-sided tape which each has a 1st adhesive bond layer and a 2nd adhesive bond layer on both surfaces of the resin base material layer was produced.

次いで、温度が80℃、ラミネート圧力が0.5Mpaのラミネーターを使用し、1.0m/分のスピードにて、上記で作製した両面テープを、厚さ100μmの片面粗化銅合金箔(ジャパンエナジー社製「BHY−13B−7025」)と貼り合わせて半導体装置製造用の接着テープを得た。   Next, using a laminator with a temperature of 80 ° C. and a laminating pressure of 0.5 Mpa, the double-sided tape produced above was made into a 100 μm thick single-side roughened copper alloy foil (Japan Energy). The adhesive tape for manufacture of a semiconductor device was obtained by pasting together with “BHY-13B-7005”).

〔基板の作製〕
まず、厚さ40μmの銅箔(「Olin7025」)の両面にドライフィルムレジスト(東京応化製「オーディルAR330」)をラミネートした。そして、そのドライフィルムレジストをフォトリソグラフィー法により導電部とは逆のパターンでパターニングした。次いで、パターニングされたドライフィルムレジストをマスクとして、銅箔の両面にニッケルめっきとAuめっきを順次施した後、ドライフィルムレジストを除去した。続いて、ニッケルめっき層とAuめっき層の積層物が部分的に配された銅箔を接着テープに接着剤層を介して貼り付けた。そして、この貼り付け状態で、Auめっき層をレジストとして銅箔をエッチングし導電部を独立させた。このエッチング加工に際して、銅箔の側面をもエッチングすることによ、銅箔の上下にAuとニッケルからなる張出部分を設けた。最後に、プレス加工により接着テープの外形を加工した。
[Production of substrate]
First, a dry film resist (“Audir AR330” manufactured by Tokyo Ohka Kogyo Co., Ltd.) was laminated on both sides of a 40 μm thick copper foil (“Olin 7025”). And the dry film resist was patterned by the pattern opposite to the electroconductive part by the photolithographic method. Next, using the patterned dry film resist as a mask, nickel plating and Au plating were sequentially performed on both sides of the copper foil, and then the dry film resist was removed. Subsequently, a copper foil in which a laminate of a nickel plating layer and an Au plating layer was partially arranged was attached to an adhesive tape via an adhesive layer. Then, in this attached state, the copper foil was etched using the Au plating layer as a resist to make the conductive portion independent. During this etching process, the side surfaces of the copper foil were also etched to provide overhang portions made of Au and nickel above and below the copper foil. Finally, the outer shape of the adhesive tape was processed by pressing.

そして、図6の例(Wは500mm)で示したようなパターンで接着テープ50上に導電部20を形成した。1つのブロック70における四角形の各辺に16個の導電部20を形成し、合計で64個の導電部20を形成した。   And the electroconductive part 20 was formed on the adhesive tape 50 with the pattern as shown in the example (W is 500 mm) of FIG. Sixteen conductive portions 20 were formed on each side of the square in one block 70, and a total of 64 conductive portions 20 were formed.

〔半導体素子の搭載〕
試験用のアルミ蒸着シリコンチップ(6mm×6mm)を、前記接着テープの接着剤層面(図6(b)の71に相当)へ固着した。具体的には、175℃、0.3MPa、1秒間の条件で貼り付けた後、150℃で1時間、乾燥させて固着した。次いで、直径25μmの金ワイヤーを用いて、シリコンチップの電極と導電部との間をボンディングした。ワイヤーボンド数は1個のチップ当たり64点である。
[Installation of semiconductor elements]
An aluminum-deposited silicon chip for test (6 mm × 6 mm) was fixed to the adhesive layer surface (corresponding to 71 in FIG. 6B) of the adhesive tape. Specifically, after pasting under conditions of 175 ° C., 0.3 MPa, and 1 second, it was dried and fixed at 150 ° C. for 1 hour. Next, bonding between the electrode of the silicon chip and the conductive portion was performed using a gold wire having a diameter of 25 μm. The number of wire bonds is 64 points per chip.

前記1単位(4個×4個)の10単位について、すなわち、アルミ蒸着チップ160個に対しワイヤーボンディングを行った。ワイヤーボンディングの成功率は100%であった。続いて、トランスファー成形により封止樹脂(日東電工製「HC−100」)をモールドした。この樹脂モールド時に、接着テープにおける第一接着剤層が加熱発泡して銅箔が剥離した。したがって、残った樹脂基材層を第一接着剤層と第二接着剤層と共に、角度15度のナイフエッジ上に合わせて剥離した。このように接着テープを剥離してから、175℃で5時間、乾燥機中で後硬化を行った。その後、ダイサーにて1ブロック単位に切断し半導体装置を得た。   Wire bonding was performed on 10 units of the 1 unit (4 × 4), that is, 160 aluminum vapor-deposited chips. The success rate of wire bonding was 100%. Subsequently, a sealing resin (“HC-100” manufactured by Nitto Denko) was molded by transfer molding. During the resin molding, the first adhesive layer in the adhesive tape was heated and foamed, and the copper foil was peeled off. Therefore, the remaining resin base material layer was peeled off together with the first adhesive layer and the second adhesive layer on the knife edge at an angle of 15 degrees. After peeling off the adhesive tape in this way, post-curing was performed in a dryer at 175 ° C. for 5 hours. Then, it cut | disconnected by 1 block unit with the dicer, and the semiconductor device was obtained.

この半導体装置に対して軟X線装置(マイクロフォーカスX線テレビ透視装置:島津製作所製「SMX−100」)で内部観察を行ったところ、ワイヤー変形やチップズレ等がなく、しかも導電部の張出部分が封止樹脂の中に埋め込まれた状態になっており、導電部と封止樹脂との接合強度が高い半導体装置が得られていたことを確認した。   When this semiconductor device was internally observed with a soft X-ray device (microfocus X-ray TV fluoroscopy device: “SMX-100” manufactured by Shimadzu Corporation), there was no wire deformation or chip misalignment, and the conductive portion was extended. It was confirmed that a semiconductor device having a high bonding strength between the conductive portion and the sealing resin was obtained because the portion was embedded in the sealing resin.

なお、ワイヤーボンディング条件、トランスファーモールド条件、弾性率測定方法、接着力測定方法、ワイヤーボンド成功率については次のとおりである。   The wire bonding conditions, transfer mold conditions, elastic modulus measurement method, adhesive force measurement method, and wire bond success rate are as follows.

〔ワイヤーボンディング条件〕
装置:株式会社新川製「UTC−300BI SUPER」
超音波周波数:115KHz
超音波出力時間:15ミリ秒
超音波出力:120mW
ボンド荷重:1018N
サーチ荷重:1037N
[Wire bonding conditions]
Device: “UTC-300BI SUPER” manufactured by Shinkawa Co., Ltd.
Ultrasonic frequency: 115KHz
Ultrasonic output time: 15 milliseconds Ultrasonic output: 120 mW
Bond load: 1018N
Search load: 1037N

〔トランスファーモールド条件〕
装置:TOWA成形機
成形温度:175℃
時間:90秒
クランプ圧力:200KN
トランスファースピード:3mm/秒
トランスファー圧:5KN
[Transfer mold conditions]
Equipment: TOWA molding machine Molding temperature: 175 ° C
Time: 90 seconds Clamping pressure: 200KN
Transfer speed: 3mm / sec Transfer pressure: 5KN

〔弾性率測定方法〕
基材層、接着剤層のいずれも
評価機器:レオメトリックス社製の粘弾性スペクトルメータ「ARES」
昇温速度:5℃/min
周波数:1HZ
測定モード:引張モード
[Elastic modulus measurement method]
Both base material layer and adhesive layer Evaluation device: Viscoelasticity spectrum meter “ARES” manufactured by Rheometrics
Temperature increase rate: 5 ° C / min
Frequency: 1HZ
Measurement mode: Tensile mode

〔接着力測定方法〕
幅20mm、長さ50mmの接着テープを、120℃×0.5MPa×0.5m/minの条件で、35μm銅箔(ジャパンエナジー製「C7025」)にラミネートした後、150℃の熱風オーブンにて1時間放置後、温度23℃、湿度65%RHの雰囲気条件で、引張り速度300mm/min、180°方向に35μm銅箔を引張り、その中心値を接着強度とした。
[Adhesive strength measurement method]
After laminating an adhesive tape with a width of 20 mm and a length of 50 mm on a 35 μm copper foil (Japan Energy “C7025”) under the conditions of 120 ° C. × 0.5 MPa × 0.5 m / min, in a hot air oven at 150 ° C. After standing for 1 hour, a 35 μm copper foil was pulled in a 180 ° direction at a pulling speed of 300 mm / min under an atmospheric condition of a temperature of 23 ° C. and a humidity of 65% RH, and the center value was taken as the adhesive strength.

〔ワイヤーボンド成功率〕
ワイヤーボンドのプル強度を、株式会社レスカ製のボンディングテスタ「PTR−30」を用い、測定モード:プルテスト、測定スピード:0.5mm/secで測定した。プル強度が0.04N以上の場合を成功、0.04Nより小さい場合を失敗とした。ワイヤーボンド成功率は、これらの測定結果から成功の割合を算出した値である。
[Wire bond success rate]
The pull strength of the wire bond was measured using a bonding tester “PTR-30” manufactured by Reska Co., Ltd., with a measurement mode: pull test and a measurement speed: 0.5 mm / sec. The case where the pull strength was 0.04N or higher was regarded as success, and the case where the pull strength was smaller than 0.04N was regarded as failure. The wire bond success rate is a value obtained by calculating the success rate from these measurement results.

この実施例2では、接着テープの除去工程を変えた以外は実施例1と同様にして半導体装置を製造した。すなわち、樹脂モールド後に、半導体装置を200℃のホットプレート上で加温して接着テープの第一接着剤層を加熱発泡させ、銅箔を剥離させてから、実施例1と同様に、残った樹脂基材層を第一接着剤層と第二接着剤層と共に、角度15度のナイフエッジ上に合わせて剥離した。   In Example 2, a semiconductor device was manufactured in the same manner as Example 1 except that the adhesive tape removing process was changed. That is, after the resin molding, the semiconductor device was heated on a hot plate at 200 ° C., the first adhesive layer of the adhesive tape was heated and foamed, and the copper foil was peeled off. The resin base material layer was peeled off together with the first adhesive layer and the second adhesive layer on a knife edge at an angle of 15 degrees.

(比較例)
この比較例では、接着テープの構成とその除去工程を変えた以外は実施例1と同様にして半導体装置を製造した。すなわち、実施例1で用いた第二接着剤層用の接着剤溶液を、厚さ100μmの片面粗化銅合金箔(ジャパンエナジー社製「BHY−13B−7025」)に塗布した後、150℃で3分間乾燥させることにより、厚さ15μmの接着剤層を形成した接着シートを作製した。そして、樹脂モールド後、接着シートを室温にて角度15度のナイフエッジ上に合わせて剥離した。
(Comparative example)
In this comparative example, a semiconductor device was manufactured in the same manner as in Example 1 except that the configuration of the adhesive tape and the removal process thereof were changed. That is, after applying the adhesive solution for the second adhesive layer used in Example 1 to a 100 μm thick single-sided roughened copper alloy foil (“BHY-13B-7025” manufactured by Japan Energy Co., Ltd.), 150 ° C. Was dried for 3 minutes to produce an adhesive sheet having an adhesive layer having a thickness of 15 μm. After the resin molding, the adhesive sheet was peeled off at a room temperature on a knife edge with an angle of 15 degrees.

上記の実施例1,2と比較例で製造した半導体装置に対し、接着テープ除去工程における端子の欠損と半導体装置の破壊(チップ破損、封止樹脂割れ)の2点について評価を行った。サンプル数はそれぞれ64個とした。その結果、実施例1,2で製造した半導体装置はいずれの欠陥も発生しなかったが、比較例で製造した半導体装置は、端子欠損の見られるものが64個中5個あり、破壊の見られたものが64個中2個あった。   The semiconductor devices manufactured in Examples 1 and 2 and the comparative example were evaluated with respect to two points of terminal loss and chip breakage (chip breakage, sealing resin cracking) in the adhesive tape removing process. The number of samples was 64. As a result, the semiconductor devices manufactured in Examples 1 and 2 did not generate any defects, but the semiconductor device manufactured in Comparative Example had 5 out of 64 semiconductors with terminal defects. 2 out of 64 were found.

本発明に係る半導体装置の製造方法を示す前半の工程図である。It is process drawing of the first half which shows the manufacturing method of the semiconductor device which concerns on this invention. 図1に続く接着テープ除去工程を示す説明図である。It is explanatory drawing which shows the adhesive tape removal process following FIG. 本発明の製造方法で得られる半導体装置を示す概略構成図である。It is a schematic block diagram which shows the semiconductor device obtained with the manufacturing method of this invention. 図1の工程にて導電部を形成した時点での接着テープ(基板)の平面図を模式的に示した説明例である。It is the explanatory example which showed typically the top view of the adhesive tape (board | substrate) at the time of forming an electroconductive part in the process of FIG. 基板作成の手順を示す工程図である。It is process drawing which shows the procedure of board | substrate preparation. 本発明の半導体装置の製造方法における基板作成工程で接着テープに導電部形成した状態の上面図である。It is a top view of the state which formed the electroconductive part in the adhesive tape at the board | substrate preparation process in the manufacturing method of the semiconductor device of this invention. リードレス構造をした従来の半導体装置の一例を示す説明図である。It is explanatory drawing which shows an example of the conventional semiconductor device which has a leadless structure. リードレス構造をした従来の半導体装置の別の例を示す説明図である。It is explanatory drawing which shows another example of the conventional semiconductor device which has a leadless structure.

符号の説明Explanation of symbols

10 半導体素子
11 電極
20 導電部
20a 張出部分
30 ワイヤー
40 封止樹脂
50 接着テープ
51 金属基材層
52 第一接着剤層
53 樹脂基材層
54 第二接着剤層
60 金属箔
61 ドライフィルムレジスト
62 バリア層
63 貴金属めっき層
70 ブロック
71 半導体素子固着領域
DESCRIPTION OF SYMBOLS 10 Semiconductor element 11 Electrode 20 Conductive part 20a Overhang | projection part 30 Wire 40 Sealing resin 50 Adhesive tape 51 Metal base material layer 52 1st adhesive layer 53 Resin base material layer 54 2nd adhesive layer 60 Metal foil 61 Dry film resist 62 Barrier layer 63 Precious metal plating layer 70 Block 71 Semiconductor element fixing region

Claims (6)

接着テープにおける接着面上に部分的に複数の導電部を少なくとも形成する基板作成工程、電極が形成されている少なくとも1つの半導体素子を電極が形成されていない側が基板側となるように前記基板上に固着し、複数の導電部の上側と半導体素子の上側にある電極とをワイヤーにより電気的に接続する半導体素子搭載工程、半導体素子とワイヤーと導電部とを封止樹脂で封止して接着テープ上に半導体装置を形成する樹脂封止工程、半導体装置から接着テープを分離する接着テープ除去工程、ダイサーカット又はパンチングにより個片化する切断工程からなる半導体装置の製造方法であって、
前記接着テープとして、金属基材層の上に第一接着剤層、樹脂基材層、第二接着剤層が順次積層された多層構造で、そのうちの第一接着剤層が加熱により接着力を失う性質を有する接着テープを使用し、
前記接着テープ除去工程では、所定の温度に加温することにより、接着テープにおける第一接着剤層の接着力を消失せしめて金属基材層を剥離させてから、樹脂基材層を第一接着剤層及び第二接着剤層と共に折返し剥離するようにしたことを特徴とする半導体装置の製造方法。
A substrate forming step of forming at least a plurality of conductive portions partially on the adhesive surface of the adhesive tape; and at least one semiconductor element on which the electrode is formed on the substrate so that the side on which the electrode is not formed is the substrate side A semiconductor element mounting step in which the upper side of the plurality of conductive parts and the electrode on the upper side of the semiconductor element are electrically connected by a wire, and the semiconductor element, the wire, and the conductive part are sealed and sealed with a sealing resin A method for manufacturing a semiconductor device comprising a resin sealing step for forming a semiconductor device on a tape, an adhesive tape removing step for separating the adhesive tape from the semiconductor device, a cutting step for dicing into pieces by dicer cutting or punching,
The adhesive tape has a multilayer structure in which a first adhesive layer, a resin base layer, and a second adhesive layer are sequentially laminated on a metal base layer, and the first adhesive layer of which has an adhesive force by heating. Use adhesive tape with the property of losing,
In the adhesive tape removing step, by heating to a predetermined temperature, the adhesive strength of the first adhesive layer in the adhesive tape is lost and the metal base material layer is peeled off, and then the resin base material layer is first bonded. A method of manufacturing a semiconductor device, wherein the adhesive layer and the second adhesive layer are folded back and peeled off.
請求項1に記載の製造方法に用いられる接着テープであって、金属基材層の上に第一接着剤層、樹脂基材層、第二接着剤層が順次積層された多層構造で、そのうちの第一接着剤層が加熱により接着力を失う性質を有するとともに第二接着剤層が熱硬化型接着剤からなり、100〜150℃における硬化前の弾性率が0.1MPa以下で、200℃における硬化後の弾性率が0.1MPa以上であることを特徴とする接着テープ。 It is the adhesive tape used for the manufacturing method of Claim 1, Comprising: It is a multilayer structure by which the 1st adhesive bond layer, the resin base material layer, and the 2nd adhesive bond layer were laminated | stacked one by one on the metal base material layer, the with one adhesive layer to have the property of losing the adhesive force by heating, the second adhesive layer consists of thermosetting adhesive, an elastic modulus before curing at 100 to 150 ° C. is 0.1MPa less, adhesive tapes elastic modulus after curing, characterized in der Rukoto least 0.1MPa at 200 ° C.. 一接着剤層が、加熱により接着力を失う性質として加熱発泡剥離機能を有することを特徴とする請求項2に記載の接着テープ。 Adhesive tape according to claim 2 first Ichise' Chakuzaiso, characterized in that it has a heating foaming peeling function as a property of losing the adhesive force by heating. 金属基材層と樹脂基材層の200℃における弾性率が共に1.0GPa以上であり、かつ第一接着剤層及び第二接着剤層の200℃における弾性率が0.1MPa以上であることを特徴とする請求項2又は3に記載の接着テープ。 Both the elastic modulus at 200 ° C. of the metal substrate layer and the resin substrate layer is 1.0 GPa or more, and the elastic modulus at 200 ° C. of the first adhesive layer and the second adhesive layer is 0.1 MPa or more. The adhesive tape according to claim 2 or 3 characterized by these. 第二接着剤層の熱硬化型接着剤が、エポキシ樹脂、エポキシ硬化剤、弾性体を必須成分として含有することを特徴とする請求項2〜4のいずれかに記載の接着テープ。 The adhesive tape according to any one of claims 2 to 4, wherein the thermosetting adhesive of the second adhesive layer contains an epoxy resin, an epoxy curing agent, and an elastic body as essential components. 半導体素子の上側にある電極と複数の導電部の上側とがそれぞれワイヤーで電気的に接続され、半導体素子の電極が形成されていない下側と導電部のワイヤーに接続していない下側とが裏面に露出した状態で半導体素子とワイヤーと導電部とが封止樹脂で封止されてなるリードレス構造の半導体装置であって、請求項1に記載の製造方法によって製造されたことを特徴とする半導体装置。   The electrode on the upper side of the semiconductor element and the upper side of the plurality of conductive parts are electrically connected by wires, respectively, and the lower side where the electrode of the semiconductor element is not formed and the lower side not connected to the wire of the conductive part A semiconductor device having a leadless structure in which a semiconductor element, a wire, and a conductive portion are sealed with a sealing resin in a state of being exposed on the back surface, wherein the semiconductor device is manufactured by the manufacturing method according to claim 1. Semiconductor device.
JP2003374364A 2003-11-04 2003-11-04 Manufacturing method of semiconductor device, adhesive tape used in the method, and semiconductor device manufactured by the method Expired - Fee Related JP4140963B2 (en)

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