JP2016082018A - Semiconductor device manufacturing method, wafer with semiconductor element laminate, semiconductor element laminate and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which achieves excellent workability and excellent connectivity even when a thinned wafer is used.SOLUTION: A semiconductor device manufacturing method comprises: a resin composition layer formation process (S2) of forming a resin composition layer on a surface of a first semiconductor wafer which is fixed to a support medium and has a conductor, in which the surface is on the side opposite to the support medium; a conductor exposure process (S3) of performing exposure and developing on the resin composition layer to expose the conductor; an adhesive tape attachment process (S4) of attaching an adhesive tape on the surface of the first semiconductor wafer on the side opposite to the support medium; a support medium separation process (S5) of separating the support medium from the first semiconductor wafer; a dicing process (S6) of dicing the first semiconductor wafer to obtain semiconductor chips with resin composition; an adhesive tape separation process (S7) of separating the semiconductor chips with resin composition from the adhesive tape; and a connection process (S8) of connecting the semiconductor chips with resin composition to a connection member for connecting the semiconductor chips with resin composition.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor device, a wafer with a semiconductor element stack, a semiconductor element stack, and a semiconductor device.

  Various methods for manufacturing semiconductor devices have been proposed as electronic parts have higher performance and higher functionality. In the semiconductor mounting field, when connecting semiconductor chips and / or connecting a semiconductor chip and a support member for mounting a semiconductor chip, a substrate through conductive bumps due to stress based on a difference in thermal expansion coefficient of each connection member And a semiconductor chip may be connected abnormally. For this reason, a method is known in which conductive bumps are sealed by filling a resin (underfill material) between connecting members in order to alleviate the stress.

  Until now, in general, underfill material has been applied by a method (post-injection method) in which a liquid underfill material is injected using a capillary phenomenon after connecting semiconductor chips and the like. However, the gap between metal bumps becomes narrower as bumps become smaller and pitches with higher performance and functionality of electronic components, so liquid underfill material is injected in the post-injection method. If a low dielectric constant material is used for the substrate, it is becoming difficult to fill the underfill material for reasons such as damaging the substrate. Further, in the post-injection method, productivity may not be sufficient.

  Therefore, in order to improve productivity, a pre-feeding method, which is an underfill material injection method corresponding to the wafer process, has been studied. For example, methods described in Patent Documents 1 and 2 are known as manufacturing methods based on the first supply method. In the method described in Patent Document 1, first, a semiconductor wafer with an underfill material to which a film-like underfill material is attached is prepared. Next, after grinding the back surface of the semiconductor wafer, the semiconductor wafer is cut into chips by cutting it together with the underfill material, so that an underfill material of the same size as the semiconductor chip adheres to the semiconductor chip. A semiconductor chip with a material is produced. Next, this is mounted on a circuit board to manufacture a semiconductor device. In the method described in Patent Document 2, instead of preparing a semiconductor wafer with an underfill material using a film-like underfill material, a paste-like underfill material containing a solvent is applied onto the semiconductor wafer by spin coating. Then, the applied resin paste is B-staged (semi-cured) by heating and drying to produce a semiconductor wafer with an underfill material.

  However, since the metal bumps are covered with the underfill material in the first supply method, when the metal bumps are metal-connected to each other, the underfill material bites between the metal bumps, increasing the electric resistance value and improving the connection reliability. There is concern that it may cause defects such as decline.

  Therefore, a method has been proposed in which the underfill material covering the metal bumps is removed by exposure and development, and then the metal is connected so that the underfill material does not get caught between the metal bumps (see, for example, Patent Document 3). ).

JP 2006-049482 A JP 2009-38349 A JP 2013-160899 A

  In recent years, along with further improvement in performance of electronic devices, miniaturization of semiconductor devices and thinning of the entire semiconductor device have been progressing year by year. Therefore, for the purpose of downsizing and thinning of the semiconductor device, a thinned wafer (for example, a silicon wafer) is used for manufacturing the semiconductor device. For this reason, compared with the case where the conventional thick wafer is used, there is a concern that the thinned wafer is inferior in handleability.

  In the method described in Patent Document 3, when a thin wafer is used, the handling property may not be sufficient. In addition, when performing multi-layer lamination, workability may not be sufficiently satisfied.

  The present invention solves the problems associated with the prior art as described above, and provides a method for manufacturing a semiconductor device having excellent workability and excellent connectivity even when a thinned wafer is used. Objective.

  As a result of intensive studies to solve the above problems, the present inventors have found a production method having excellent characteristics. That is, in the method for manufacturing a semiconductor device of the present invention, a resin composition layer is formed by forming a resin composition layer on a surface opposite to the support of the first semiconductor wafer fixed on the support and having a conductor. Forming step; exposing and developing the resin composition layer to expose the conductor; and attaching an adhesive tape to the surface of the first semiconductor wafer opposite to the support. A step of separating the support from the first semiconductor wafer, a step of separating the first semiconductor wafer to obtain a semiconductor chip with a resin composition, and the resin composition An adhesive tape peeling step for peeling the semiconductor chip with an object from the adhesive tape, and a connecting step for connecting the semiconductor chip with a resin composition to a connecting member for connecting the semiconductor chip with a resin composition are provided in this order. .

  The conductor preferably includes a metal bump. Thereby, the residue of the resin composition at the time of pattern formation can be reduced. Moreover, since the opening size can be designed to be smaller, voids during pressure bonding can be reduced.

  Moreover, it is preferable that the said conductor contains the silicon penetration electrode which penetrates said 1st semiconductor wafer. As a result, it becomes easier to manufacture a chip-size package, and further, by shortening the wiring length, it becomes possible to increase the frequency of signals, and the power consumption can be greatly reduced. Moreover, you may utilize a silicon penetration electrode as a metal bump.

  The wafer with a semiconductor element laminate, the semiconductor element laminate or the semiconductor device according to the present invention is produced using the above method. In addition, you may obtain the semiconductor element laminated body by which the 1st semiconductor wafer or the semiconductor chip with a resin composition was laminated | stacked repeatedly using the said method.

  According to the present invention, it is possible to obtain a highly reliable semiconductor device that realizes a good connection state with low electrical resistance in the connection between semiconductor chips, or in the connection between a semiconductor chip and a semiconductor wafer or a semiconductor chip mounting support member. Can do. Further, even when a thinned wafer is used, the workability is good, and by using the thinned wafer, a semiconductor element stack having a high density can be obtained.

3 is a flowchart showing a method for manufacturing a semiconductor device. It is process drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment. It is process drawing which shows typically the manufacturing method of the semiconductor device which concerns on embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted. The numerical range includes the upper and lower end values. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

  As shown in FIG. 1, in the method of manufacturing a semiconductor device, first, a support fixing step (S1) is performed, then a resin composition layer forming step (S2) is performed, and then a conductor exposing step (S3). Next, the adhesive tape sticking step (S4) is performed, then the support peeling step (S5) is performed, then the individualization step (S6) is performed, and then the adhesive tape peeling step (S7) is performed, and then a connecting step (S8) is performed.

  In the support fixing step (S1), a first semiconductor wafer having a conductor is fixed on the support.

  In the resin composition layer forming step (S2), a resin composition layer is formed on the surface of the first semiconductor wafer fixed on the support on the side opposite to the support.

  In the conductor exposing step (S3), the resin composition layer is exposed and developed to expose the conductor.

  In the adhesive tape attaching step (S4), an adhesive tape is attached to the surface of the first semiconductor wafer opposite to the support.

  In the support peeling process (S5), the support is peeled from the first semiconductor wafer.

  In the singulation step (S6), the first semiconductor wafer is singulated to obtain a semiconductor chip with a resin composition.

  In the adhesive tape peeling step (S7), the semiconductor chip with a resin composition is peeled off from the adhesive tape.

  In the connecting step (S8), the semiconductor chip with a resin composition is connected to a connecting member that connects the semiconductor chip with a resin composition.

  Next, these steps will be described in detail with reference to FIGS. 2 to 8 are process diagrams schematically showing the method for manufacturing the semiconductor device according to the embodiment.

  In the support fixing step (S1), the first semiconductor wafer 1 is fixed on the support 2 via the temporary fixing layer 3 (FIG. 2).

  The first semiconductor wafer 1 has connection electrodes 4 that are conductors. The connection electrode 4 may be provided in any manner with respect to the first semiconductor wafer 1. For example, as shown in FIG. 2A, it may be an electrode 4a formed on one side of the first semiconductor wafer 1, and as shown in FIG. The electrode 4b formed on both surfaces of the first semiconductor wafer 1 may be used, and as shown in FIG. 2C, the silicon through-electrode 4c penetrating the first semiconductor wafer 1 and projecting from both surfaces of the first semiconductor wafer 1 It may be.

  The thickness of the first semiconductor wafer 1 is not particularly limited, but is preferably 20 to 200 μm from the viewpoint of thinning the semiconductor device, and preferably 20 to 100 μm from the viewpoint of easy stacking of semiconductor chips. . Moreover, when using the silicon penetration electrode 4c as the connection electrode 4, it is preferable that it is 20-50 micrometers from a viewpoint of making it easy to form an electrode with high density. Moreover, it is preferable that it is 30-50 micrometers from a viewpoint of improving the handleability of a thin wafer further. If the thickness of the first semiconductor wafer 1 is less than 20 μm, it is difficult to produce a wafer having a uniform thickness, and cracks are likely to occur during the mounting process. Further, when the thickness of the first semiconductor wafer 1 exceeds 200 μm, the resulting semiconductor device becomes thick, so that the number of stages of the semiconductor stacked body is limited, and it becomes difficult to sufficiently integrate the semiconductor stacked body.

  Examples of the connection electrode 4 include conductor patterns, pads, metal bumps (gold bumps, copper bumps, and bumps in which solder is formed on copper), silicon through electrodes, and the like, including metal bumps. Is preferred. The connection electrode 4 is formed by, for example, a gold stud bump formed using a gold wire, a metal ball fixed to an electrode pad by thermocompression using ultrasonic waves as necessary, plating, or vapor deposition. Bumps or the like may be used. The connection electrode 4 does not need to be composed of a single metal, and may include a plurality of metals. That is, the connection electrode 4 may include gold, silver, copper, nickel, indium, cobalt, palladium, tin, bismuth, or the like, or may be a laminate including a plurality of metal layers.

  The support 2 is not particularly limited as long as it can hold a semiconductor wafer having a thickness of 20 to 200 μm. However, a glass or silicon wafer is preferably used from the viewpoint of preventing contamination of the semiconductor wafer and further improving uniformity.

  The temporary fixing layer 3 is not particularly limited as long as it can hold a semiconductor wafer and can be easily peeled off after use, but a resin layer is preferably used because it is more excellent in workability.

  In the resin composition layer forming step (S2), as shown in FIG. 3A, what is the support 2 of the first semiconductor wafer 1 fixed on the support 2 via the temporary fixing layer 3? The resin composition layer 5 is formed on the opposite surface. In FIGS. 3 and 4, the first semiconductor wafer 1 shown in FIG. 2A is shown as the first semiconductor wafer 1.

  The resin composition layer 5 has adhesiveness to adherends such as semiconductor chips and substrates. For example, it is possible to bond the resist pattern and the adherend by applying pressure while heating the adherend as necessary.

  The resin composition layer 5 includes a thermosetting resin. The thermosetting resin is cured by being three-dimensionally cross-linked by heat. Examples of such thermosetting resins include epoxy resins, bismaleimide resins, triazine resins, polyimide resins, polyamide resins, cyanoacrylate resins, phenol resins, unsaturated polyester resins, melamine resins, urea resins, polyurethane resins, poly Examples include isocyanate resins, furan resins, resorcinol resins, xylene resins, benzoguanamine resins, diallyl phthalate resins, silicone resins, polyvinyl butyral resins, siloxane-modified epoxy resins, siloxane-modified polyamideimide resins, and acrylate resins. These can be used alone or as a mixture of two or more.

  The resin composition layer 5 may include a curing agent for promoting the curing reaction. The resin composition layer 5 preferably contains a latent curing agent in order to improve high reactivity and storage stability in a well-balanced manner.

  The resin composition layer 5 may contain a thermoplastic resin. Examples of such thermoplastic resins include polyester resins, polyether resins, polyamide resins, polyamideimide resins, polyimide resins, polyarylate resins, polyvinyl butyral resins, polyurethane resins, phenoxy resins, polyacrylate resins, polybutadienes, acrylonitrile butadienes. Examples thereof include a copolymer (NBR), an acrylonitrile butadiene rubber styrene resin (ABS), a styrene butadiene copolymer (SBR), and an acrylic acid copolymer. These can be used alone or in combination of two or more. Among these, from the viewpoint of improving the stickability to the first semiconductor wafer 1, a thermoplastic resin having a softening point near room temperature is preferable, and an acrylic acid copolymer containing glycidyl methacrylate or the like as a raw material is preferable.

  The resin composition layer 5 may contain a filler (inorganic particles) in order to make the linear expansion coefficient smaller. Such fillers may be crystalline or non-crystalline. When the linear expansion coefficient after curing of the resin composition layer 5 is small, thermal deformation can be suppressed. Therefore, it is possible to easily maintain the electrical connection between the protruding electrode of the semiconductor chip and the conductor pattern of the wiring board, so that the reliability of the semiconductor device manufactured by connecting the semiconductor chip and the wiring board is further increased. Can be improved.

  The resin composition layer 5 may include an additive such as a coupling agent. Thereby, the adhesiveness of a semiconductor chip and a wiring board can be improved.

  The resin composition layer 5 is a photosensitive resin composition that can be patterned by exposure and development. Even if this photosensitive resin composition is patterned, it is a form with preferable adhesiveness with respect to a to-be-adhered body by crimping, heating as needed. As a developing method, it is preferable that development with an alkaline aqueous solution is possible.

  The photosensitive resin composition that can be used as the resin composition layer 5 can be either a negative type or a positive type. In the present embodiment, a case where a negative type is used will be described.

  As a method of forming the resin composition layer 5, for example, a method of forming the resin composition layer 5 by preparing a film-like adhesive previously formed into a film shape and attaching the adhesive to the first semiconductor wafer 1. Is simple, but a method of forming a resin composition layer 5 by applying a liquid varnish containing an adhesive composition onto the first semiconductor wafer 1 using a spin coating method or the like, and drying by heating. It may be.

  As a method for attaching the film adhesive to the first semiconductor wafer, a laminating method is generally used. Examples of the laminating apparatus include an apparatus in which rollers are installed on the upper and lower sides of a film adhesive sheet, and an apparatus that presses the film adhesive on the first semiconductor wafer 1 in a vacuum state. It is preferable to heat the film adhesive when laminating. Accordingly, the resin composition layer 5 can be sufficiently adhered to the first semiconductor wafer 1 and the periphery of the connection electrode 4 can be sufficiently embedded so that there is no gap. The heating temperature should just be a grade which the resin composition layer 5 softens and does not harden | cure. When the resin composition layer 5 includes, for example, an epoxy resin, an acrylic acid copolymer having a softening temperature of 40 ° C., and a latent curing agent for an epoxy resin having a reaction start temperature of 100 ° C., the heating temperature is For example, it is 80 degreeC. Moreover, it is preferable to make heating temperature into 200 degrees C or less from a viewpoint of considering the heat resistance of a temporarily fixed layer.

  In the conductor exposing step (S3), as shown in FIG. 3B, first, an opening is formed at a predetermined position with respect to the resin composition layer 5 formed on the first semiconductor wafer 1. Actinic rays (typically ultraviolet rays) are irradiated through the mask 7. Thereby, the resin composition layer 5 is exposed in a predetermined pattern. After the exposure, as shown in FIG. 3 (c), the unexposed portion of the resin composition layer 5 is removed by development using an alkaline developer, whereby the connection terminal of the first semiconductor wafer 1 is obtained. The resin composition layer 5 is patterned so as to form an opening through which is exposed. Thereby, the connection electrode 4 is exposed from the resin composition layer 5.

  In the adhesive tape attaching step (S4), as shown in FIG. 4A, the adhesive tape 6 is attached to the surface of the first semiconductor wafer 1 opposite to the support 2. As the adhesive tape 6, it is preferable to use a dicing tape in consideration of the subsequent singulation step (S6). Further, when the support 2 is peeled, the peeling at the interface between the pressure-sensitive adhesive tape 6 and the resin composition layer 5 is suppressed, and in the subsequent peeling step (S7), the separated semiconductor chip is peeled off with the pressure-sensitive adhesive tape. In view of easy peeling from 6, it is more preferable to use a UV-type dicing tape whose adhesiveness is changed by UV.

  In the support peeling process (S5), as shown in FIG. 4B, the support 2 is peeled from the first semiconductor wafer 1 to which the adhesive tape 6 is attached. As a peeling method of the support body 2, it is preferable to peel by a peel method from the viewpoint of reducing damage to the first semiconductor wafer 1. Moreover, it is preferable to clean with a solvent after peeling in terms of reducing resin residues.

  In the singulation step (S6), as shown in FIG. 4C, the first semiconductor wafer 1 from which the support 2 has been peeled is singulated to obtain the semiconductor chip 8 with a resin composition. As a method of dividing into pieces, blade dicing, laser dicing, and stealth dicing are preferable.

  In the adhesive tape peeling step (S7), as shown in FIG. 5, the separated semiconductor chip 8 with a resin composition is peeled from the adhesive tape 6. FIG. 5A is a view showing the semiconductor chip 8 with a resin composition in the case where the electrode 4a shown in FIG. 2A is formed as the connection electrode 4, and FIG. ) Is a diagram showing the semiconductor chip 8 with a resin composition in the case where the electrode 4b shown in FIG. 2B is formed as the connection electrode 4, and FIG. It is a figure which shows the semiconductor chip 8 with a resin composition in case the silicon penetration electrode 4c shown to (c) of FIG.

  In a connection process (S8), as shown in FIGS. 6-8, the semiconductor chip 8 with a resin composition is connected to the connection member 9 which connects the semiconductor chip with a resin composition. Examples of the connection member 9 include a second semiconductor wafer 9a, a second semiconductor chip 9b, and a semiconductor element mounting support member 9c. The second semiconductor chip 9b is, for example, a semiconductor chip 8 with a resin composition from which the adhesive tape 6 has been peeled off in the adhesive tape peeling step (S7), and is connected to the connecting member 9 in the current connecting step (S8). A semiconductor chip 8 with a resin composition different from the semiconductor chip 8 with a resin composition to be used can be used. For example, in the connecting step (S8), as shown in FIG. 6A, one or more semiconductor chips 8 with a resin composition are heated on the second semiconductor chip 9b, which is the semiconductor chip 8 with a resin composition. Or it laminates | stacks by pressure bonding and the semiconductor element laminated body 10 is obtained. In the connecting step (S8), as shown in FIG. 6B, one or more semiconductor chips 8 with a resin composition are heated or applied to the second semiconductor wafer 9a or the semiconductor element mounting support member 9c. By laminating by pressure bonding, a wafer 11 with a semiconductor element laminate is obtained.

  The lamination method is not particularly limited. For example, as a preferred lamination method, as shown in FIG. 7 (a), the semiconductor chips 8 with individual resin compositions are laminated to form a semiconductor element. 7, a method of laminating the obtained semiconductor element stack 10 on the second semiconductor wafer 9 a or the semiconductor element mounting support member 9 c, as shown in FIG. As shown to c), the method of laminating | stacking the semiconductor chip 8 with the resin composition separated on the 2nd semiconductor wafer 9a or the supporting member 9c for semiconductor element mounting is mentioned.

  Although different from the above steps, as shown in FIG. 8A, the adhesive tape peeling step (S7) is performed before the individualization step (S6), and then the individualization step (S6). You may obtain the semiconductor wafer laminated body 12 by performing the connection process (S8) which laminates | stacks the 1st semiconductor wafers 1 before. Further, as shown in FIG. 8B, the semiconductor element stacked body 10 may be obtained by performing an individualization step (S6) in which the obtained semiconductor wafer stacked body 12 is divided into pieces by dicing. .

  As lamination conditions, for example, temperature: 150 ° C. to 400 ° C., pressure: 0.1 MPa to 2.0 MPa, time: 10 seconds to 1 hour can be set.

  A semiconductor device is obtained by the above method. As described above, according to the present embodiment, in the connection between the semiconductor chips or in the connection between the semiconductor chip and the semiconductor wafer or the semiconductor chip mounting support member, it is possible to realize a good connection state with low electrical resistance and high reliability. A semiconductor device can be obtained. In addition, since the first semiconductor wafer 1 is fixed on the support 2, workability is good even when a thinned wafer is used. A densified semiconductor element stack can be obtained.

  The method for manufacturing a semiconductor device of the present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 ... 1st semiconductor wafer, 2 ... Support body, 3 ... Temporary fixing layer, 4 ... Connection electrode, 4a ... Electrode, 4b ... Electrode, 4c ... Silicon penetration electrode, 5 ... Resin composition layer, 6 ... Adhesive tape DESCRIPTION OF SYMBOLS 7 ... Mask, 8 ... Semiconductor chip with resin composition, 9 ... Connection member, 9a ... Second semiconductor wafer, 9b ... Second semiconductor chip, 9c ... Semiconductor element mounting support member, 10 ... Semiconductor element laminate 11 ... Wafer with semiconductor element laminate, 12 ... Semiconductor wafer laminate.

Claims (6)

A resin composition layer forming step of forming a resin composition layer on the surface of the first semiconductor wafer fixed on the support and having a conductor on the surface opposite to the support;
A conductor exposing step of exposing and developing the resin composition layer to expose the conductor;
An adhesive tape attaching step of attaching an adhesive tape to the surface of the first semiconductor wafer opposite to the support;
A support peeling process for peeling the support from the first semiconductor wafer;
An individualization step for obtaining a semiconductor chip with a resin composition by separating the first semiconductor wafer;
An adhesive tape peeling step for peeling the semiconductor chip with the resin composition from the adhesive tape;
A connecting step of connecting the semiconductor chip with a resin composition to a connecting member for connecting the semiconductor chip with a resin composition in this order,
A method for manufacturing a semiconductor device. The conductor includes a metal bump,
A method for manufacturing a semiconductor device according to claim 1. The conductor includes a silicon through electrode that penetrates the first semiconductor wafer.
A method for manufacturing a semiconductor device according to claim 1.   The wafer with a semiconductor element laminated body produced using the manufacturing method of the semiconductor device as described in any one of Claims 1-3.   The semiconductor element laminated body produced using the manufacturing method of the semiconductor device as described in any one of Claims 1-3. The semiconductor device produced using the manufacturing method of the semiconductor device as described in any one of Claims 1-3.

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