JP2010135777A5 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2010135777A5
JP2010135777A5 JP2009253687A JP2009253687A JP2010135777A5 JP 2010135777 A5 JP2010135777 A5 JP 2010135777A5 JP 2009253687 A JP2009253687 A JP 2009253687A JP 2009253687 A JP2009253687 A JP 2009253687A JP 2010135777 A5 JP2010135777 A5 JP 2010135777A5
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Japan
Prior art keywords
oxide semiconductor
semiconductor layer
wiring
gate electrode
insulating layer
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JP2009253687A
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Japanese (ja)
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JP2010135777A (en
JP5587591B2 (en
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Priority to JP2009253687A priority Critical patent/JP5587591B2/en
Priority claimed from JP2009253687A external-priority patent/JP5587591B2/en
Publication of JP2010135777A publication Critical patent/JP2010135777A/en
Publication of JP2010135777A5 publication Critical patent/JP2010135777A5/en
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Claims (3)

第1のゲート電極と、A first gate electrode,
第2のゲート電極と、A second gate electrode,
前記第1のゲート電極及び前記第2のゲート電極上の第1の絶縁層と、A first insulating layer on the first gate electrode and the second gate electrode;
前記第1の絶縁層上に設けられ、前記第1のゲート電極と重なる領域を有する第1の酸化物半導体層と、A first oxide semiconductor layer provided over the first insulating layer and having a region overlapping with the first gate electrode;
前記第1の絶縁層上に設けられ、前記第2のゲート電極と重なる領域を有する第2の酸化物半導体層と、A second oxide semiconductor layer provided over the first insulating layer and having a region overlapping with the second gate electrode;
前記第1の絶縁層上の第1の配線と、A first wire on the first insulating layer,
前記第1の絶縁層上の第2の配線と、A second wire on the first insulating layer,
前記第1の絶縁層上の第3の配線と、A third wire on the first insulating layer,
前記第1の酸化物半導体層及び前記第2の酸化物半導体層上の有機絶縁層と、An organic insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer;
を有し、Have
前記第1の酸化物半導体層上に、前記第1の配線及び前記第2の配線を有し、The first wiring and the second wiring are provided over the first oxide semiconductor layer,
前記第2の酸化物半導体層上に、前記第2の配線及び前記第3の配線を有し、The second wiring and the third wiring are provided over the second oxide semiconductor layer,
前記第1の配線は、前記第1の酸化物半導体層に電気的に接続され、The first wiring is electrically connected to the first oxide semiconductor layer,
前記第2の配線は、前記第1の酸化物半導体層及び前記第2の酸化物半導体層に電気的に接続され、The second wiring is electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer,
前記第3の配線は、前記第2の酸化物半導体層に電気的に接続され、The third wiring is electrically connected to the second oxide semiconductor layer,
前記第2の配線は、前記第1の絶縁層に設けられたコンタクトホールを介して、前記第2のゲート電極に電気的に接続されていることを特徴とする半導体装置。A semiconductor device characterized in that the second wiring is electrically connected to the second gate electrode through a contact hole provided in the first insulating layer.
第1のゲート電極と、A first gate electrode,
第2のゲート電極と、A second gate electrode,
前記第1のゲート電極及び前記第2のゲート電極上の第1の絶縁層と、A first insulating layer on the first gate electrode and the second gate electrode;
前記第1の絶縁層上に設けられ、前記第1のゲート電極と重なる領域を有する第1の酸化物半導体層と、A first oxide semiconductor layer provided over the first insulating layer and having a region overlapping with the first gate electrode;
前記第1の絶縁層上に設けられ、前記第2のゲート電極と重なる領域を有する第2の酸化物半導体層と、A second oxide semiconductor layer provided over the first insulating layer and having a region overlapping with the second gate electrode;
前記第1の絶縁層上の第1の配線と、A first wire on the first insulating layer,
前記第1の絶縁層上の第2の配線と、A second wire on the first insulating layer,
前記第1の絶縁層上の第3の配線と、A third wire on the first insulating layer,
前記第1の酸化物半導体層及び前記第2の酸化物半導体層上の有機絶縁層と、An organic insulating layer on the first oxide semiconductor layer and the second oxide semiconductor layer;
を有し、Have
前記第1の酸化物半導体層上に、前記第1の配線及び前記第2の配線を有し、The first wiring and the second wiring are provided over the first oxide semiconductor layer,
前記第2の酸化物半導体層上に、前記第2の配線及び前記第3の配線を有し、The second wiring and the third wiring are provided over the second oxide semiconductor layer,
前記第1の配線は、前記第1の酸化物半導体層に電気的に接続され、The first wiring is electrically connected to the first oxide semiconductor layer,
前記第2の配線は、前記第1の酸化物半導体層及び前記第2の酸化物半導体層に電気的に接続され、The second wiring is electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer,
前記第3の配線は、前記第2の酸化物半導体層に電気的に接続され、The third wiring is electrically connected to the second oxide semiconductor layer,
前記第3の配線は、前記第1の絶縁層に設けられたコンタクトホールを介して、前記第2のゲート電極に電気的に接続されていることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein the third wiring is electrically connected to the second gate electrode through a contact hole provided in the first insulating layer.
請求項1又は請求項2において、In claim 1 or claim 2,
前記第1の酸化物半導体層及び前記第2の酸化物半導体層は、結晶領域を有することを特徴とする半導体装置。A semiconductor device characterized in that the first oxide semiconductor layer and the second oxide semiconductor layer have a crystalline region.
JP2009253687A 2008-11-07 2009-11-05 Semiconductor device Active JP5587591B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009253687A JP5587591B2 (en) 2008-11-07 2009-11-05 Semiconductor device

Applications Claiming Priority (3)

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JP2008286900 2008-11-07
JP2008286900 2008-11-07
JP2009253687A JP5587591B2 (en) 2008-11-07 2009-11-05 Semiconductor device

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JP2014150498A Division JP2014241424A (en) 2008-11-07 2014-07-24 Semiconductor device

Publications (3)

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JP2010135777A JP2010135777A (en) 2010-06-17
JP2010135777A5 true JP2010135777A5 (en) 2012-11-15
JP5587591B2 JP5587591B2 (en) 2014-09-10

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