JP2010135777A - Thin film transistor, display device, and manufacturing methods thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor whose electric characteristics can be enhanced in reliability, a display device which can be enhanced in picture quality, and manufacturing methods thereof. <P>SOLUTION: The thin film transistor includes a gate electrode, a gate insulating layer formed on the gate electrode, an oxide semiconductor layer overlapping the gate electrode and formed on the gate insulating layer, an interconnect formed on the gate insulating layer and oxide semiconductor layer, and an organic resin layer brought into contact with the oxide semiconductor layer and interconnects. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a display device using an oxide semiconductor and a manufacturing method thereof.

As represented by a liquid crystal display device, a thin film transistor formed on a flat plate such as a glass substrate is made of amorphous silicon or polycrystalline silicon. A thin film transistor using amorphous silicon can cope with an increase in the area of a glass substrate although the field effect mobility is low. On the other hand, a thin film transistor using crystalline silicon has a high field effect mobility, but crystal such as laser annealing. Therefore, it has a characteristic that it is not necessarily adapted to increase the area of the glass substrate.

In contrast, a technique in which a thin film transistor is manufactured using an oxide semiconductor and applied to an electronic device or an optical device has attracted attention. For example, Patent Document 1, Patent Document 2, and Non-Patent Documents describe a technique in which a thin film transistor is manufactured using zinc oxide or an In—Ga—Zn—O-based oxide semiconductor as an oxide semiconductor layer and used for a switching element of a display device. It is disclosed in Document 1.

JP 2007-123861 A JP 2007-96055 A

Y. Park et al. IDW'07, p. 1775-p. 1778

However, in a thin film transistor using an oxide semiconductor layer, as a passivation layer of the oxide semiconductor layer, a silicon nitride layer formed using a plasma CVD method using any one of silane, nitrogen dioxide, ammonia, nitrogen, or the like as a source gas, Alternatively, when a silicon oxide layer is used, there is a problem in that reliability of electric characteristics of the thin film transistor is reduced.

Thus, it is an object to provide a thin film transistor that can improve the reliability of electric characteristics of the thin film transistor and a manufacturing method thereof. Another object is to provide a display device capable of improving image quality and a manufacturing method thereof.

The thin film transistor includes a gate electrode, an oxide semiconductor layer overlapping with the gate electrode, an organic resin layer in contact with the oxide semiconductor layer, and a wiring provided between the oxide semiconductor layer and the organic resin layer.

In addition, a gate electrode, a gate insulating layer formed over the gate electrode, an oxide semiconductor layer overlapping with the gate electrode and formed over the gate insulating layer, and formed over the gate insulating layer and the oxide semiconductor layer The thin film transistor includes a wiring formed, an oxide semiconductor layer, and an organic resin layer in contact with the wiring.

In addition, the display device includes the thin film transistor in a driver circuit and a pixel portion.

Note that the oxide semiconductor layer is a thin film represented by InMO ₃ (ZnO) _m (m> 0), and M is gallium (Ga), iron (Fe), nickel (Ni), manganese (Mn), and One or more metal elements selected from cobalt (Co) are shown. For example, M may be Ga, and may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. In addition to the metal element included as M, the oxide semiconductor layer may include Fe, Ni, other transition metal elements, or an oxide of the transition metal as an impurity element. Here, the thin film with M = gallium (Ga) is also referred to as an In—Ga—Zn—O-based non-single-crystal layer.

The crystal structure of the In—Ga—Zn—O-based non-single-crystal layer can be formed by sputtering and then heated at 200 to 500 ° C., typically 300 to 400 ° C. for 10 to 100 minutes. An amorphous structure is observed by XRD (X-ray diffraction) measurement. Further, by using an In—Ga—Zn—O-based non-single-crystal layer, a thin film transistor having an electrical property with an on / off ratio of 10 ⁹ or more and a mobility of 10 cm ² / Vs or more at a gate voltage of ± 20 V is manufactured. be able to.

It is useful to use a thin film transistor having such electrical characteristics for a driver circuit. For example, the gate line driver circuit includes a shift register circuit that sequentially transfers gate signals and a buffer circuit, and the source line driver circuit includes a shift register that sequentially transfers gate signals, a buffer circuit, and an image to a pixel. It consists of an analog switch that switches on / off of signal transfer. A thin film transistor using an oxide semiconductor layer having higher mobility than a thin film transistor using amorphous silicon can drive a shift register circuit at high speed.

In the case where at least part of a driver circuit for driving the pixel portion is formed using a thin film transistor including an oxide semiconductor, the driver circuit is formed using n-channel TFTs, and the circuit illustrated in FIG. 1B is used as a basic unit. Form. In the driver circuit, a good contact can be obtained and contact resistance can be reduced by directly connecting the gate electrode and the source wiring or the drain wiring. In the driving circuit, when the gate electrode and the source wiring or the drain wiring are connected through another conductive layer, for example, a transparent conductive layer, the number of contact holes increases, the occupied area increases due to the increase in the number of contact holes, or There is a possibility that the contact resistance and the wiring resistance increase, and further the process becomes complicated.

In addition, since the thin film transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driver circuit over the same substrate for the gate line or the source line. The protection circuit is preferably formed using a non-linear element using an oxide semiconductor.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

In addition to a liquid crystal display device, a display device including a driver circuit includes a light-emitting display device using a light-emitting element and a display device also called electronic paper using an electrophoretic display element.

A light-emitting display device using a light-emitting element includes a plurality of thin film transistors in a pixel portion, and a portion in which a gate electrode of a thin film transistor in the pixel portion is directly connected to a source wiring or a drain wiring of another thin film transistor. Yes. In addition, a driver circuit of a light-emitting display device using a light-emitting element has a portion where a gate electrode of a thin film transistor and a source wiring or a drain wiring of the thin film transistor are directly connected.

In a thin film transistor using an oxide semiconductor, a thin film transistor with high electrical characteristics can be manufactured by forming an organic insulating layer in contact with the oxide semiconductor. In addition, a display device with improved image quality can be manufactured.

4A and 4B are a cross-sectional view, an equivalent circuit diagram, and a top view illustrating one embodiment of a display device. 4A and 4B are an equivalent circuit diagram and a top view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a process of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a process of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a process of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. 10A and 10B are a cross-sectional view and a top view illustrating one embodiment of a display device. FIG. 11 is a top view illustrating one embodiment of a display device. It is sectional drawing of electronic paper. FIG. 11 is a diagram illustrating a block diagram of one embodiment of a display device. It is a figure explaining the structure of a signal line drive circuit. 6 is a timing chart for explaining the operation of the signal line driving circuit. 6 is a timing chart for explaining the operation of the signal line driving circuit. It is a figure explaining the structure of a shift register. It is a figure explaining the connection structure of the flip-flop shown in FIG. FIG. 11 is an equivalent circuit diagram illustrating one embodiment of a pixel equivalent circuit of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. 10A and 10B are a cross-sectional view and a top view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. 10A and 10B are a cross-sectional view and a top view illustrating one embodiment of a display device. It is a figure explaining the example of the usage pattern of electronic paper. It is an external view explaining an example of an electronic book. It is an external view explaining the example of a television apparatus and a digital photo frame. It is an external view explaining the example of a gaming machine. It is an external view explaining an example of a mobile phone. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a process of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. FIG. 10 is a top view illustrating one embodiment of a process of a display device. It is a figure explaining a multi-tone mask. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 11 is a top view illustrating one embodiment of a display device. FIG. 11 illustrates one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. FIG. 10 is a cross-sectional view illustrating one embodiment of a display device. 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a display device. It is a figure explaining the reuse cycle of the oxide semiconductor contained in etching waste liquid. It is a figure explaining the process of reusing the oxide semiconductor contained in etching waste liquid.

Hereinafter, embodiments will be described in detail with reference to the drawings. However, the disclosed invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the disclosed invention. The Therefore, the disclosed invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
Here, a description will be given below based on an example in which an inverter circuit is configured using two n-channel thin film transistors.

A cross-sectional structure of the inverter circuit of the driver circuit is illustrated in FIG. Note that each of the first thin film transistor 430 and the second thin film transistor 431 illustrated in FIGS. 1A and 1B is an inverted staggered thin film transistor, which is an example of a thin film transistor in which a wiring is provided over an oxide semiconductor layer through a source region or a drain region.

In FIG. 1A, a first gate electrode 401 and a second gate electrode 402 are formed over a substrate 400. A gate insulating layer 403 is formed on the first gate electrode 401 and the second gate electrode 402. In addition, a first oxide semiconductor layer 405 in contact with the gate insulating layer 403 is formed at a position overlapping with the first gate electrode 401, and a second oxide semiconductor in contact with the gate insulating layer 403 at a position overlapping with the second gate electrode 402. Layer 407 is formed. A first wiring 409 and a second wiring 410 are formed over the first oxide semiconductor layer 405. In addition, n ⁺ layers 406 a and 406 b functioning as a source region or a drain region are formed between the first oxide semiconductor layer 405 and the first wiring 409 and the second wiring 410. In addition, n ⁺ layers 408 a and 408 b functioning as a source region or a drain region are formed between the second oxide semiconductor layer 407, the second wiring 410, and the third wiring 411. The second wiring 410 is directly connected to the second gate electrode 402 through a contact hole 404 formed in the gate insulating layer 403. In addition, the second wiring 410 and the third wiring 411 are formed over the second oxide semiconductor layer 407. In addition, an organic insulating layer 452 in contact with the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407 is formed. A composition is applied over the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407, the first wiring 409 to the third wiring 411, and the gate insulating layer 403, and then fired, whereby the first oxide semiconductor layer is formed. Since the organic insulating layer 452 in contact with the layer 405 and the second oxide semiconductor layer 407 can be formed, a thin film transistor with high reliability in electrical characteristics can be manufactured.

As the substrate 400, a light-transmitting substrate is preferably used, and examples of the light-transmitting substrate include barium borosilicate glass and aluminoborosilicate glass typified by Corning 7059 glass and 1737 glass. A glass substrate can be used.

The material of the first gate electrode 401 and the second gate electrode 402 is an element selected from aluminum, copper, molybdenum, tungsten, or an element selected from the above, or the elements described above, titanium, tantalum, tungsten, molybdenum, and chromium. , Neodymium, an alloy containing scandium, or the like, or a single layer or a stacked structure using a nitride of the above element.

For example, the two-layer structure of the first gate electrode 401 and the second gate electrode 402 includes a structure in which a molybdenum layer is stacked on an aluminum layer, a structure in which a molybdenum layer is stacked on a copper layer, or a structure on a copper layer It is preferable to have a stacked structure in which a titanium nitride layer or a tantalum nitride layer is stacked, or a structure in which a titanium nitride layer and a molybdenum layer are stacked. The three-layer structure is preferably a structure in which a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are stacked.

The gate insulating layer 403 can be formed using a single layer or a stacked layer of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer. In the case where the gate insulating layer 403 has a stacked structure, a silicon nitride layer or a silicon nitride oxide layer is formed over the substrate 400 and a silicon oxide layer or a silicon oxynitride layer can be formed thereover.

A first oxide semiconductor layer 405 and a second oxide semiconductor layer 407 are provided over the gate insulating layer 403 that covers the first gate electrode 401 and the second gate electrode 402.

The first oxide semiconductor layer 405 and the second oxide semiconductor layer 407 form a layer represented by InMO ₃ (ZnO) _m (m> 0). Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Ni, Mn, and Co. For example, M may be Ga, and may contain the above metal elements other than Ga, such as Ga and Ni or Ga and Fe. In addition to the metal element contained as M, some of the above oxide semiconductors contain Fe, Ni, other transition metal elements, or oxides of the transition metal as impurity elements. In this specification, this thin film is also referred to as an In—Ga—Zn—O-based non-single-crystal film. The concentration of mobile ions in the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407, typically sodium, is 5 × 10 ¹⁸ / cm ³ or less, and further 1 × 10 ¹⁸ / cm ³ or less. It is preferable that the electrical characteristics of the thin film transistor can be prevented from changing.

In this embodiment, the n ⁺ layers 406 a, 406 b, 408 a, and 408 b functioning as a source region or a drain region are In—Ga—Zn—O-based non-single-crystal layers, the first oxide semiconductor layer 405, The oxide semiconductor layer has a lower resistance and is formed under conditions different from the conditions for forming the two oxide semiconductor layers 407. For example, the n ⁺ layers 406a, 406b, 408a, and 408b have n-type conductivity and have an activation energy (ΔE) of 0.01 eV or more and 0.1 eV or less. Note that in this embodiment, the n ⁺ layers 406a, 406b, 408a, and 408b are In—Ga—Zn—O-based non-single-crystal layers and include at least an amorphous component. The n ⁺ layers 406a, 406b, 408a, and 408b may include crystal grains (nanocrystals) in an amorphous structure. The crystal grains (nanocrystals) in the n ⁺ layers 406a, 406b, 408a, and 408b have a diameter of 1 nm to 10 nm, typically about 2 nm to 4 nm.

By providing the n ⁺ layers 406a, 406b, 408a, and 408b, the first wiring 409, the second wiring 410, and the third wiring 411 that are metal layers, the first oxide semiconductor layer 405, and the second oxide semiconductor layer 407 are provided. As a good junction, it is possible to have a thermally stable operation compared to a Schottky junction. In addition, an n ⁺ layer is positively provided to supply channel carriers (source side), stably absorb channel carriers (drain side), or not to create a resistance component at the interface with the wiring. And effective. Further, by reducing the resistance, good mobility can be maintained even at a high drain voltage.

Examples of the material of the first wiring 409 to the third wiring 411 include an element selected from aluminum, chromium, tantalum, titanium, molybdenum, and tungsten, an alloy containing the above-described elements as a main component, or an alloy combining the above-described elements. There is. The first wiring 409 to the third wiring 411 may have a single-layer structure of an aluminum layer containing silicon or a single-layer structure of a titanium layer. The first wiring 409 to the third wiring 411 may have a two-layer structure, and a titanium layer may be stacked over the aluminum layer.

In the case where heat treatment at 200 ° C. to 600 ° C. is performed in a later step, it is preferable that the first wiring 409 to the third wiring 411 have heat resistance enough to withstand the heat treatment. Since aluminum alone has problems such as poor heat resistance and easy corrosion, it is formed in combination with a heat resistant conductive material. As a heat-resistant conductive material combined with aluminum, an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, an alloy containing the above-mentioned elements as a main component, an alloy combining a plurality of the above-described elements, or It is formed of the nitride of the element described above.

The first thin film transistor 430 includes a first gate electrode 401 and a first oxide semiconductor layer 405 that overlaps the first gate electrode 401 with the gate insulating layer 403 interposed therebetween. The first wiring 409 is a power supply line having a ground potential. (Ground power line). The power supply line having the ground potential may be a power supply line (negative power supply line) to which a negative voltage VDL is applied.

The second thin film transistor 431 includes a second gate electrode 402 and a second oxide semiconductor layer 407 that overlaps with the second gate electrode 402 with the gate insulating layer 403 interposed therebetween. The third wiring 411 has a positive voltage. A power supply line (positive power supply line) to which VDD is applied.

As shown in FIG. 1A, the second wiring 410 electrically connected to both the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407 is formed in a contact hole 404 formed in the gate insulating layer 403. And is directly connected to the second gate electrode 402 of the second thin film transistor 431. By direct connection, good contact can be obtained and contact resistance can be reduced. Compared to the case where the second gate electrode 402 and the second wiring 410 are connected via another conductive layer, for example, a transparent conductive layer, the number of contact holes is reduced, and the occupied area is reduced by reducing the number of contact holes. be able to.

The organic insulating layer 452 can be formed without damaging the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407 by applying and baking the composition. Organic materials that can be used as the organic insulating layer 452 include epoxy resin, polyimide, acrylic resin, polyacrylonitrile, polyamide, silicone resin, polyester, siloxane polymer, fluorine-containing polymer, and low dielectric constant material (low-k material). PSG (phosphorus glass), BPSG (phosphorus boron glass), and the like.

The organic insulating layer 452 may have a function of preferentially transmitting light in an arbitrary wavelength range in the visible light wavelength range. An organic insulating layer that preferentially transmits light in the red wavelength range, light in the blue wavelength range, and light in the green wavelength range may be combined to function as a color filter. However, the combination of the colored layers is not limited to this.

In this embodiment, the organic insulating layer 452 formed by a coating method is formed in contact with the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407, so that reliability of electric characteristics of the thin film transistor is improved. be able to.

A top view of the inverter circuit of the driver circuit is shown in FIG. In FIG. 1C, a cross section taken along the chain line Z1-Z2 corresponds to FIG.

Note that in the display device, a driver circuit for driving the pixel portion is formed using an inverter circuit, a capacitor, a resistor, and the like. When an inverter circuit is formed by combining two n-channel thin film transistors, an enhancement type transistor and a depletion type transistor are combined (hereinafter referred to as an EDMOS circuit), or an enhancement type thin film transistor (hereinafter referred to as an enhancement type thin film transistor). EEMOS circuit). Note that when the threshold voltage of the n-channel thin film transistor is positive, it is defined as an enhancement type transistor, and when the threshold voltage of the n-channel thin film transistor is zero or negative, it is defined as a depletion type transistor. This definition shall be followed throughout the document.

The pixel portion and the driver circuit are formed over the same substrate, and in the pixel portion, on / off of voltage application to the pixel electrode is switched using enhancement type transistors arranged in a matrix. The enhancement-type transistor disposed in this pixel portion uses an oxide semiconductor, and its electrical characteristics are such that an on / off ratio is 10 ⁹ or more at a gate voltage of ± 20 V, so that there is little leakage current and low power consumption. Driving can be realized.

An equivalent circuit of the EDMOS circuit is shown in FIG. 1A and 1C corresponds to FIG. 1B. The first thin film transistor 430 is an enhancement type n-channel transistor, and the second thin film transistor 431 is a depletion type n-channel type. This is an example of a transistor.

As a method for manufacturing an enhancement type n-channel transistor and a depletion type n-channel transistor over the same substrate, for example, the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407 are formed of different materials or differently. Fabricate using conditions. In addition, threshold values are controlled by providing gate electrodes above and below the oxide semiconductor layer so that a voltage is applied to the gate electrode so that one TFT is normally on, and the other TFT is normally off. Thus, an EDMOS circuit may be configured.

In the thin film transistor described in this embodiment, an organic insulating layer is formed over an oxide semiconductor layer; thus, reliability of electric characteristics of the thin film transistor can be improved.

(Embodiment 2)
Although Embodiment 1 shows an example of an EDMOS circuit, FIG. 2A shows an equivalent circuit of an EEMOS circuit in this embodiment. A top view of the EEMOS is shown in FIG. FIG. 3 shows a manufacturing process of the EEMOS circuit shown in FIG. In the equivalent circuit in FIG. 2A, both are combinations of enhancement type n-channel transistors.

By using the EEMOS circuit in FIG. 2A which can be manufactured using an enhancement type n-channel transistor for a driver circuit, an enhancement type n-channel transistor is manufactured in the driver circuit as well as the transistor used for the pixel portion. Therefore, it can be said that the manufacturing process does not increase and is preferable.

Note that each of the first thin film transistor 460 and the second thin film transistor 461 illustrated in FIGS. 2A and 2B is an inverted staggered thin film transistor and is an example of a thin film transistor in which a wiring is provided over an oxide semiconductor layer through a source region or a drain region.

A cross section taken along chain line Y1-Y2 in FIG. 2B corresponds to FIG.

A first conductive layer is formed over the substrate 440 by a sputtering method. Next, the first conductive layer is selectively etched using the resist mask formed by a photolithography process using the first photomask, so that the first gate electrode 441 and the second gate electrode 442 are formed. Thereafter, the resist mask is removed.

Next, a gate insulating layer 443 that covers the first gate electrode 401 and the second gate electrode 442 is formed by a plasma CVD method or a sputtering method. The gate insulating layer 443 can be formed using the materials listed in Embodiment 1 by a CVD method, a sputtering method, or the like. As the gate insulating layer 443, a silicon oxide layer can be formed by a CVD method using an organosilane gas. Examples of the organic silane gas include ethyl silicate (TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ), tetramethylsilane (TMS: chemical formula Si (CH ₃ ) ₄ ), tetramethylcyclotetrasiloxane (TMCTS), and octamethylcyclotetrasiloxane. It is possible to use a silicon-containing compound such as (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH (OC ₂ H ₅ ) ₃ ), trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ). it can.

Next, the gate insulating layer 443 is selectively etched using a resist mask formed by a photolithography process using a second photomask, so that a contact hole 444 reaching the second gate electrode 442 is formed. Thereafter, the resist mask is removed. A cross-sectional view of the steps so far corresponds to FIG.

Next, an oxide semiconductor layer is formed by a sputtering method, and an n ⁺ layer is further formed thereover. Note that before the oxide semiconductor layer is formed by a sputtering method, reverse sputtering that generates plasma by introducing argon gas is performed, so that dust attached to the surface of the gate insulating layer 443 and the bottom surface of the contact hole 444 is removed. It is preferable to do. Inverse sputtering is a method of modifying the surface by forming a plasma on a substrate by applying a voltage using an RF power source on the substrate side in an argon atmosphere without applying a voltage to the target side. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an atmosphere in which oxygen, hydrogen, N ₂ O, or the like is added to an argon atmosphere may be used. Alternatively, an atmosphere in which Cl ₂ , CF _4, or the like is added to an argon atmosphere may be used. Note that when reverse sputtering is performed, the surface of the gate insulating layer 403 is cut by about 2 to 10 nm, preferably about 2 to 10 nm.

As the sputtering method, there are an RF sputtering method using a high-frequency power source as a sputtering power source and a DC sputtering method, and a pulse DC sputtering method for applying a bias in a pulsed manner. The RF sputtering method is mainly used when an insulating layer is formed, and the DC sputtering method is mainly used when a metal layer is formed.

There is also a multi-source sputtering apparatus in which a plurality of targets of different materials can be installed. The multi-source sputtering apparatus can be formed by stacking different material layers in the same chamber or by simultaneously discharging a plurality of types of materials in the same chamber.

In addition, there is a sputtering apparatus using a magnetron sputtering method having a magnet mechanism inside a chamber, and a sputtering apparatus using an ECR sputtering method using plasma generated using microwaves without using glow discharge.

As a forming method, there are a reactive sputtering method in which a target material and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is applied to the substrate during film formation. .

In the sputtering of this specification, the above-described sputtering apparatus and sputtering method can be used as appropriate.

Next, selectively using a third photo mask, the etching of the oxide semiconductor layer and the n ⁺ layer. Thereafter, the resist mask is removed.

Next, a second conductive layer is formed by a sputtering method. Next, the second conductive layer is selectively etched using a resist mask formed by a photolithography process using a fourth photomask to form a first wiring 449, a second wiring 450, and a third wiring 451. To do. The third wiring 451 is in direct contact with the second gate electrode 442 through the contact hole 444.

Note that before the second conductive layer is formed by a sputtering method, reverse sputtering that generates plasma by introducing argon gas is performed, and the surface of the gate insulating layer 443, the surface of the n ⁺ layer, and the bottom surface of the contact hole 444 are formed. It is preferable to remove adhering dust. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an atmosphere in which oxygen, hydrogen, N ₂ O, or the like is added to an argon atmosphere may be used. Alternatively, an atmosphere in which Cl ₂ , CF _4, or the like is added to an argon atmosphere may be used.

Note that when the second conductive layer is etched, the n ⁺ layer and a part of the oxide semiconductor layer are further etched, so that the n ⁺ layers 446a, 446b, 448a, 448b, the first oxide semiconductor layer 445, A two-oxide semiconductor layer 447 is formed. By this etching, the thickness of the first oxide semiconductor layer 445 and the second oxide semiconductor layer 447 which overlap with the first gate electrode and the second gate electrode is reduced. Thereafter, the resist mask is removed. When the etching is completed, the first thin film transistor 460 and the second thin film transistor 461 are completed. A cross-sectional view of the steps so far corresponds to FIG.

Here, an enlarged view of the first thin film transistor 460 is shown in FIG. If reverse sputtering is performed before the second conductive layer is formed by the sputtering method, the exposed portion of the gate insulating layer 443 is removed by about 2 to 10 nm, preferably about 2 to 10 nm. Therefore, as shown in FIG. Recesses 471a and 471b are formed in the gate insulating layer 443 in a region where the first wiring 449 and the second wiring 450, which are formed later, are in contact with each other.

Further, after the second conductive layer is etched to form the first wiring 449, the second wiring 450, and the third wiring 451, reverse sputtering is performed, so that the first wiring is formed as shown in FIG. The ends of 449, the second wiring 450, and the third wiring 451 are curved.

Next, heat treatment is performed at 200 ° C. to 600 ° C. in an air atmosphere or a nitrogen atmosphere. By this heat treatment, rearrangement at the atomic level of the In—Ga—Zn—O-based non-single-crystal layer is performed. Since heat treatment releases strain that hinders carrier movement, heat treatment here (including optical annealing) is important. Note that the timing of performing this heat treatment is not limited and may be any time after the oxide semiconductor layers 445 and 447 are formed.

Next, a composition that is a material for the organic insulating layer is applied, and heat treatment is performed at 200 ° C. to 600 ° C. in an air atmosphere or a nitrogen atmosphere, so that the organic insulating layer 452 is formed. For the organic insulating layer 452, the material described in Embodiment 1 can be used as appropriate. 3C illustrates a mode in which the organic insulating layer 452 is formed using a non-photosensitive resin, the end portion of the organic insulating layer 452 is square in the cross section of the region where the contact hole is formed. However, when the organic insulating layer 452 is formed using a photosensitive resin, as shown in FIG. 44, the end of the organic insulating layer 452 is curved in the cross section of the region where the contact hole is formed. As a result, the coverage of connection wirings 453 and pixel electrodes formed later is improved.

Further, instead of applying the composition, dip, spray coating, ink jet method, printing method, doctor knife, roll coater, curtain coater, knife coater or the like can be used depending on the material.

Note that heat treatment after the oxide semiconductor layers 445 and 447 are formed may be combined with heat treatment of the oxide semiconductor layers 445 and 447 at the time of heat treatment of the composition that is a material of the organic insulating layer.

The organic insulating layer 452 is formed with a thickness of 200 nm to 5 μm, preferably 300 nm to 1 μm.

Next, a third conductive layer is formed. Next, the third conductive layer is selectively etched using a resist mask formed by a photolithography process using a fifth photomask, so that connection wirings 453 that are electrically connected to the second wirings 410 are formed. A cross-sectional view of the steps so far corresponds to FIG.

Note that after the resist mask is removed by wet etching, heat treatment at 200 ° C. to 600 ° C. may be performed in an air atmosphere or a nitrogen atmosphere.

In a light-emitting display device using a light-emitting element, a pixel portion includes a plurality of thin film transistors, and in the pixel portion, a gate electrode of one thin film transistor and a source wiring or a drain wiring of another transistor are directly connected. Has a contact hole. This contact hole can be formed using the same mask when the contact hole is formed in the gate insulating layer using the second photomask.

In a liquid crystal display device or electronic paper, when a contact hole reaching a gate wiring is formed in a terminal portion for connecting to an external terminal such as an FPC, a contact hole is formed in the gate insulating layer using a second photomask. When forming, the same mask can be used.

In addition, the process sequence mentioned above is an example, and is not specifically limited. For example, although the number of photomasks increases by one, etching may be performed separately using a photomask for etching the second conductive layer and a photomask for etching part of the n ⁺ layer and the oxide semiconductor layer.

By forming the organic insulating layer in contact with the oxide semiconductor layer through the above steps, a thin film transistor with high electrical characteristics can be manufactured.

(Embodiment 3)
In this embodiment, an example of a manufacturing process which is different from that in Embodiment 2 in manufacturing an inverter circuit is described with reference to FIGS. 4A, 4B, and 4C.

A first conductive layer is formed over the substrate 440 by a sputtering method. Next, the first conductive layer is selectively etched using the resist mask formed by a photolithography process using the first photomask, so that the first gate electrode 441 and the second gate electrode 442 are formed. Thereafter, the resist mask is removed.

Next, a gate insulating layer 443 that covers the first gate electrode 441 and the second gate electrode 442 is formed by a plasma CVD method or a sputtering method.

Next, an oxide semiconductor layer is formed by a sputtering method, and an n ⁺ layer is further formed thereover.

Next, the oxide semiconductor layer and the n ⁺ layer are selectively etched using a resist mask formed by a photolithography process using a second photomask. Thus, the oxide semiconductor layer 454 and the n ⁺ layer 455 which overlap with the first gate electrode 441 through the gate insulating layer 443 are formed, and the oxide semiconductor layer 456 which overlaps with the second gate electrode 442 through the gate insulating layer 443 is formed. , N ⁺ layer 457 is formed. A cross-sectional view of the steps so far corresponds to FIG.

Next, the gate insulating layer 443 is selectively etched using a resist mask formed by a photolithography process using a third photomask, so that a contact hole 444 reaching the second gate electrode 442 is formed. Thereafter, the resist mask is removed. A cross-sectional view of the steps so far corresponds to FIG.

Next, a second conductive layer is formed by a sputtering method, and the second conductive layer is selectively etched using a fourth photomask to form a first wiring 449, a second wiring 450, and a third wiring 451. .

Note that before the second conductive layer is formed by a sputtering method, reverse sputtering in which argon gas is introduced to generate plasma is performed, so that the surface of the gate insulating layer 443, the surfaces of the n ⁺ layers 455 and 457, and the contact hole 444 are formed. It is preferable to remove dust adhering to the bottom surface. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an atmosphere in which oxygen, hydrogen, N ₂ O, or the like is added to an argon atmosphere may be used. Alternatively, an atmosphere in which Cl ₂ , CF _4, or the like is added to an argon atmosphere may be used.

In the process of this embodiment mode, after the contact hole 444 is formed, the second conductive layer can be formed without forming another layer. Therefore, the bottom surface of the contact hole is exposed as compared with the second embodiment. Since the number of steps to be performed is small, the degree of freedom in selecting the material of the gate electrode material is expanded. This is because, in Embodiment 2, the oxide semiconductor layer is formed in contact with the gate electrode surface exposed in the contact hole 444, and thus the gate electrode material is not etched in the oxide semiconductor layer etching step. This is because it is necessary to select conditions or a material of the gate electrode.

Note that when the second conductive layer is etched, the n ⁺ layer and a part of the oxide semiconductor layer are further etched, so that the n ⁺ layers 446a, 446b, 448a, 448b, the first oxide semiconductor layer 445, A two-oxide semiconductor layer 447 is formed. By this etching, the thickness of the first oxide semiconductor layer 445 and the second oxide semiconductor layer 447 which overlap with the first gate electrode and the second gate electrode is reduced. Thereafter, the resist mask is removed. When the etching is completed, the first thin film transistor 460 and the second thin film transistor 461 are completed.

The first thin film transistor 460 includes a first gate electrode 441 and a first oxide semiconductor layer 445 which overlaps with the first gate electrode 441 with the gate insulating layer 443 interposed therebetween. The first wiring 449 includes a ground potential power supply line. (Ground power line). The power supply line having the ground potential may be a power supply line (negative power supply line) to which a negative voltage VDL is applied.

The second thin film transistor 461 includes a second gate electrode 442 and a second oxide semiconductor layer 447 which overlaps with the second gate electrode 442 with the gate insulating layer 443 provided therebetween, and the third wiring 451 has a positive voltage. A power supply line (positive power supply line) to which VDD is applied.

Further, the first oxide semiconductor layer 445 between the first wiring 449 is provided an ^{n +} layer 446a, a first oxide semiconductor layer 445 between the second wiring 450 is provided an ^{n +} layer 446b. Further, a second oxide semiconductor layer 447 is provided between the second wiring 450 is provided an ^{n +} layer 448a, a second oxide semiconductor layer 447 between the third wiring 451 is provided an ^{n +} layer 448b.

A cross-sectional view of the steps so far corresponds to FIG.

Next, heat treatment is performed at 200 ° C. to 600 ° C. in an air atmosphere or a nitrogen atmosphere. Note that there is no limitation on the timing of performing this heat treatment, and the heat treatment may be performed at any time after the oxide semiconductor layer is formed.

Next, a composition that is a material for the organic insulating layer is applied, and heat treatment is performed at 200 ° C. to 600 ° C. in an air atmosphere or a nitrogen atmosphere, so that the organic insulating layer 452 is formed. For the organic insulating layer 452, the material described in Embodiment 1 can be used as appropriate. Note that the heat treatment after the formation of the first oxide semiconductor layer 445 and the second oxide semiconductor layer 447 is not performed, and the heat treatment of the composition that is a material of the organic insulating layer is not performed in the oxide semiconductor layers 445 and 447. It may also serve as a heat treatment.

Next, a contact hole is formed by selectively etching the organic insulating layer 452 using a resist mask formed by a photolithography process using a fifth photomask. Thereafter, the resist mask is removed. Note that in the case where the organic insulating layer 452 is formed of a photosensitive resin, a resist is not applied on the organic insulating layer 452, and the organic insulating layer is exposed and developed using a fifth photomask, and contacted with the organic insulating layer 452. Holes can be formed.

Next, a third conductive layer is formed. Next, the third conductive layer is selectively etched using a resist mask formed by a photolithography process using a sixth photomask, so that connection wirings 453 that are electrically connected to the second wirings 450 are formed. A cross-sectional view of the steps so far corresponds to FIG.

Note that when the resist mask is removed by wet etching, heat treatment at 200 ° C. to 600 ° C. may be performed in an air atmosphere or a nitrogen atmosphere.

In a light-emitting display device using a light-emitting element, a pixel portion includes a plurality of thin film transistors, and a contact hole for directly connecting a gate electrode of a thin film transistor in the pixel portion to a source wiring or a drain wiring of another transistor is provided. Have. This contact portion can be formed using the same mask when the contact hole is formed in the gate insulating layer using the third photomask.

In a liquid crystal display device or electronic paper, when a contact hole reaching a gate wiring is formed in a terminal portion for connecting to an external terminal such as an FPC, a contact hole is formed in the gate insulating layer using a third photomask. When forming, the same mask can be used.

In addition, the process sequence mentioned above is an example, and is not specifically limited. For example, although the number of photomasks increases by one, etching may be performed separately using a photomask for etching the second conductive layer and a photomask for etching part of the n ⁺ layer and the oxide semiconductor layer.

By forming the organic insulating layer in contact with the oxide semiconductor layer through the above steps, a thin film transistor with high electrical characteristics can be manufactured.

(Embodiment 4)
In this embodiment, a manufacturing process of a thin film transistor in a pixel portion and a terminal portion that can be formed over the same substrate as the driver circuit described in Embodiment 1 or 2 will be described with reference to FIGS. .

5A, the substrate 400 described in Embodiment 1 can be used as appropriate as the substrate 100.

Next, after a conductive layer is formed over the entire surface of the substrate 100, unnecessary portions are removed by etching using a resist mask formed by performing a first photolithography step, and wirings and electrodes (a gate wiring including the gate electrode 101) are removed. The capacitor wiring 108 and the first terminal 121) are formed. At this time, etching is performed so that at least an end portion of the gate electrode 101 is tapered. Thereafter, the resist mask is removed. Note that a top view at this stage corresponds to FIG. An oxide semiconductor layer, a source electrode layer, a drain electrode layer, a pixel electrode, and a contact hole that are formed later are indicated by broken lines.

The gate wiring including the gate electrode 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion are formed using the materials of the first gate electrode 401 and the second gate electrode 402 described in Embodiment 1 as appropriate.

Next, a gate insulating layer 102 is formed over the entire surface of the gate electrode 101. The gate insulating layer 102 is appropriately formed using the gate insulating layer 403 described in Embodiment 1 and a thickness of 50 to 250 nm by a sputtering method or the like.

Note that before the oxide semiconductor layer is formed, it is preferable to perform reverse sputtering in which an argon gas is introduced to generate plasma to remove dust attached to the surface of the gate insulating layer. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an atmosphere in which oxygen, hydrogen, N ₂ O, or the like is added to an argon atmosphere may be used. Alternatively, an atmosphere in which Cl ₂ , CF _4, or the like is added to an argon atmosphere may be used.

Next, a first oxide semiconductor layer (a first In—Ga—Zn—O-based non-single-crystal layer in this embodiment) is formed over the gate insulating layer 102. After the plasma treatment, forming the first In—Ga—Zn—O-based non-single-crystal layer without being exposed to the air is useful in that dust and moisture are not attached to the interface between the gate insulating layer and the oxide semiconductor layer. .

Here, the distance between the substrate and the target is set using an oxide semiconductor target (In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1) containing In, Ga, and Zn having a diameter of 8 inches. Is formed at 170 mm, a pressure of 0.4 Pa, a direct current (DC) power supply of 0.5 kW, and in an argon or oxygen atmosphere. Note that a pulse direct current (DC) power source is preferable because dust can be reduced and the film thickness can be uniform. The thickness of the first In—Ga—Zn—O-based non-single-crystal layer is 5 nm to 200 nm. In this embodiment, the thickness of the first In—Ga—Zn—O-based non-single-crystal layer is 100 nm.

Next, a second oxide semiconductor layer (a second In—Ga—Zn—O-based non-single-crystal layer in this embodiment) is formed by a sputtering method without exposure to the air. Here, a target with In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 is used, and the formation conditions are a pressure of 0.4 Pa, a power of 500 W, a film formation temperature of room temperature, and argon. Sputtering is performed by introducing a gas flow rate of 40 sccm. In—Ga— containing crystal grains having a size of 1 nm to 10 nm immediately after film formation, despite the intentional use of a target of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1. A Zn—O-based non-single crystal layer may be formed. The target component ratio, film forming pressure (0.1 Pa to 2.0 Pa), power (250 W to 3000 W: 8 inches φ), temperature (room temperature to 100 ° C.), reactive sputtering formation conditions, and the like are adjusted as appropriate. Thus, it can be said that the presence or absence of crystal grains, the density of crystal grains, and the diameter size can be adjusted in the range of 1 nm to 10 nm. The thickness of the second In—Ga—Zn—O-based non-single-crystal layer is 5 nm to 20 nm. Of course, when crystal grains are included in the layer, the size of the included crystal grains does not exceed the thickness. In this embodiment, the thickness of the second In—Ga—Zn—O-based non-single-crystal layer is 5 nm.

The first In—Ga—Zn—O-based non-single-crystal layer is different from the formation conditions of the second In—Ga—Zn—O-based non-single-crystal layer. For example, the oxygen gas in the formation condition of the first In—Ga—Zn—O-based non-single-crystal layer is larger than the ratio of the oxygen gas flow rate to the argon gas flow rate in the formation condition of the second In—Ga—Zn—O-based non-single-crystal layer. The conditions are such that the ratio of flow rate is large. Specifically, the second In—Ga—Zn—O-based non-single-crystal layer is formed under a rare gas (argon or helium) atmosphere (or oxygen gas 10% or less, argon gas 90% or more), The formation condition of the first In—Ga—Zn—O-based non-single-crystal layer is an oxygen atmosphere (or a ratio of an oxygen gas flow rate to an argon gas flow rate of 1: 1).

Next, a second photolithography step is performed to form a resist mask, and the first In—Ga—Zn—O-based non-single crystal layer and the second In—Ga—Zn—O-based non-single crystal are formed using the resist mask. Etch the layer. Here, unnecessary portions are removed by wet etching using ITO07N (manufactured by Kanto Chemical Co., Inc.) as an etchant, and the oxide semiconductor layer 109, which is the first In—Ga—Zn—O-based non-single-crystal layer, and the second In— The oxide semiconductor layer 111 that is a Ga—Zn—O-based non-single-crystal layer is formed. Note that the etching here is not limited to wet etching, and dry etching may be used. A top view at this stage is illustrated in FIG. Note that a top view at this stage corresponds to FIG. A source electrode, a drain electrode, a pixel electrode, a contact hole, and the like to be formed later are indicated by broken lines. Thereafter, the resist mask is removed.

Next, a resist mask is formed by performing a third photolithography step, and unnecessary portions are removed by etching using the resist mask to form a contact hole reaching the wiring or electrode of the same material as the gate electrode. This contact hole is provided for direct connection to a conductive layer to be formed later. For example, a contact hole is formed when a thin film transistor in direct contact with a gate electrode and a source electrode or a drain electrode or a terminal electrically connected to a gate wiring in a terminal portion is formed in a driver circuit portion. Thereafter, the resist mask is removed.

Next, a conductive layer 132 formed using a metal material is formed over the oxide semiconductor layer 109 and the oxide semiconductor layer 111 by a sputtering method or a vacuum evaporation method. A cross-sectional view at this stage is illustrated in FIG.

As a material of the conductive layer 132, the material of the first wiring 409 to the third wiring 411 described in Embodiment 1 can be used as appropriate.

Next, a resist mask 131 is formed by performing a fourth photolithography process, and unnecessary portions are removed by etching using the resist mask, so that the source or drain electrodes 105a and 105b and the source or drain region function. The n ⁺ layers 104a and 104b, the connection electrode 120, and the second terminal 122 are formed. As an etching method at this time, wet etching or dry etching is used.

For example, when an aluminum layer or an aluminum alloy layer is used as the conductive layer 132, wet etching using a mixed solution of phosphoric acid, acetic acid, and nitric acid can be performed. Here, the conductive layer 132 formed of a titanium layer is etched by wet etching using ammonia overwater (hydrogen peroxide: ammonia: water = 5: 2: 2), and the source or drain electrodes 105a and 105b are etched. Form. Further, the oxide semiconductor layer 111 is etched to form n ⁺ layers 104a and 104b. In this etching step, part of the exposed region of the oxide semiconductor layer 109 is also etched, so that the oxide semiconductor layer 103 is formed. Therefore, the channel region of the oxide semiconductor layer 103 between the n ⁺ layers 104a and 104b is a thin region.

In FIG. 6A, since the source or drain electrodes 105a and 105b and the n ⁺ layers 104a and 104b are etched at once with an etching solution of ammonia-hydrogen, the source or drain electrodes 105a and 105b and n The ends of the ⁺ layers 104a and 104b are coincident and have a continuous structure. In addition, since wet etching is used, etching is performed isotropically, and the end portions of the source or drain electrodes 105 a and 105 b are set back from the resist mask 131. Thereafter, the resist mask is removed. Through the above steps, the thin film transistor 170 using the oxide semiconductor layer 103 as a channel formation region can be manufactured. A cross-sectional view at this stage is illustrated in FIG. Note that a top view at this stage corresponds to FIG. Pixel electrodes, contact holes, and the like that are formed later are indicated by broken lines.

Further, oxygen radical treatment may be performed on the exposed channel formation region of the oxide semiconductor layer 103. By performing the oxygen radical treatment, the thin film transistor can be normally off. In addition, by performing radical treatment, damage due to etching of the oxide semiconductor layer 103 can be recovered. The radical treatment is preferably performed in an O ₂ , N ₂ O, preferably N ₂ , He, Ar atmosphere containing oxygen. It may also be carried out in an atmosphere obtained by adding _Cl 2, CF ₄ to the atmosphere. Note that the radical treatment is preferably performed without bias. In addition, due to the radical treatment, the end portions of the source electrode 105 a, the drain electrode 105 b, the connection electrode 120, and the second terminal 122 are curved.

Note that in the case where the radical treatment is not performed, as illustrated in FIG. 6A, the end portions of the source electrode 105a, the drain electrode 105b, the connection electrode 120, and the second terminal 122 are not curved and are angular. .

In the fourth photolithography process, the second terminal 122 made of the same material as the source or drain electrodes 105a and 105b is left in the terminal portion. Note that the second terminal 122 is electrically connected to a source wiring (a source wiring including the source or drain electrodes 105a and 105b).

In the terminal portion, the connection electrode 120 is directly connected to the first terminal 121 in the terminal portion through a contact hole formed in the gate insulating layer. Although not shown here, the source wiring or drain wiring of the thin film transistor of the driver circuit and the gate electrode are directly connected through the same process as described above.

Next, it is preferable to perform heat treatment at 200 ° C. to 600 ° C., typically 300 ° C. to 500 ° C. Here, heat treatment is performed in a furnace at 350 ° C. for 1 hour in a nitrogen atmosphere. By this heat treatment, rearrangement at the atomic level of the In—Ga—Zn—O-based non-single-crystal layer is performed. The heat treatment (including optical annealing) is important because distortion that hinders carrier movement is released by this heat treatment. Note that the timing of performing the heat treatment is not particularly limited as long as it is after the formation of the second In—Ga—Zn—O-based non-single-crystal layer, and may be performed after the formation of the organic insulating layer to be performed later.

Next, an organic insulating layer 107 that covers the oxide semiconductor layer 103 is formed. The organic insulating layer 107 can be formed using any of the materials listed for the organic insulating layer 452 described in Embodiment 1 as appropriate.

Next, a fifth photolithography step is performed to form a resist mask, and the organic insulating layer 107 is etched using the resist mask to form a contact hole 125 reaching the drain electrode 105b. Further, a contact hole 127 reaching the second terminal 122 and a contact hole 126 reaching the connection electrode 120 are also formed by etching here. Further, by this etching, an opening 124 for forming the dielectric in the capacitor portion as the gate insulating layer 102 is also formed. Thereafter, the resist mask is removed. A cross-sectional view at this stage is illustrated in FIG.

Next, a transparent conductive layer is formed over the organic insulating layer 107. As a material for the transparent conductive layer, indium oxide (In ₂ O ₃ ), indium tin oxide alloy (In ₂ O ₃ —SnO ₂ , abbreviated as ITO) or the like is formed by a sputtering method, a vacuum evaporation method, or the like. . Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, since etching of ITO is likely to generate a residue, an indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) may be used to improve etching processability.

Next, a sixth photolithography step is performed to form a resist mask, and unnecessary portions are removed by etching using the resist mask, so that the pixel electrode 110 is formed.

In the sixth photolithography step, a storage capacitor is formed by the capacitor wiring 108 and the pixel electrode 110 using the gate insulating layer 102 and the organic insulating layer 107 in the capacitor portion as dielectrics.

Further, in the sixth photolithography process, the connection electrodes 120 and the second terminals 122 are covered with a resist mask, and the transparent conductive layers 128 and 129 formed in the terminal portions are left. The transparent conductive layers 128 and 129 serve as electrodes or wirings used for connection with the FPC. The transparent conductive layer 128 formed on the connection electrode 120 directly connected to the first terminal 121 serves as a connection terminal electrode that functions as an input terminal of the gate wiring. The transparent conductive layer 129 formed on the second terminal 122 is a connection terminal electrode that functions as an input terminal of the source wiring.

Next, the resist mask is removed. A cross-sectional view at this stage is illustrated in FIG. Note that a top view at this stage corresponds to FIG. Note that when the resist mask is removed by wet etching, heat treatment at 200 ° C. to 600 ° C. may be performed in an air atmosphere or a nitrogen atmosphere.

11A1 and 11A2 are a top view and a cross-sectional view of the gate wiring terminal portion at this stage, respectively. FIG. 11A1 corresponds to a cross-sectional view taken along line C1-C2 in FIG. In FIG. 11A1, the transparent conductive layer 155 formed over the organic insulating layer 107 is a connection terminal electrode that functions as an input terminal. In FIG. 11A1, in the gate wiring terminal portion, a first terminal 151 formed of the same material as the gate wiring and a connection electrode 153 formed of the same material as the source wiring are provided with the gate insulating layer 102 interposed therebetween. They overlap and are in direct contact with each other. Further, the connection electrode 153 and the transparent conductive layer 155 are in direct contact with each other in a contact hole provided in the organic insulating layer 107.

11B1 and 11B2 are a top view and a cross-sectional view of the source wiring terminal portion, respectively. FIG. 11B1 corresponds to a cross-sectional view taken along line D1-D2 in FIG. In FIG. 11B1, a transparent conductive layer 155 formed over the organic insulating layer 107 is a connection terminal electrode that functions as an input terminal. In FIG. 11B1, in the source wiring terminal portion, an electrode 156 formed of the same material as the gate wiring is provided below the second terminal 150 electrically connected to the source wiring with the gate insulating layer 102 interposed therebetween. Overlap. The electrode 156 formed of the same material as the gate wiring is not electrically connected to the second terminal 150. If the electrode 156 is set to a potential different from that of the second terminal 150, for example, floating, GND, 0V, or the like. In addition, a capacitance for noise countermeasures or a capacitance for static electricity countermeasures can be formed. The second terminal 150 is directly connected to the transparent conductive layer 155 in a contact hole provided in the organic insulating layer 107.

A plurality of gate wirings, source wirings, and capacitor wirings are provided depending on the pixel density. In the terminal portion, a plurality of first terminals having the same potential as the gate wiring, second terminals having the same potential as the source wiring, third terminals having the same potential as the capacitor wiring, and the like are arranged. Any number of terminals may be provided, and the practitioner may determine the number appropriately.

In this manner, the pixel thin film transistor portion including the thin film transistor 170 which is a bottom-gate n-channel thin film transistor and the storage capacitor can be completed by using six photomasks through six photolithography processes. Then, by arranging these in a matrix corresponding to each pixel to form a pixel portion, one substrate for manufacturing an active matrix display device can be obtained. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

In the case of manufacturing an active matrix liquid crystal display device, a liquid crystal layer is provided between an active matrix substrate and a counter substrate provided with a counter electrode, and the active matrix substrate and the counter substrate are fixed. Note that a common electrode electrically connected to the counter electrode provided on the counter substrate is provided over the active matrix substrate, and a fourth terminal electrically connected to the common electrode is provided in the terminal portion. The fourth terminal is a terminal for setting the common electrode to a fixed potential such as GND or 0V.

Further, this embodiment is not limited to the pixel configuration in FIG. 10, and FIG. 12 shows an example of a top view different from FIG. In FIG. 12, the capacitor wiring is not provided, and the storage capacitor is formed by overlapping the pixel electrode 110 and the gate wiring of the adjacent pixel via the gate insulating layer. In this case, the capacitor wiring and the capacitor wiring are connected to each other. Three terminals can be omitted. Further, since a capacitor can be formed without providing a recess in the display region, flatness is improved and uneven alignment of liquid crystal can be reduced. In FIG. 12, the same parts as those in FIG. 12 will be described using the same reference numerals.

In an active matrix liquid crystal display device, a display pattern is formed on a screen of a liquid crystal display device by driving pixel electrodes arranged in a matrix. Specifically, by applying a voltage between the selected pixel electrode and the counter electrode corresponding to the pixel electrode, optical modulation of the liquid crystal layer disposed between the pixel electrode and the counter electrode is performed. The observer recognizes transmission and non-transmission of light by optical modulation as a display pattern.

In moving image display of a liquid crystal display device, there is a problem that an afterimage is generated or a moving image is blurred because of a slow response of liquid crystal molecules themselves. In order to improve the moving image characteristics of a liquid crystal display device, there is a so-called black insertion driving technique in which black display is performed every other frame.

There is also a so-called double speed drive technique that improves the moving image characteristics by setting the vertical synchronization frequency to 1.5 times the normal frequency, preferably 2 times or more.

Moreover, in order to improve the moving image characteristics of the liquid crystal display device, a surface light source is configured using a plurality of LED (light emitting diode) light sources or a plurality of EL light sources as a backlight, and each light source constituting the surface light source is independent. There is also a driving technique that performs intermittent lighting driving within one frame period. As the surface light source, three or more kinds of LEDs may be used, or white light emitting LEDs may be used. Since a plurality of LEDs can be controlled independently, the light emission timings of the LEDs can be synchronized with the optical modulation switching timing of the liquid crystal layer. Since this driving technique can partially turn off the LED, an effect of reducing power consumption can be achieved particularly in the case of video display in which the ratio of the black display area occupying one screen is large.

By combining these driving techniques, the display characteristics such as the moving picture characteristics of the liquid crystal display device can be improved as compared with the related art.

In the n-channel transistor obtained in this embodiment, an oxide semiconductor layer, typically an In—Ga—Zn—O-based non-single-crystal layer is used for a channel formation region. Since the organic resin layer is in contact with each other, it has excellent electrical characteristics, and thus these driving techniques can be combined.

In the case of manufacturing a light-emitting display device, one electrode (also referred to as a cathode) of an organic light-emitting element is set to a low power supply potential, for example, GND, 0 V, and the like. , A fourth terminal for setting to 0V or the like is provided. In the case of manufacturing a light-emitting display device, a power supply line is provided in addition to a source wiring and a gate wiring. Accordingly, the terminal portion is provided with a fifth terminal that is electrically connected to the power supply line.

By forming the gate line driver circuit or the source line driver circuit with a thin film transistor using an oxide semiconductor, manufacturing cost is reduced. A display device can be provided in which the number of contact holes is reduced by directly connecting a gate electrode of a thin film transistor used for a driver circuit to a source wiring or a drain wiring, and the area occupied by the driver circuit can be reduced.

Therefore, according to this embodiment, a display device with improved image quality can be provided at low cost.

This embodiment mode can be freely combined with any of Embodiment Modes 1 to 3.

(Embodiment 5)
In this embodiment, a manufacturing process of a display device including a thin film transistor which can be manufactured with fewer photomasks than in Embodiment 4 will be described with reference to FIGS.

In FIG. 31A, after a conductive layer is formed over the entire surface of the substrate 100, a resist mask formed by performing a first photolithography process is used, unnecessary portions are removed by etching, and wirings and electrodes ( A gate wiring including the gate electrode 101, a capacitor wiring 108, and a first terminal 121) are formed. Thereafter, the resist mask is removed. A top view at this stage corresponds to FIG. An oxide semiconductor layer, a source electrode layer, a drain electrode layer, a pixel electrode, and a contact hole that are formed later are indicated by broken lines.

The gate wiring including the gate electrode 101, the capacitor wiring 108, and the first terminal 121 of the terminal portion are formed using the materials of the first gate electrode 401 and the second gate electrode 402 described in Embodiment 1 as appropriate.

Next, a gate insulating layer 102 is formed over the entire surface of the gate electrode 101. The gate insulating layer 102 is formed by a sputtering method or the like with a thickness of 50 to 250 nm.

Note that before the oxide semiconductor layer is formed, it is preferable to perform reverse sputtering in which an argon gas is introduced to generate plasma to remove dust attached to the surface of the gate insulating layer. Note that nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an atmosphere in which oxygen, hydrogen, N ₂ O, or the like is added to an argon atmosphere may be used. Alternatively, an atmosphere in which Cl ₂ , CF _4, or the like is added to an argon atmosphere may be used.

Next, a first oxide semiconductor layer 109 (a first In—Ga—Zn—O-based non-single-crystal layer in this embodiment) is formed over the gate insulating layer 102. After the plasma treatment, forming the first In—Ga—Zn—O-based non-single-crystal layer without being exposed to the air is useful in that dust and moisture are not attached to the interface between the gate insulating layer and the first oxide semiconductor layer. It is. Here, as in Embodiment 4, the first In—Ga—Zn—O-based non-single-crystal layer is formed.

Next, the second oxide semiconductor layer 111 (second In—Ga—Zn—O-based non-single-crystal layer in this embodiment) is formed by a sputtering method without being exposed to the air. Here, a target with In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1 is used, and the formation condition is the second In—Ga—Zn—O-based non-single-crystal layer as in Embodiment Mode 4. Form.

Note that the first In—Ga—Zn—O-based non-single-crystal layer is different from the formation conditions of the second In—Ga—Zn—O-based non-single-crystal layer.

Next, a conductive layer 132 formed using a metal material is formed over the first oxide semiconductor layer 109 and the second oxide semiconductor layer 111 by a sputtering method or a vacuum evaporation method. Here, it is formed in the same manner as in Embodiment Mode 4. A top view at this stage is illustrated in FIG.

Next, a second photolithography process is performed to form a resist mask 133. In this embodiment, an example of performing exposure using a multi-tone (high-tone) mask in order to form the resist mask 133 is described.

Here, exposure using the multi-tone mask 59 will be described with reference to FIG.

A multi-tone mask is a mask that can perform three exposure levels on an exposed portion, an intermediate exposed portion, and an unexposed portion, and is an exposure mask in which transmitted light has a plurality of intensities. By a single exposure and development process, a resist mask having a plurality of (typically two kinds) of thickness regions can be formed. For this reason, the number of exposure masks can be reduced by using a multi-tone mask.

Typical examples of the multi-tone mask include a gray-tone mask 59a as shown in FIG. 37A and a half-tone mask 59b as shown in FIG.

As shown in FIG. 37 (A), the gray tone mask 59a is composed of a translucent substrate 63, a light shielding portion 64 and a diffraction grating 65 formed thereon. In the light shielding portion 64, the light transmittance is 0%. On the other hand, the diffraction grating 65 can control the light transmittance by setting the interval between the light transmitting portions such as slits, dots, and meshes to be equal to or less than the resolution limit of the light used for exposure. Note that the diffraction grating 65 may be a periodic slit, dot, or mesh, or an aperiodic slit, dot, or mesh.

As the translucent substrate 63, a translucent substrate such as quartz can be used. The light shielding portion 64 and the diffraction grating 65 can be formed using a light shielding material that absorbs light such as chromium or chromium oxide.

When the gray-tone mask 59a is irradiated with exposure light, as shown in FIG. 30B, the light transmittance 66 is 0% in the light shielding portion 64, and the light shielding portion 64 and the diffraction grating 65 are not provided. In the region, the light transmittance 66 is 100%. Further, the diffraction grating 65 can be adjusted within a range of 10 to 70%. The light transmittance of the diffraction grating 65 can be adjusted by adjusting the spacing and pitch of slits, dots, or meshes of the diffraction grating.

As shown in FIG. 37C, the halftone mask 59b is composed of a translucent substrate 63, a semi-transmissive portion 67 and a light-shielding portion 68 formed thereon. For the semi-transmissive portion 167, MoSiN, MoSi, MoSiO, MoSiON, CrSi, or the like can be used. The light shielding portion 168 can be formed using a light shielding material that absorbs light, such as chromium or chromium oxide.

When the halftone mask 59b is irradiated with exposure light, as shown in FIG. 37D, the light transmittance 69 is 0% in the light shielding portion 68, and the light shielding portion 68 and the semi-transmissive portion 167 are provided. In the absence region, the light transmittance 69 is 100%. Moreover, in the semi-transmissive part 67, it can adjust in 10 to 70% of range. The light transmittance in the semi-transmissive portion 67 can be adjusted by adjusting the material of the semi-transmissive portion 67.

By developing after exposure using a multi-tone mask, a resist mask 133 having regions with different thicknesses can be formed as shown in FIG.

Next, a first etching step is performed using the resist mask 133, and the first oxide semiconductor layer 109, the second oxide semiconductor layer 111, and the conductive layer 132 are etched and processed into an island shape. As a result, the first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer 136 can be formed (see FIG. 31C). Note that a top view at this stage corresponds to FIG. A source electrode layer, a drain electrode layer, a pixel electrode, and a contact hole that are formed later are indicated by broken lines.

Next, the resist mask 133 is ashed. As a result, the area of the resist mask is reduced and the thickness is reduced. At this time, the resist mask in a thin region (a region overlapping with part of the gate electrode 101) is removed, so that a separated resist mask 131 can be formed (see FIG. 32A).

The first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer 136 are etched by the second etching process using the resist mask 131, and the oxide semiconductor layer 103, n ⁺ that is the source region and the drain region, respectively ^. Layers 104a and 104b and source or drain electrodes 105a and 105b are formed. Note that only part of the oxide semiconductor layer 103 is etched to be an oxide semiconductor layer having a groove (a depressed portion) and part of the oxide semiconductor layer 103 is exposed by being etched.

In the present embodiment, the first etching step and the second etching step are performed using wet etching. However, the first etching step and the second etching step may be performed. One of the first etching step and the second etching step may be dry etching and the other may be wet etching.

When the first oxide semiconductor layer 109, the second oxide semiconductor layer 111, and the conductive layer 132 are wet-etched in the first etching step, the first oxide semiconductor layer 109, the second oxide semiconductor layer 111, the conductive layer 132, etc. Therefore, the edges of the resist mask 133 and the edges of the first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer 136 do not coincide with each other, and the edges of the resist mask 133 recede. The shape has a curvature. As a result, disconnection of the film formed thereon and poor coverage can be prevented. Further, in wet etching, it is easy to obtain a high selection ratio between the first oxide semiconductor film 109 and the gate insulating layer 102, and an unintended thinning of the gate insulating layer 102 can be prevented.

Similarly, when the first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer 136 are wet-etched in the second etching step, the first oxide semiconductor layer 134, the second oxide semiconductor layer 135, and the conductive layer Since 136 is etched isotropically, the end portion of the resist mask 131 and the end portion of the recessed portion of the oxide semiconductor layer 103, the n ⁺ layers 104a and 104b, and the source or drain electrodes 105a and 105b do not coincide with each other. Retreat, and its end becomes a shape with curvature. Thereafter, the resist mask 131 is removed. As a result, disconnection of the film formed thereon and poor coverage can be prevented. In addition, in wet etching, it is easy to increase the selection ratio of the conductive layer 136 or the second oxide semiconductor layer 135 and the gate insulating layer 102, and an unintended thinning of the gate insulating layer 102 can be prevented.

In addition, the etchant after the wet etching is removed by cleaning together with the etched material. The waste solution of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively used and costs can be reduced.

Further, oxygen radical treatment may be performed on the exposed channel formation region of the oxide semiconductor layer 103. By performing the oxygen radical treatment, the thin film transistor can be normally off. In addition, by performing radical treatment, damage due to etching of the oxide semiconductor layer 103 can be recovered. In addition, due to the plasma treatment, the end portions of the source electrode 105a, the drain electrode 105b, and the second terminal 122 are curved.

Next, it is preferable to perform heat treatment at 200 ° C. to 600 ° C., typically 300 ° C. to 500 ° C. Note that the timing for performing the heat treatment is not particularly limited as long as it is after the formation of the second In—Ga—Zn—O-based non-single-crystal layer, and for example, the heat treatment may be performed after the pixel electrode is formed.

Through the above steps, the thin film transistor 170 using the oxide semiconductor layer 103 as a channel formation region can be manufactured. A cross-sectional view at this stage is illustrated in FIG. Note that a top view at this stage corresponds to FIG. Pixel electrodes and contact holes to be formed later are indicated by broken lines.

In the second etching step, the same material as the terminal layer 139, which is the same material as the oxide semiconductor layer 103, the terminal layer 140, which is the same material as the n ⁺ layers 104a and 104b, and the source or drain electrodes 105a and 105b is used. The second terminal 122 is left in the terminal portion. Note that the second terminal 122 is electrically connected to a source wiring (a source wiring including the source or drain electrodes 105a and 105b).

When a resist mask having a plurality of (typically two kinds) of thickness regions formed using a multi-tone mask is used, the number of resist masks can be reduced, so that the process can be simplified and costs can be reduced.

Next, an organic insulating layer 107 that covers the oxide semiconductor layer 103 is formed. The organic insulating layer 107 can be formed using any of the materials listed for the organic insulating layer 452 described in Embodiment 1 as appropriate.

Next, a third photolithography step is performed to form a resist mask, and the organic insulating layer 107 is etched using the resist mask to form a contact hole 125 reaching the drain electrode 105b. Further, a contact hole 127 reaching the second terminal 122 and a contact hole 126 reaching the second terminal 121 are also formed. Further, by this etching, an opening 124 for forming the dielectric in the capacitor portion as the gate insulating layer 102 is also formed. Thereafter, the resist mask is removed. A cross-sectional view at this stage is illustrated in FIG.

Next, a transparent conductive layer is formed on the organic insulating layer 107 as in the fourth embodiment.

Next, a fourth photolithography step is performed to form a resist mask, and unnecessary portions are removed by etching using the resist mask, so that the pixel electrode 110 is formed.

In the fourth photolithography process, a storage capacitor is formed by the capacitor wiring 108 and the pixel electrode 110 using the gate insulating layer 102 and the organic insulating layer 107 in the capacitor portion as dielectrics.

Further, in the fourth photolithography process, the first terminal 121 and the second terminal 122 are covered with a resist mask, and the transparent conductive layers 128 and 129 formed in the terminal portion are left. The transparent conductive layers 128 and 129 serve as electrodes or wirings used for connection with the FPC. The transparent conductive layer 128 formed on the first terminal 121 directly connected to the first terminal 121 serves as a connection terminal electrode that functions as an input terminal of the gate wiring. The transparent conductive layer 129 formed on the second terminal 122 is a connection terminal electrode that functions as an input terminal of the source wiring.

Next, the resist mask is removed. A cross-sectional view at this stage is illustrated in FIG. Note that a top view at this stage corresponds to FIG. Note that when the resist mask is removed by wet etching, heat treatment at 200 ° C. to 600 ° C. may be performed in an air atmosphere or a nitrogen atmosphere.

In this manner, the pixel thin film transistor portion and the storage capacitor having the thin film transistor 170 which is a bottom-gate n-channel thin film transistor can be completed by using four photomasks through four photolithography steps. An active matrix substrate can be manufactured by arranging these in a matrix corresponding to each pixel to form a pixel portion.

(Embodiment 6)
In this embodiment mode, structures applicable to Embodiment Modes 1 to 3 are described with reference to FIGS.

In this embodiment mode, the wiring 410 of the first thin film transistor 430 and the gate electrode 402 of the second thin film transistor 431 are connected by a connection wiring 462. The connection wiring 462 connects the wiring 410 of the first thin film transistor 430 and the gate electrode 402 of the second thin film transistor 431 through a contact hole formed in the organic insulating layer 452. Therefore, the connection wiring 462 can be formed at the same time as the pixel electrode 110 formed in the pixel portion described in Embodiments 4 and 5. In addition, since a photolithography process for forming a contact hole in the gate insulating layer 403 is not necessary, the photolithography process can be reduced once. For this reason, it is possible to reduce the number of steps for manufacturing the active matrix substrate, so that the cost can be reduced.

(Embodiment 7)
Here, FIG. 30 illustrates an example of a display device including a thin film transistor having a structure in which a wiring and an oxide semiconductor layer are in contact with each other in Embodiment 1.

FIG. 30 shows a cross-sectional structure of the inverter circuit of the drive circuit. Note that the first thin film transistor 480 and the second thin film transistor 481 illustrated in FIGS. 30A and 30B are inverted staggered thin film transistors, in which a first wiring 409 and a second wiring 410 are formed in contact with the first oxide semiconductor layer 405, and the second oxide film is formed. In this example, the second wiring 410 and the third wiring 411 are formed in contact with the physical semiconductor layer 407.

In the first thin film transistor 480 and the second thin film transistor 481, the contact region between the first oxide semiconductor layer 405 and the first wiring 409 and the second wiring 410, and the second oxide semiconductor layer 407, the second wiring 410, the second wiring The contact area with the three wirings 411 is preferably modified by plasma treatment. In this embodiment, plasma treatment is performed on the oxide semiconductor layer (In—Ga—Zn—O-based non-single-crystal layer in this embodiment) in an argon atmosphere before the formation of the conductive layer to be a wiring.

In the plasma treatment, nitrogen, helium, or the like may be used instead of the argon atmosphere. Alternatively, an atmosphere in which oxygen, hydrogen, N ₂ O, or the like is added to an argon atmosphere may be used. Alternatively, an atmosphere in which Cl ₂ , CF _4, or the like is added to an argon atmosphere may be used.

In this embodiment, wet etching is performed using ammonia overwater (hydrogen peroxide: ammonia: water = 5: 2: 2) using a titanium layer for the first wiring 409, the second wiring 410, and the third wiring 411. I do. In this etching step, part of the exposed region of the oxide semiconductor layer that is an In—Ga—Zn—O-based non-single-crystal layer is also etched, so that a first oxide semiconductor layer 405 and a second oxide semiconductor layer 407 are formed. Therefore, the channel region of the first oxide semiconductor layer 405 between the first wiring 409 and the second wiring 410 is a thin region. Similarly, the channel region of the second oxide semiconductor layer 407 between the second wiring 410 and the third wiring 411 is a thin region.

By forming a conductive layer in contact with the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407 modified by the plasma treatment, and forming a first wiring 409, a second wiring 410, and a third wiring 411, In addition, contact resistance between the first oxide semiconductor layer 405 and the second oxide semiconductor layer 407 and the first wiring 409, the second wiring 410, and the third wiring 411 can be reduced.

Through the above process, a highly reliable display device can be manufactured.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 8)
In this embodiment, the shape of an organic insulating layer applicable to Embodiment 2 is described with reference to FIGS.

As shown in FIG. 39, an organic insulating layer 161 is formed over the gate insulating layer 102, the first wiring 105a, the second wiring 105b, and the oxide semiconductor layer 103 of the thin film transistor 170 manufactured in Embodiment 2, and the organic insulating layer The layer 161 is characterized in that it does not cover part of the second wiring 105b. The pixel electrode 163 is formed over the second wiring 105b and the gate insulating layer 102.

Further, the transparent conductive layer 165 formed in the terminal portion is formed over the connection electrode 120 and the gate insulating layer 102. The transparent conductive layer 164 formed in the terminal portion is formed on the second terminal 122 and the gate insulating layer 102.

Through the above, a display device with improved image quality can be manufactured.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 9)
In this embodiment, a structure of a counter substrate of a liquid crystal display device which is one embodiment of the display device is described with reference to FIGS.

40 is a cross-sectional view of the pixel portion of the liquid crystal display device, and FIG. 41 is a top view of the pixel portion. A cross-sectional view taken along line AB of FIG. 41 corresponds to FIG.

A thin film transistor 170 is formed over the substrate 100. In addition, the organic insulating layer 107 is formed over the thin film transistor 170. In the contact hole of the organic insulating layer 107, the pixel electrode 110 connected to the wiring of the thin film transistor 170 is formed. An alignment film 171 is formed on the pixel electrode 110 and the organic insulating layer 107.

A light shielding layer 173 that covers the thin film transistor 170 is formed over the counter substrate 172. A colored layer 174 that covers the light shielding layer 173 and the counter substrate 172 is formed. An auxiliary electrode 176 is formed on the coloring layer 174. A counter electrode 175 that covers the light shielding layer 173, the colored layer 174, and the auxiliary electrode 176 is formed. An alignment film 177 is formed on the counter electrode 175.

Although not shown, the substrate 100 and the counter substrate 172 are fixed with a sealing material. Further, liquid crystal 178 is filled inside the substrate 100, the counter substrate 172, and the sealant.

The counter electrode 175 is formed using the material for the pixel electrode 110 described in Embodiment 4 as appropriate.

The colored layer 174 is formed by appropriately using an insulating layer that preferentially transmits light in the red wavelength range, light in the blue wavelength range, and light in the green wavelength range. The colored layer 174 functions as a color filter.

The auxiliary electrode 176 is an auxiliary electrode provided for the purpose of reducing the resistance value of the counter electrode 175. For this reason, the auxiliary electrode 176 may be formed using a material having high contact with the counter electrode 175 and having a lower resistivity than the counter electrode 175. Typically, it can be formed using a simple substance such as aluminum, titanium, copper, tantalum, tungsten, and molybdenum. Alternatively, an alloy of the above metal and scandium, niobium, copper, or silicon can be used.

In this embodiment mode, the auxiliary electrode 176 is formed in contact with the counter electrode 175. For this reason, since the resistance value of the counter electrode 175 can be reduced, the thickness of the counter electrode 175 can be reduced. In addition, a common line for applying a potential to the counter electrode 175 is not formed in the entire periphery of the substrate 100, and the common electrode, the auxiliary electrode 176, and the conductive particles may be connected to each other at the common terminal portion. The frame of the device can be narrowed.

(Embodiment 10)
In this embodiment, an example in which at least part of a driver circuit and a thin film transistor provided in a pixel portion are formed over the same substrate in the display device will be described below.

The thin film transistor provided in the pixel portion is formed in accordance with Embodiment 4 or Embodiment 5. In addition, since the thin film transistor described in Embodiment 4 or 5 is an n-channel TFT, a part of the driver circuit that can be formed using the n-channel TFT in the driver circuit is the same as the thin film transistor in the pixel portion. Form on the substrate.

An example of a block diagram of an active matrix liquid crystal display device is shown in FIG. A display device illustrated in FIG. 14A includes a pixel portion 5301 having a plurality of pixels each provided with a display element over a substrate 5300, a scan line driver circuit 5302 for selecting each pixel, and a video signal to the selected pixel. And a signal line driver circuit 5303 for controlling input.

The pixel portion 5301 is connected to the signal line driver circuit 5303 by a plurality of signal lines S1 to Sm (not shown) arranged extending from the signal line driver circuit 5303 in the column direction. A plurality of scanning lines G1 to Gn (not shown) arranged in the direction are connected to the scanning line driving circuit 5302 and arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. A plurality of pixels (not shown). Each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn).

Further, the thin film transistor described in Embodiment 4 or 5 is an n-channel TFT, and a signal line driver circuit including the n-channel TFT is described with reference to FIGS.

The signal line driver circuit illustrated in FIG. 15 includes a driver IC 5601, switch groups 5602-1 to 5602 -M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 5621-1 to 5621 -M. Each of the switch groups 5602-1 to 5602 -M includes a first thin film transistor 5603 a, a second thin film transistor 5603 b, and a third thin film transistor 5603 c.

The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the wirings 5621-1 to 5621-M. Each of the switch groups 5602-1 to 5602 -M includes wirings 5621-1 to 5621 -M corresponding to the first wiring 5611, the second wiring 5612, the third wiring 5613, and the switch groups 5602-1 to 5602 -M, respectively. Connected to. Each of the wirings 5621-1 to 5621 -M is connected to three signal lines through the first thin film transistor 5603 a, the second thin film transistor 5603 b, and the third thin film transistor 5603 c. For example, the wiring 5621-J (any one of the wirings 5621-1 to 5621-M) in the J column includes the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c included in the switch group 5602-J. To the signal line Sj-1, the signal line Sj, and the signal line Sj + 1.

Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

Note that the driver IC 5601 is preferably formed over a single crystal substrate. Further, the switch groups 5602-1 to 5602 -M are preferably formed over the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602-1 to 5602 -M are preferably connected via an FPC or the like.

Next, operation of the signal line driver circuit illustrated in FIG. 15 is described with reference to a timing chart of FIG. Note that the timing chart of FIG. 16 shows the timing chart when the i-th scanning line Gi is selected. Further, the selection period of the i-th scanning line Gi is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driver circuit in FIG. 15 operates in the same manner as in FIG. 16 even when a scan line in another row is selected.

Note that in the timing chart of FIG. 16, the wiring 5621-J in the J-th column is connected to the signal line Sj-1, the signal line Sj, and the signal line Sj + 1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. It shows the case of connection.

Note that the timing chart in FIG. 16 shows the timing at which the i-th scanning line Gi is selected, the on / off timing 5703a of the first thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, and the third thin film transistor 5603c. The ON / OFF timing 5703c and the signal 5721-J input to the wiring 5621-J in the J-th column are shown.

Note that different video signals are input to the wirings 5621-1 to 5621-M in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. For example, a video signal input to the wiring 5621-J in the first sub selection period T1 is input to the signal line Sj-1, and a video signal input to the wiring 5621-J in the second sub selection period T2 is the signal line Sj. And the video signal input to the wiring 5621-J in the third sub-selection period T3 is input to the signal line Sj + 1. Further, in the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, video signals input to the wiring 5621-J are respectively represented as Data-j-1, Data-j, and Data-j + 1. To do.

As shown in FIG. 16, in the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data-j-1 input to the wiring 5621-J is input to the signal line Sj-1 through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data-j input to the wiring 5621-J is input to the signal line Sj through the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data-j + 1 input to the wiring 5621-J is input to the signal line Sj + 1 through the third thin film transistor 5603c.

From the above, the signal line driver circuit in FIG. 15 can divide one gate selection period into three to input video signals from one wiring 5621_J to three signal lines during one gate selection period. it can. Therefore, the signal line driver circuit in FIG. 15 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1/3 of the number of signal lines. When the number of connections is about ３, the signal line driver circuit in FIG. 15 can improve reliability, yield, and the like.

As shown in FIG. 15, if one gate selection period is divided into a plurality of sub-selection periods and a video signal can be input from a certain wiring to each of a plurality of signal lines in each of the plurality of sub-selection periods, The arrangement and number of thin film transistors and the driving method are not limited.

For example, when video signals are input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, a thin film transistor and a wiring for controlling the thin film transistor may be added. However, if one gate selection period is divided into four or more sub selection periods, one sub selection period is shortened. Therefore, it is desirable that one gate selection period is divided into two or three sub selection periods.

As another example, as shown in the timing chart of FIG. 17, one selection period may be divided into a precharge period Tp, a first sub selection period T1, a second sub selection period T2, and a third sub selection period T3. Good. Further, the timing chart of FIG. 17 shows the timing at which the i-th scanning line Gi is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, and the third thin film transistor 5603c. ON / OFF timing 5803c and signal 5821-J input to the wiring 5621-J in the J-th column are shown. As shown in FIG. 17, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on in the precharge period Tp. At this time, the precharge voltage Vp input to the wiring 5621-J is input to the signal line Sj-1, the signal line Sj, and the signal line Sj + 1 through the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. The In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data-j-1 input to the wiring 5621-J is input to the signal line Sj-1 through the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data-j input to the wiring 5621-J is input to the signal line Sj through the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data-j + 1 input to the wiring 5621-J is input to the signal line Sj + 1 through the third thin film transistor 5603c.

From the above, the signal line driver circuit in FIG. 15 to which the timing chart in FIG. 17 is applied can precharge the signal line by providing a precharge period before the sub selection period. Writing can be performed at high speed. Note that in FIG. 17, components similar to those in FIG. 16 are denoted by common reference numerals, and detailed description of the same portions or portions having similar functions is omitted.

A structure of the scan line driver circuit will be described. The scan line driver circuit includes a shift register and a buffer. In some cases, a level shifter may be provided. In the scan line driver circuit, when a clock signal (CLK) and a start pulse signal (SP) are input to the shift register, a selection signal is generated. The generated selection signal is buffered and amplified in the buffer and supplied to the corresponding scanning line. A gate electrode of a transistor of a pixel for one line is connected to the scanning line. Since the transistors of pixels for one line must be turned on all at once, a buffer that can flow a large current is used.

One mode of a shift register used for part of the scan line driver circuit is described with reference to FIGS.

FIG. 18 shows a circuit configuration of the shift register. The shift register illustrated in FIG. 18 includes a plurality of flip-flops, flip-flops 5701-1 to 5701-n. In addition, the first clock signal, the second clock signal, the start pulse signal, and the reset signal are input to operate.

Connection relations of the shift register in FIG. 18 are described. In the shift register of FIG. 18, the i-th flip-flop 5701-i (any one of the flip-flops 5701-1 to 5701-n) has the first wiring 5501 shown in FIG. -1, the second wiring 5502 shown in FIG. 19 is connected to the seventh wiring 5717-i + 1, the third wiring 5503 shown in FIG. 19 is connected to the seventh wiring 5717-i, and is shown in FIG. The sixth wiring 5506 is connected to the fifth wiring 5715.

Further, the fourth wiring 5504 shown in FIG. 19 is connected to the second wiring 5712 in the odd-numbered flip-flops, and is connected to the third wiring 5713 in the even-numbered flip-flops. The fifth wiring shown in FIG. 5505 is connected to the fourth wiring 5714.

However, the first wiring 5501 of the first-stage flip-flop 5701-1 shown in FIG. 19 is connected to the first wiring 5711, and the second wiring 5502 of the n-th flip-flop 5701-n shown in FIG. It is connected to the wiring 5716.

Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Further, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as a first power supply line and a second power supply line, respectively.

Next, FIG. 19 shows details of the flip-flop shown in FIG. The flip-flop illustrated in FIG. 19 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Note that the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 are n-channel transistors. It is assumed that the gate-source voltage (Vgs) becomes conductive when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

In FIG. 19, the gate electrode of the third thin film transistor 5573 is electrically connected to the power supply line. A circuit in which the third thin film transistor 5573 and the fourth thin film transistor 5574 are connected (a circuit surrounded by a chain line 5500 in FIG. 19) corresponds to the circuit configuration illustrated in FIG. Here, an example in which all thin film transistors are enhancement type n-channel transistors is shown; however, the present invention is not particularly limited. For example, the third thin film transistor 5573 drives a driving circuit even if a depletion type n-channel transistor is used. You can also

Next, a connection structure of the flip-flop illustrated in FIG. 19 is described below.

A first electrode (one of a source electrode and a drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504, and a second electrode (the other of the source electrode and the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503. Is done.

A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and a second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, the second electrode of the third thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505. Connected.

The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, the second electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the fourth thin film transistor 5574 is connected to the first thin film transistor 5571. Connected to the gate electrode.

The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, the second electrode of the fifth thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571, and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501. Connected.

The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, the second electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571, and the gate electrode of the sixth thin film transistor 5576 is connected to the second thin film transistor 5572. Connected to the gate electrode.

The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, the second electrode of the seventh thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571, and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. Connected. The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506, the second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 5501. Connected.

Note that a connection position of the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574, the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 is a node 5543. And Further, a connection position of the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574, the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 is a node 5544. And

Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5504 may be referred to as a first signal line, a second signal line, a third signal line, and a fourth signal line, respectively. Further, the fifth wiring 5505 may be called a first power supply line, and the sixth wiring 5506 may be called a second power supply line.

In addition, the signal line driver circuit and the scan line driver circuit can be manufactured using only the n-channel TFT described in Embodiment Mode 4. Since the n-channel TFT described in Embodiment 4 has high field effect mobility of the transistor, the driving frequency of the driver circuit can be increased. In addition, the n-channel TFT described in Embodiment 4 has frequency characteristics (referred to as f characteristics) because parasitic capacitance is reduced by a source region or a drain region which is an In—Ga—Zn—O-based non-single-crystal layer. high. For example, the scan line driver circuit using n-channel TFTs described in Embodiment Mode 4 can be operated at high speed, so that the frame frequency is increased or black screen insertion is realized. be able to.

Further, a higher frame frequency can be realized by increasing the channel width of the transistor in the scan line driver circuit or disposing a plurality of scan line driver circuits. When a plurality of scanning line driving circuits are arranged, a scanning line driving circuit for driving even-numbered scanning lines is arranged on one side, and a scanning line driving circuit for driving odd-numbered scanning lines is arranged on the opposite side. By arranging them in this manner, it is possible to increase the frame frequency. In addition, when a plurality of scanning line driving circuits outputs signals to the same scanning line, it is advantageous for increasing the size of the display device.

In the case of manufacturing an active matrix light-emitting display device, it is preferable to dispose a plurality of scan line driver circuits in order to dispose a plurality of thin film transistors in at least one pixel. An example of a block diagram of an active matrix light-emitting display device is illustrated in FIG.

A light-emitting display device illustrated in FIG. 14B includes a pixel portion 5401 having a plurality of pixels each provided with a display element over a substrate 5400, a first scan line driver circuit 5402 and a second scan line driver circuit 5404 for selecting each pixel. And a signal line driver circuit 5403 for controlling input of a video signal to the selected pixel.

In the case where a video signal input to the pixel of the light-emitting display device illustrated in FIG. 14B is in a digital format, the pixel is turned on or off by switching on and off of the transistor. Therefore, gradation display can be performed using the area gradation method or the time gradation method. The area gradation method is a driving method in which gradation display is performed by dividing one pixel into a plurality of subpixels and independently driving each subpixel based on a video signal. The time gray scale method is a driving method for performing gray scale display by controlling a period during which a pixel emits light.

Since a light emitting element has a higher response speed than a liquid crystal element or the like, it is more suitable for a time gray scale method than a liquid crystal element. Specifically, when displaying by the time gray scale method, one frame period is divided into a plurality of subframe periods. Then, in accordance with the video signal, the light emitting element of the pixel is turned on or off in each subframe period. By dividing into a plurality of subframe periods, the total length of a period during which a pixel actually emits light during one frame period can be controlled by a video signal, and gradation can be displayed.

Note that in the light-emitting display device illustrated in FIG. 14B, when two switching TFTs are provided in one pixel, a signal input to the first scan line which is a gate wiring of one switching TFT is the first. In this example, the second scanning line driving circuit 5404 generates a signal generated by the scanning line driving circuit 5402 and input to the second scanning line which is the gate wiring of the other switching TFT. Both a signal input to one scanning line and a signal input to the second scanning line may be generated by one scanning line driving circuit. Further, for example, a plurality of scanning lines used for controlling the operation of the switching element may be provided in each pixel depending on the number of switching TFTs included in one pixel. In this case, all signals input to the plurality of scanning lines may be generated by one scanning line driving circuit, or may be generated by a plurality of scanning line driving circuits.

In the light-emitting display device, part of a driver circuit that can include n-channel TFTs among driver circuits can be formed over the same substrate as the thin film transistor in the pixel portion. In addition, the signal line driver circuit and the scan line driver circuit can be manufactured using only the n-channel TFTs described in Embodiments 4 to 6.

FIG. 42 is a diagram illustrating the positional relationship between a signal input terminal, a scan line, a signal line, a protection circuit including a nonlinear element, and a pixel portion included in a display device. A scanning line 323 and a signal line 324 are arranged so as to intersect with each other over the substrate 320 having an insulating surface, so that a pixel portion 327 is formed. Note that the pixel portion 327 corresponds to the pixel portion 5301 and the pixel portion 5401 shown in FIG.

The pixel portion 327 includes a plurality of pixels 328 arranged in a matrix. The pixel 328 includes a pixel TFT 329 connected to the scanning line 323 and the signal line 324, a storage capacitor portion 330, and a pixel electrode 331.

In the pixel configuration shown here, in the storage capacitor portion 330, one electrode and the pixel TFT 329 are connected, and the other electrode and the capacitor line 332 are connected. The pixel electrode 331 constitutes one electrode for driving a display element (a liquid crystal element, a light emitting element, a contrast medium (electronic ink), or the like). The other electrode of these display elements is connected to the common terminal 333.

The protection circuit is provided between the pixel portion 327 and the signal line input terminal 322. Further, it is disposed between the scan line driver circuit and the pixel portion 327. In this embodiment mode, a plurality of protection circuits are provided so that a surge voltage is applied to the scanning line 323, the signal line 324, and the capacitor bus line 337 due to static electricity or the like, and the pixel TFT 329 and the like are not destroyed. . For this reason, the protection circuit is configured to release charges to the common wiring when a surge voltage is applied.

In this embodiment, the protection circuit 334 is provided on the scanning line 323 side, the protection circuit 335 is provided on the signal line 324 side, and the protection circuit 336 is provided on the capacitor bus line 337. However, the position of the protection circuit is not limited to this. In the case where the scan line driver circuit is not mounted using a semiconductor device such as an IC, the protection circuit 334 is not necessarily provided on the scan line 323 side.

The thin film transistor described in any of Embodiments 1 to 3 can be used for each of these circuits.

Here, the structure of the common terminal 333 will be described with reference to FIG.

FIG. 45A is a cross-sectional view of the common terminal portion, and corresponds to D1-D2 of the top view shown in FIG.

The common potential line 491 is provided over the gate insulating layer 403 and is formed using the same material and through the same steps as the first wiring 409 to the third wiring 411 illustrated in FIG.

Further, the common potential line 491 is covered with an organic insulating layer 452, and the organic insulating layer 452 has a plurality of openings at positions overlapping with the common potential line 491. This opening is formed in the same process as a contact hole connecting any one of the first wiring 409 to the third wiring 411 and the pixel electrode 110.

The common electrode 492 is provided over the organic insulating layer 452 and is manufactured using the same material and through the same process as the connection wiring 453 and the pixel electrode of the pixel portion.

Note that the common electrode 492 is an electrode that comes into contact with the conductive particles contained in the sealant, and is electrically connected to the counter electrode of the second substrate.

The driving circuit described above is not limited to a liquid crystal display device or a light-emitting display device, and may be used for electronic paper that drives electronic ink using an element that is electrically connected to a switching element. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the same readability as paper, low power consumption compared to other display devices, and the advantage that it can be made thin and light. ing.

Through the above, a display device with improved image quality can be manufactured.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 11)
A display device can be manufactured using the thin film transistor described in the above embodiment in a pixel portion and further in a driver circuit. In addition, the thin film transistor described in any of the above embodiments can be used for part or all of the driver circuit and formed over the same substrate as the pixel portion, whereby a system-on-panel can be formed.

The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element) or a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, and the like. In addition, a display medium whose contrast is changed by an electric effect, such as electronic ink, can be used.

The display device includes a panel in which the display element is sealed, and a module in which an IC including a controller is mounted on the panel. Further, in the process of manufacturing the display device, the element substrate which corresponds to one embodiment before the display element is completed is provided with a means for supplying current to the display element in each of the plurality of pixels. Specifically, the element substrate may be in a state in which only the pixel electrode of the display element is formed, or after the formation of the conductive layer to be the pixel electrode and before the pixel electrode is formed by etching. It can be in any state, and all forms apply.

Note that a display device in this specification means an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, a module with a FPC (Flexible printed circuit) or TAB (Tape Automated Bonding) tape or TCP (Tape Carrier Package), a module with a printed wiring board at the end of a TAB tape or TCP, or a display It is assumed that the display device includes all modules in which an IC (integrated circuit) is directly mounted on the element by a COG (Chip On Glass) method.

In this embodiment, the appearance and a cross section of a liquid crystal display panel will be described with reference to FIGS. FIG. 22 shows highly reliable thin film transistors 4010 and 4011 including the In—Ga—Zn—O-based non-single-crystal layer described in Embodiment 4 formed over the first substrate 4001 as an oxide semiconductor layer, and liquid crystal FIG. 22B is a top view of a panel in which an element 4013 is sealed between a second substrate 4006 and a sealant 4005, and FIG. 22B is a cross-sectional view taken along line MN in FIGS. 22A1 and 22A2. Equivalent to.

A sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealant 4005, and the second substrate 4006. In addition, a signal line driver circuit 4003 formed using a single crystal semiconductor layer or a polycrystalline semiconductor layer is mounted over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. ing.

Note that a connection method of a driver circuit which is separately formed is not particularly limited, and a COG method, a wire bonding method, a TAB method, or the like can be used. FIG. 22A1 illustrates an example in which the signal line driver circuit 4003 is mounted by a COG method, and FIG. 22A2 illustrates an example in which the signal line driver circuit 4003 is mounted by a TAB method.

In addition, the pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of thin film transistors. In FIG. 22B, the thin film transistor 4010 included in the pixel portion 4002 and the scan line driver circuit are provided. A thin film transistor 4011 included in the circuit 4004 is illustrated. An organic insulating layer 4021 is provided over the thin film transistors 4010 and 4011.

As the thin film transistors 4010 and 4011, the highly reliable thin film transistor described in Embodiment 4 including an In—Ga—Zn—O-based non-single-crystal layer as an oxide semiconductor layer can be used. Further, the thin film transistor described in Embodiment 5 may be applied. In this embodiment mode, the thin film transistors 4010 and 4011 are n-channel thin film transistors.

In addition, the pixel electrode 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. A counter electrode 4031 of the liquid crystal element 4013 is formed over the second substrate 4006. A portion where the pixel electrode 4030, the counter electrode 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that the pixel electrode 4030 and the counter electrode 4031 are each provided with insulating layers 4032 and 4033 each functioning as an alignment film, and the liquid crystal layer 4008 is interposed between the insulating layers 4032 and 4033.

Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or polyester films can also be used.

Reference numeral 4035 denotes a columnar spacer obtained by selectively etching the insulating layer, and is provided for controlling the distance (cell gap) between the pixel electrode 4030 and the counter electrode 4031. A spherical spacer may be used. The counter electrode 4031 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 4010. Using the common connection portion, the counter electrode 4031 and the common potential line can be electrically connected to each other through conductive particles arranged between the pair of substrates. Note that the conductive particles are included in the sealant 4005.

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer 4008 in order to improve the temperature range. A liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 10 μs to 100 μs and is optically isotropic, so that alignment treatment is unnecessary and viewing angle dependency is small.

Note that although this embodiment is an example of a transmissive liquid crystal display device, this embodiment can be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

In the liquid crystal display device of this embodiment, a polarizing plate is provided on the outer side (viewing side) of the substrate, a colored layer is provided on the inner side, and an electrode used for the display element. The polarizing plate may be provided on the inner side of the substrate. Good. In addition, the stacked structure of the polarizing plate and the colored layer is not limited to this embodiment mode, and may be set as appropriate depending on the material and manufacturing process conditions of the polarizing plate and the colored layer. Further, a light shielding layer functioning as a black matrix may be provided.

In this embodiment mode, the thin film transistor obtained in the above embodiment mode is covered with the organic insulating layer 4021 in order to reduce surface unevenness of the thin film transistor and improve the reliability of the thin film transistor.

In addition, an organic insulating layer 4021 having flatness is formed. As the organic insulating layer 4021, the material described for the organic insulating layer 452 described in Embodiment 1 can be used as appropriate.

The pixel electrode 4030 and the counter electrode 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, and indium zinc. A light-transmitting conductive material such as an oxide or indium tin oxide to which silicon oxide is added can be used.

The pixel electrode 4030 and the counter electrode 4031 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / □ or less and a light transmittance of 70% or more at a wavelength of 550 nm. Moreover, it is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω · cm or less.

As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more kinds thereof can be given.

In addition, a variety of signals and potentials are supplied to the signal line driver circuit 4003 which is formed separately, the scan line driver circuit 4004, or the pixel portion 4002 from an FPC 4018.

In this embodiment, the connection terminal electrode 4015 is formed using the same conductive layer as the pixel electrode 4030 included in the liquid crystal element 4013, and the terminal electrode 4016 is formed using the same conductive layer as the source and drain electrodes of the thin film transistors 4010 and 4011. ing.

The connection terminal electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019.

FIG. 22 illustrates an example in which the signal line driver circuit 4003 is separately formed and mounted on the first substrate 4001; however, this embodiment is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

FIG. 23 shows an example in which a liquid crystal display module is formed as a display device using a TFT substrate 2600 manufactured by applying the above embodiment mode.

FIG. 23 illustrates an example of a liquid crystal display module, in which a TFT substrate 2600 and a counter substrate 2601 are fixed by a sealant 2602, and a pixel portion 2603 including a TFT and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween. A display area is formed. The colored layer 2605 is necessary for color display. In the case of the RGB method, a colored layer corresponding to each color of red, green, and blue is provided corresponding to each pixel. A polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are provided outside the TFT substrate 2600 and the counter substrate 2601. The light source is composed of a cold cathode tube 2610 and a reflector 2611. The circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible wiring board 2609, and an external circuit such as a control circuit or a power circuit is incorporated. Yes. Moreover, you may laminate | stack in the state which had the phase difference plate between the polarizing plate and the liquid-crystal layer.

The liquid crystal display module includes a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, and a PVA (Pattern Vertical Alignment) mode. (Axial Symmetrical Aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Antiferroelectric liquid crystal) It is possible to use a crystal.

Through the above, a highly reliable liquid crystal display panel can be manufactured.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 12)
In this embodiment, an example of electronic paper is described as an embodiment of a display device.

FIG. 13 illustrates active matrix electronic paper as an example of a display device to which the above embodiment is applied. The thin film transistor 581 used for the display device can be manufactured similarly to the thin film transistor described in the above embodiment and is a highly reliable thin film transistor including an In—Ga—Zn—O-based non-single-crystal layer as an oxide semiconductor layer.

The electronic paper illustrated in FIG. 13 is an example of a display device using a twisting ball display system. In the twisting ball display system, spherical particles that are painted in white and black are arranged between the first electrode and the second electrode, which are electrodes used for the display element, and a potential difference is generated between the first electrode and the second electrode. This is a method of displaying by controlling the direction of all spherical particles.

The thin film transistor 581 over the first substrate 580 is a bottom-gate thin film transistor, and is in contact with and electrically connected to the first electrode 587 through openings formed in the insulating layers 583, 584, and 585 by a source electrode or a drain electrode. ing. Between the first electrode 587 formed on the first substrate 580 and the second electrode 588 formed on the second substrate 596, the black region 590a and the white region 590b, and the black region 590a and the white region 590b Spherical particles 589 are provided having cavities 594 that are filled with liquid. The periphery of the spherical particles 589 is filled with a filler 595 such as a resin (see FIG. 13). In the present embodiment, the first electrode 587 corresponds to a pixel electrode, and the second electrode 588 corresponds to a common electrode. The second electrode 588 is electrically connected to a common potential line provided over the same substrate as the thin film transistor 581. Using any one common connection portion described in any of Embodiments 1 to 3, the second electrode 588 and the common potential line can be electrically connected to each other through conductive particles disposed between the pair of substrates. it can.

Further, instead of the twisting ball, an electrophoretic element can be used. The electrophoretic element includes a transparent liquid and microcapsules having a diameter of about 10 μm to 200 μm in which positively charged white fine particles and negatively charged black fine particles are enclosed. The microcapsule provided between the first electrode and the second electrode, when an electric field is applied by the first electrode and the second electrode, the white fine particles and the black fine particles move in opposite directions, and white or black Can be displayed. A display element to which this principle is applied is an electrophoretic display element, and is generally called electronic paper. Since the electrophoretic display element has higher reflectance than the liquid crystal display element, an auxiliary light is unnecessary, power consumption is small, and the display portion can be recognized even in a dim place. Further, even when power is not supplied to the display portion, an image once displayed can be held; therefore, a semiconductor device with a display function from a radio wave source (simply a display device or a semiconductor having a display device) Even when the device is also moved away, the displayed image can be stored.

Through the above, highly reliable electronic paper as a display device can be manufactured.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 13)
In this embodiment, an example of a light-emitting display device is described as an embodiment of a display device. As a display element included in the display device, a light-emitting element utilizing electroluminescence is used here. A light-emitting element using electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are respectively injected from the pair of electrodes into the layer containing the light emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excitation light-emitting element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

FIG. 20 is a diagram illustrating an example of a pixel configuration to which digital time grayscale driving can be applied as an example of a light-emitting display device among display devices.

A structure and operation of a pixel to which digital time gray scale driving can be applied will be described. Here, a mode is shown in which two n-channel transistors each using an oxide semiconductor layer (In—Ga—Zn—O-based non-single-crystal layer) for a channel formation region are used for one pixel.

The pixel 6400 includes a switching transistor 6401, a driving transistor 6402, a light-emitting element 6404, and a capacitor 6403. The switching transistor 6401 has a gate connected to the scanning line 6406, a first electrode (one of the source electrode and the drain electrode) connected to the signal line 6405, and a second electrode (the other of the source electrode and the drain electrode) connected to the driving transistor. 6402 is connected to the gate.

The driving transistor 6402 has a gate connected to the power supply line 6407 through the capacitor 6403, a first electrode (one of a source electrode and a drain electrode) connected to the power supply line 6407, and a second electrode (a source electrode and a drain electrode). Is connected to the first electrode (pixel electrode) of the light emitting element 6404. The second electrode of the light emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is electrically connected to a common potential line formed over the same substrate.

Note that a low power supply potential is set for the second electrode (the common electrode 6408) of the light-emitting element 6404. Note that the low power supply potential is a potential that satisfies the low power supply potential <the high power supply potential with reference to the high power supply potential set on the power supply line 6407. For example, GND, 0 V, or the like is set as the low power supply potential. May be. The potential difference between the high power supply potential and the low power supply potential is applied to the light emitting element 6404 and a current is caused to flow through the light emitting element 6404 so that the light emitting element 6404 emits light. Each potential is set to be equal to or higher than the forward threshold voltage.

Note that the capacitor 6403 can be omitted by using the gate capacitor of the driving transistor 6402 instead. As for the gate capacitance of the driving transistor 6402, a capacitance may be formed between the channel region and the gate electrode.

Here, in the case of the voltage input voltage driving method, a video signal is input to the gate of the driving transistor 6402 so that the driving transistor 6402 is sufficiently turned on or off. That is, the driving transistor 6402 is operated in a linear region. Since the driving transistor 6402 operates in a linear region, a voltage higher than the voltage of the power supply line 6407 is applied to the gate of the driving transistor 6402. Note that a voltage higher than the sum of the power supply line voltage and Vth of the driving transistor 6402 is applied to the signal line 6405.

In addition, when analog grayscale driving is performed instead of digital time grayscale driving, the same pixel configuration as that in FIG. 20 can be used by changing signal input.

In the case of performing analog gradation driving, a voltage higher than the sum of the forward voltage of the light-emitting element 6404 and the Vth of the driving transistor 6402 is applied to the gate of the driving transistor 6402. The forward voltage of the light-emitting element 6404 refers to a voltage for obtaining desired luminance, and is at least larger than the forward threshold voltage. Note that when a video signal that causes the driving transistor 6402 to operate in a saturation region is input, a current can flow through the light-emitting element 6404. In order to operate the driving transistor 6402 in the saturation region, the potential of the power supply line 6407 is set higher than the gate potential of the driving transistor 6402. By making the video signal analog, current corresponding to the video signal can be supplied to the light-emitting element 6404 to perform analog gradation driving.

Note that the pixel structure illustrated in FIG. 20 is not limited thereto. For example, a switch, a resistor, a capacitor, a transistor, a logic circuit, or the like may be newly added to the pixel illustrated in FIG.

Next, the structure of the light-emitting element will be described with reference to FIG. Here, the cross-sectional structure of the pixel will be described with an example in which the driving TFT is an n-type. TFTs 7001, 7011, and 7021 which are driving TFTs used for the display device in FIG. 21 can be manufactured in a manner similar to the thin film transistor described in the above embodiment, and an In—Ga—Zn—O-based non-single-crystal layer is formed using an oxide semiconductor layer. It is a highly reliable thin film transistor.

The light emitting element only needs to have at least an anode or a cathode transparent in order to extract emitted light. Then, a thin film transistor and a light emitting element are formed on the substrate, and a top emission that extracts light from a surface opposite to the substrate, a bottom emission that extracts light from a surface on the substrate, and a surface opposite to the substrate and the substrate are provided. The pixel structure of this embodiment mode can be applied to a light-emitting element having any emission structure.

A light-emitting element having a top emission structure will be described with reference to FIG.

FIG. 21A is a cross-sectional view of a pixel in the case where the TFT 7001 that is a driving TFT is n-type and light emitted from the light-emitting element 7002 passes to the anode 7005 side. In FIG. 21A, a cathode 7003 of a light-emitting element 7002 and a TFT 7001 which is a driving TFT are electrically connected, and an EL layer 7004 and an anode 7005 are stacked in this order on the cathode 7003. Various materials can be used for the cathode 7003 as long as it has a low work function and reflects light. For example, Ca, Al, MgAg, AlLi, etc. are desirable. The EL layer 7004 may be a single layer or a plurality of layers stacked. In the case of a plurality of layers, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are stacked in this order on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, or titanium oxide. A light-transmitting conductive conductive layer such as indium tin oxide, indium tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added may be used.

A region where the EL layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 21A, light emitted from the light-emitting element 7002 is emitted to the anode 7005 side as shown by an arrow.

Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. A cross-sectional view of a pixel in the case where the driving TFT 7011 is n-type and light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side is shown. In FIG. 21B, a cathode 7013 of a light-emitting element 7012 is formed over a light-transmitting conductive layer 7017 electrically connected to the driving TFT 7011. An EL layer 7014 and an anode 7015 are formed over the cathode 7013. Are sequentially stacked. Note that in the case where the anode 7015 has a light-transmitting property, a shielding layer 7016 for reflecting or shielding light may be formed so as to cover the anode. As in the case of FIG. 21A, any material can be used for the cathode 7013 as long as it is a conductive material having a low work function. However, the thickness is set so as to transmit light (preferably, about 5 nm to 30 nm). For example, an aluminum layer having a thickness of 20 nm can be used as the cathode 7013. In addition, as in FIG. 21A, the EL layer 7014 may be formed of a single layer or a stack of a plurality of layers. The anode 7015 is not required to transmit light, but can be formed using a light-transmitting conductive material as in FIG. The shielding layer 7016 can be formed using, for example, a metal that reflects light, but is not limited to a metal layer. For example, a resin to which a black pigment is added can also be used.

A region where the EL layer 7014 is sandwiched between the cathode 7013 and the anode 7015 corresponds to the light-emitting element 7012. In the case of the pixel shown in FIG. 21B, light emitted from the light-emitting element 7012 is emitted to the cathode 7013 side as shown by an arrow.

Next, a light-emitting element having a dual emission structure will be described with reference to FIG. In FIG. 21C, a cathode 7023 of a light-emitting element 7022 is formed over a light-transmitting conductive layer 7027 electrically connected to a driving TFT 7021. An EL layer 7024 and an anode 7025 are formed over the cathode 7023. Are sequentially stacked. As in the case of FIG. 21A, any material can be used for the cathode 7023 as long as it is a conductive material having a low work function. However, the thickness is set so as to transmit light. For example, Al having a thickness of 20 nm can be used as the cathode 7023. Further, as in FIG. 21A, the EL layer 7024 may be formed of a single layer or a stack of a plurality of layers. The anode 7025 can be formed using a light-transmitting conductive material as in FIG. 21A.

A portion where the cathode 7023, the EL layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 7022. In the case of the pixel shown in FIG. 21C, light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by arrows.

Note that although an organic EL element is described here as a light-emitting element, an inorganic EL element can also be provided as a light-emitting element.

Note that in this embodiment mode, an example in which a thin film transistor (driving TFT) that controls driving of a light emitting element is electrically connected to the light emitting element is shown, but current control is performed between the driving TFT and the light emitting element. A configuration in which TFTs are connected may be used.

Note that the display device described in this embodiment is not limited to the structure illustrated in FIG. 21 and can be modified in various ways based on the technical idea in this specification.

Next, the appearance and one embodiment of a cross section of a light-emitting display panel (also referred to as a light-emitting panel), which is one embodiment of the display device, are described with reference to FIGS. FIG. 24A is a top view of a panel in which a first substrate on which a thin film transistor and a light-emitting element are formed and a second substrate are sealed with a sealant provided between the first substrate and the second substrate. FIG. 24B corresponds to a cross-sectional view taken along line HI in FIG.

A sealant 4505 is provided so as to surround the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b provided over the first substrate 4501. A second substrate 4506 is provided over the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b. Therefore, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b are sealed together with the filler 4507 by the first substrate 4501, the sealant 4505, and the second substrate 4506. Thus, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material that has high air tightness and little degassing so as not to be exposed to the outside air.

In addition, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scan line driver circuits 4504a and 4504b provided over the first substrate 4501 include a plurality of thin film transistors. In FIG. A thin film transistor 4510 included in 4502 and a thin film transistor 4509 included in the signal line driver circuit 4503a are illustrated.

As the thin film transistors 4509 and 4510, a highly reliable thin film transistor including an In—Ga—Zn—O-based non-single-crystal layer as an oxide semiconductor layer as described in the above embodiment can be used. Further, the thin film transistor described in Embodiment 5 may be applied. In this embodiment mode, the thin film transistors 4509 and 4510 are n-channel thin film transistors.

A first electrode 4517 that is a pixel electrode included in the light-emitting element 4511 is electrically connected to a source electrode or a drain electrode of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is a stacked structure of the first electrode 4517, the EL layer 4512, and the second electrode 4513; however, the structure is not limited to the structure described in this embodiment. The structure of the light-emitting element 4511 can be changed as appropriate depending on the direction of light extracted from the light-emitting element 4511 or the like.

A partition 4520 is formed using an organic resin layer, an inorganic insulating layer, or an organic polysiloxane layer. In particular, it is preferable to use a photosensitive material and form an opening on the first electrode 4517 so that the side wall of the opening is an inclined surface formed with a continuous curvature.

The EL layer 4512 may be formed of a single layer or a stack of a plurality of layers.

A protective layer may be formed over the second electrode 4513 and the partition 4520 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4511. As the protective layer, a silicon nitride layer, a silicon nitride oxide layer, a DLC layer, or the like can be formed.

In addition, a variety of signals and potentials are supplied to the signal line driver circuits 4503a and 4503b, the scan line driver circuits 4504a and 4504b, or the pixel portion 4502 from FPCs 4518a and 4518b.

In this embodiment, the connection terminal electrode 4515 is formed from the same conductive layer as the first electrode 4517 included in the light-emitting element 4511, and the terminal electrode 4516 is formed from the same conductive layer as the source and drain electrodes included in the thin film transistors 4509 and 4510. Is formed.

The connection terminal electrode 4515 is electrically connected to a terminal included in the FPC 4518a through an anisotropic conductive layer 4519.

The second substrate located in the direction in which light is extracted from the light emitting element 4511 must be translucent. In that case, the second substrate 4506 is formed using a light-transmitting material such as a glass plate, a plastic plate, a polyester film, or an acrylic film.

As the filler 4507, an inert gas such as nitrogen or argon, an ultraviolet curable resin, a thermosetting resin, or the like can be used. As the ultraviolet curable resin and the thermosetting resin, PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as a filler.

Further, if necessary, an optical film such as a polarizing plate, a circularly polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the emission surface of the light emitting element. You may provide suitably. Further, an antireflection layer may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

The signal line driver circuits 4503a and 4503b and the scan line driver circuits 4504a and 4504b may be mounted using a driver circuit formed using a single crystal semiconductor layer or a polycrystalline semiconductor layer over a separately prepared substrate. Further, only the signal line driver circuit, or a part thereof, or only the scanning line driver circuit or only part thereof may be separately formed and mounted, and this embodiment mode is not limited to the structure in FIG.

Through the above, a highly reliable light-emitting display device (display panel) can be manufactured as a display device.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 14)
Electronic paper can be used for electronic devices in various fields as long as they display information. For example, electronic paper can be used for electronic books (electronic books), in-car advertisements, in-car advertisements for vehicles such as trains, and displays on various cards such as credit cards. Examples of electronic devices are illustrated in FIGS.

FIG. 25A illustrates a poster 2631 made of electronic paper. When the advertisement medium is a printed matter of paper, the advertisement is exchanged manually, but the display of the advertisement can be changed in a short time by using the electronic paper to which the above embodiment is applied. In addition, a stable image can be obtained without losing the display. The in-vehicle advertisement may be configured to transmit and receive information wirelessly.

FIG. 25B illustrates an advertisement 2632 in a vehicle such as a train. When the advertising medium is printed paper, the advertisement is exchanged manually, but if the electronic paper to which the above embodiment is applied is used, the advertisement display can be changed in a short time without much labor. it can. In addition, a stable image can be obtained without distorting the display. Note that the poster may be configured to transmit and receive information wirelessly.

FIG. 26 illustrates an example of an e-book reader 2700. For example, the electronic book 2700 includes two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated with a shaft portion 2711 and can be opened / closed using the shaft portion 2711 as an axis. With such a configuration, an operation like a paper book can be performed.

A display portion 2705 and a display portion 2707 are incorporated in the housing 2701 and the housing 2703, respectively. The display unit 2705 and the display unit 2707 may be configured to display a continuous screen or may be configured to display different screens. By adopting a configuration that displays different screens, for example, a sentence can be displayed on the right display unit (display unit 2705 in FIG. 26) and an image can be displayed on the left display unit (display unit 2707 in FIG. 26). .

FIG. 26 illustrates an example in which the housing 2701 is provided with an operation unit and the like. For example, the housing 2701 is provided with a power supply 2721, operation keys 2723, a speaker 2725, and the like. Pages can be turned with the operation keys 2723. Note that a keyboard, a pointing device, or the like may be provided on the same surface as the display portion of the housing. In addition, an external connection terminal (such as an earphone terminal, a USB terminal, or a terminal that can be connected to various cables such as an AC adapter and a USB cable), a recording medium insertion unit, and the like may be provided on the back and side surfaces of the housing. . Further, the e-book reader 2700 may have a structure having a function as an electronic dictionary.

Further, the e-book reader 2700 may have a configuration capable of transmitting and receiving information wirelessly. It is also possible to adopt a configuration in which desired book data or the like is purchased and downloaded from an electronic book server wirelessly.

(Embodiment 15)
The display device according to any of the above embodiments can be applied to various electronic devices (including game machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device). ), Large game machines such as portable game machines, portable information terminals, sound reproduction apparatuses, and pachinko machines.

FIG. 27A illustrates an example of a television device 9600. In the television device 9600, a display portion 9603 is incorporated in a housing 9601. The display portion 9703 can display an image. Here, a structure in which the housing 9601 is supported by a stand 9605 is illustrated.

The television device 9600 can be operated with an operation switch provided in the housing 9601 or a separate remote controller 9610. Channels and volume can be operated with operation keys 9609 provided in the remote controller 9610, and an image displayed on the display portion 9603 can be operated. The remote controller 9610 may be provided with a display portion 9607 for displaying information output from the remote controller 9610.

Note that the television set 9600 is provided with a receiver, a modem, and the like. General TV broadcasts can be received by a receiver, and connected to a wired or wireless communication network via a modem, so that it can be unidirectional (sender to receiver) or bidirectional (sender and receiver). It is also possible to perform information communication between each other or between recipients).

FIG. 27B illustrates an example of a digital photo frame 9700. For example, a digital photo frame 9700 has a display portion 9703 incorporated in a housing 9701. The display portion 9703 can display various images. For example, by displaying image data captured by a digital camera or the like, the display portion 9703 can function in the same manner as a normal photo frame.

Note that the digital photo frame 9700 includes an operation portion, an external connection terminal (a terminal that can be connected to various types of cables such as a USB terminal and a USB cable), a recording medium insertion portion, and the like. These configurations may be incorporated on the same surface as the display portion, but it is preferable to provide them on the side surface or the back surface because the design is improved. For example, a memory that stores image data captured by a digital camera can be inserted into the recording medium insertion unit of the digital photo frame to capture the image data, and the captured image data can be displayed on the display unit 9703.

Further, the digital photo frame 9700 may be configured to transmit and receive information wirelessly. A configuration may be employed in which desired image data is captured and displayed wirelessly.

FIG. 28A illustrates a portable game machine including two housings, a housing 9881 and a housing 9891, which are connected with a hinge 9893 so that the portable game machine can be opened or folded. A display portion 9882 is incorporated in the housing 9881, and a display portion 9883 is incorporated in the housing 9891. In addition, the portable game machine shown in FIG. 28A includes a speaker portion 9884, a recording medium insertion portion 9886, an LED lamp 9890, input means (operation keys 9885, a connection terminal 9887, a sensor 9888 (force, displacement, position). , Speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 9889) and the like. Needless to say, the structure of the portable game machine is not limited to the above, and any structure including at least the display device according to any of the above embodiments may be employed, and any other attached facilities may be appropriately provided. The portable game machine shown in FIG. 28A reads out a program or data recorded in a recording medium and displays the program or data on a display portion, or wirelessly communicates with other portable game machines to share information. It has a function. Note that the function of the portable game machine illustrated in FIG. 28A is not limited to this, and the portable game machine can have a variety of functions.

FIG. 28B illustrates an example of a slot machine 9900 which is a large-sized game machine. In the slot machine 9900, a display portion 9903 is incorporated in a housing 9901. In addition, the slot machine 9900 includes operation means such as a start lever and a stop switch, a coin slot, a speaker, and the like. Needless to say, the configuration of the slot machine 9900 is not limited to that described above, and may be any configuration as long as it includes at least the display device according to any of the above embodiments.

FIG. 29A illustrates an example of a mobile phone 1000. A cellular phone 1000 includes a display portion 1002 incorporated in a housing 1001, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, and the like.

A cellular phone 1000 illustrated in FIG. 29A can input information by touching the display portion 1002 with a finger or the like. In addition, operations such as making a call or typing an e-mail can be performed by touching the display portion 1002 with a finger or the like.

There are mainly three screen modes of the display portion 1002. The first mode is a display mode mainly for displaying images. The first is a display mode mainly for displaying images, and the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the display mode and the input mode are mixed.

For example, when making a phone call or creating an e-mail, the display unit 1002 may be set to a character input mode mainly for inputting characters and an operation for inputting characters displayed on the screen may be performed. In this case, it is preferable to display a keyboard or number buttons on most of the screen of the display portion 1002.

Further, by providing a detection device having a sensor for detecting the inclination, such as a gyroscope or an acceleration sensor, in the mobile phone 1000, the orientation (vertical or horizontal) of the mobile phone 1000 is determined, and the screen display of the display unit 1002 Can be switched automatically.

Further, the screen mode is switched by touching the display portion 1002 or operating the operation button 1003 of the housing 1001. Further, switching may be performed depending on the type of image displayed on the display portion 1002. For example, if the image signal to be displayed on the display unit is moving image data, the mode is switched to the display mode, and if it is text data, the mode is switched to the input mode.

Further, in the input mode, when a signal detected by the optical sensor of the display unit 1002 is detected and there is no input by a touch operation on the display unit 1002, the screen mode is switched from the input mode to the display mode. You may control.

The display portion 1002 can also function as an image sensor. For example, personal authentication can be performed by touching the display unit 1002 with a palm or a finger to capture an image of a palm print, a fingerprint, or the like. In addition, if a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used for the display portion, finger veins, palm veins, and the like can be imaged.

FIG. 29B is also an example of a mobile phone. A mobile phone in FIG. 29B includes a housing 9411, a display device 9410 including a display portion 9412 and operation buttons 9413, an operation button 9402, an external input terminal 9403, a microphone 9404, a speaker 9405, and the like. And a communication device 9400 including a light emitting portion 9406 that emits light when an incoming call is received. A display device 9410 having a display function can be attached to and detached from the communication device 9400 having a telephone function in two directions indicated by arrows. Therefore, the short axes of the display device 9410 and the communication device 9400 can be attached, or the long axes of the display device 9410 and the communication device 9400 can be attached. When only the display function is required, the display device 9410 can be detached from the communication device 9400 and the display device 9410 can be used alone. The communication device 9400 and the display device 9410 can exchange images or input information by wireless communication or wired communication, and each have a rechargeable battery.

(Embodiment 16)
In this embodiment, in the case of manufacturing a thin film transistor using an oxide semiconductor as a semiconductor layer, a method for reusing and recycling an oxide semiconductor from etching waste liquid generated when patterning an oxide semiconductor film is described. To do.

46 and 47 show the reuse cycle.

First, in Step 1 (7101) in FIG. 46, an oxide semiconductor film is formed by a sputtering method or a laser pulse vapor deposition method. 47A and 47B show specific examples at the time of film formation. In FIG. 47A, a gate electrode 7202 and a gate insulating film 7203 are formed over a substrate 7201, and an oxide semiconductor film 7205 is formed over the gate insulating film 7203 by a sputtering method (FIG. 47B )). The target 7204 used at this time is an oxide semiconductor target containing In, Ga, and Zn. As the composition ratio, for example, a target of In: Ga: Zn = 1: 1: 0.5 can be used.

Next, in Step 2 (7102) of FIG. 46, the oxide semiconductor film is patterned. As shown in FIG. 47C, an unnecessary portion of the oxide semiconductor film 7205 is removed by a wet etching method using a resist mask 7206 formed using a photomask. Thus, an oxide semiconductor film 7207 having a desired shape can be obtained.

Next, in step 3 (7103) of FIG. 46, the etching waste liquid generated in step 2 (7102) is collected (FIG. 47E). Note that when the etching waste liquid is collected, the etching waste liquid may be neutralized. This is because, in view of good workability, it is preferable to treat the neutralized etching waste liquid because it is safer.

Next, in Step 4 (7104) of FIG. 46, a solidification process is performed to remove moisture from the etching waste liquid to obtain a solid material 7209 (FIG. 47F). In order to remove moisture, the etching waste liquid may be heated. In addition, after obtaining the solid material 7209, the composition ratio is adjusted by adding a deficient component after performing a composition analysis or the like so that the composition ratio of the target to be regenerated in a later step becomes a desired composition ratio. Do.

Next, in step 5 (7105) of FIG. 46, the solid object 7209 is put into a die having a desired shape, and is pressed and fired to obtain a sintered body 7210. Further, a target 7212 is formed by attaching the sintered body 7210 to the backing plate 7211 with an adhesive (FIG. 47G). However, the firing temperature is preferably 700 ° C. or higher. The film thickness is preferably 5 nm or more and 10 nm or less. Note that since the composition ratio of In, Ga, and Zn is adjusted in Step 3 (7103) in FIG. 46, the target 7212 having a desired composition ratio can be obtained.

Note that the obtained target 7212 can be used for film formation in Step 1 (7101) of FIG.

As described above, an oxide semiconductor can be regenerated and reused from an etching waste liquid in the case of manufacturing a thin film transistor using an oxide semiconductor as a semiconductor layer.

Note that indium and gallium contained in an oxide semiconductor are known to be rare metals, and therefore, resource saving is achieved by using the reuse method described in this embodiment. In addition, the cost of a product formed using an oxide semiconductor can be reduced.

Claims (9)

A gate electrode;
An oxide semiconductor layer overlapping with the gate electrode;
An organic resin layer in contact with the oxide semiconductor layer;
A thin film transistor comprising: a wiring provided between the oxide semiconductor layer and the organic resin layer.   2. The thin film transistor according to claim 1, further comprising a gate insulating layer between the gate electrode and the oxide semiconductor layer. A gate electrode;
A gate insulating layer formed on the gate electrode;
An oxide semiconductor layer overlapping with the gate electrode and formed over the gate insulating layer;
A wiring formed over the gate insulating layer and the oxide semiconductor layer;
A thin film transistor comprising: the oxide semiconductor layer; and an organic resin layer in contact with the wiring.   4. The thin film transistor according to claim 1, wherein the oxide semiconductor layer contains indium, gallium, and zinc. Forming a gate electrode on the substrate;
Forming a gate insulating layer covering the gate electrode;
Forming an oxide semiconductor layer overlapping the gate electrode through the gate insulating layer;
Forming a wiring on the oxide semiconductor layer;
A method for manufacturing a thin film transistor, wherein an organic insulating layer is formed in contact with the oxide semiconductor layer and the wiring.   6. The method for manufacturing a thin film transistor according to claim 5, wherein plasma treatment is performed on a surface of the gate insulating layer before the formation of the oxide semiconductor layer.   7. The method for manufacturing a thin film transistor according to claim 5, wherein plasma treatment is performed on a surface of the oxide semiconductor layer before the formation of the wiring.   5. A display device comprising the thin film transistor according to claim 1 in a pixel portion and a driver circuit. Forming a gate electrode on the substrate;
Forming a gate insulating layer covering the gate electrode;
Forming an oxide semiconductor layer overlapping the gate electrode through the gate insulating layer;
Forming a wiring on the oxide semiconductor layer;
Forming an organic insulating layer in contact with the oxide semiconductor layer and the wiring;
A method for manufacturing a display device, characterized by forming a pixel electrode in contact with the wiring.

Images