JP5090745B2 - Display device and manufacturing method of display device - Google Patents

Description

  The present invention relates to a display device and a manufacturing method of the display device, and more particularly to a technique effective when applied to a manufacturing method of a TFT substrate of a TFT liquid crystal display device.

  Conventionally, in a TFT liquid crystal display device, a pixel electrode and a common electrode (referred to as a counter electrode) for driving the liquid crystal on one of a pair of (two) substrates encapsulated with liquid crystal sandwiched between them. There are also some). At this time, as a method of forming the pixel electrode and the common electrode, for example, the pixel electrode and the common electrode are formed by etching one conductive film such as ITO formed on one insulating layer. And, for example, after etching one conductive film to form the common electrode, an insulating layer and another conductive layer are formed on the common electrode, and the second conductive layer is etched to form the common electrode. There is a method of forming a pixel electrode.

  When the pixel electrode and the common electrode are formed by the latter method, the substrate on which the pixel electrode and the common electrode are provided (hereinafter referred to as a TFT substrate) of the pair of substrates is, for example, It is manufactured by the procedure as follows.

  First, a first conductive film having a high light transmittance such as ITO is formed on the surface of an insulating substrate such as a glass substrate, and the first conductive film is etched to form a common electrode. Next, for example, a second conductive film such as aluminum is formed, and the second conductive film is etched to form scan signal lines and the like.

  Next, for example, a first insulating layer having a function as a gate insulating film of a TFT is formed. Subsequently, for example, a semiconductor material film such as amorphous silicon is formed, and the semiconductor material film is etched to form the first insulating layer. A TFT semiconductor layer is formed.

  Next, for example, a third conductive film such as aluminum is formed, and the third conductive film is etched to form a video signal line, a drain electrode and a source electrode of the TFT, and the like.

  Next, after forming the second insulating layer, for example, a fourth conductive film such as ITO having a high light transmittance is formed, and the fourth conductive film is etched to form a pixel electrode. At this time, in the second insulating layer, for example, a through hole is formed on the source electrode of the TFT so that the pixel electrode and the source electrode are electrically connected.

  When manufacturing a TFT substrate in such a procedure, the conventional TFT substrate manufacturing method generally includes, for example, a step of etching the first conductive film, a step of etching the second conductive film, and the semiconductor material. In each of the steps of etching the film, etching the third conductive film, forming a through hole in the second insulating layer, and etching the fourth conductive film, The etching resist which exposed and developed is formed. Therefore, the number of times of forming the etching resist increases, and there is a problem that the manufacturing cost increases.

  Further, in the conventional TFT substrate manufacturing method, generally, the photosensitive resist is exposed using an exposure mask in which an exposure pattern is formed using a light shielding material such as chromium on the surface of a light-transmitting substrate such as a glass substrate. doing. For this reason, the positional relationship of the video signal line and the common electrode formed on the insulating substrate tends to deviate from the positional relationship at the time of design due to the positional shift of the exposure mask. As a result, for example, there is a problem in that the image quality of the display device is uneven and it is difficult to further increase the definition of the display device.

In recent years, for example, a stacked body of a semiconductor layer and a first conductive layer with the same pattern has been formed in a drain signal line (video signal line) formation region and a thin film transistor (TFT) formation region. A forming method and a manufacturing method for separating the drain electrode and the source electrode of the thin film transistor by using the same mask after forming the second conductive film have been proposed (see, for example, Patent Document 1). ).
JP 2001-201766 A

  In the TFT substrate manufacturing method, it is desirable to reduce the number of times the etching resist is formed as much as possible in order to reduce the manufacturing cost of the TFT substrate and the positional deviation.

  In the method of manufacturing a TFT substrate in which the common electrode, the insulating layer, and the pixel electrode are stacked on the surface of the insulating substrate, as described above, the step of forming the etching resist is usually required six times. For example, even if the method described in Patent Document 1 is applied, the step of forming the etching resist usually requires 5 or 4 times.

  However, the inventors of the present invention can further reduce the step of forming the etching resist in the manufacturing method of the TFT substrate in which the common electrode, the insulating layer, and the pixel electrode are stacked on the surface of the insulating substrate. I think I can do it.

  An object of the present invention is to provide a TFT substrate manufacturing method in which the common electrode, the insulating layer, and the pixel electrode are laminated on the surface of an insulating substrate, and the step of forming the etching resist is minimized. The object is to provide a technique capable of reducing the manufacturing cost.

  Another object of the present invention is to provide a video signal line formed on a surface of an insulating substrate in a method of manufacturing a TFT substrate in which the common electrode, the insulating layer, and the pixel electrode are stacked on the surface of the insulating substrate. It is an object of the present invention to provide a technique capable of reducing such positional deviation.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of typical inventions among the inventions disclosed in the present application will be described as follows.

  (1) A plurality of scanning signal lines, a plurality of video signal lines, a plurality of TFTs and pixel electrodes arranged in a matrix, and a common electrode are provided on the surface of the insulating substrate. A gate insulating film stacked on the scanning signal line as viewed from the insulating substrate, a semiconductor layer stacked on the gate insulating film, and a drain electrode stacked on a drain region of the semiconductor layer; MIS transistor having a source electrode stacked on a source region of the semiconductor layer, the pixel electrode being connected to the source electrode or the drain electrode through a hole, and the pixel electrode and the common electrode Is formed by laminating the common electrode, the insulating layer, and the pixel electrode in this order on the surface of the insulating substrate, the common electrode being made of a first conductive material, and the scanning signal line being a second conductive material. The video signal line, the drain electrode and the source electrode of the TFT are made of a third conductive material, the pixel electrode is made of a fourth conductive material, and the gate insulating film is made of a first insulating material, The insulating layer interposed between the common electrode and the pixel electrode is a display device made of a second insulating material, and the first conductive material is interposed between the insulating substrate and the video signal line. A conductive film made of, a conductive film made of the second conductive material, an insulating film made of the first insulating material, and a semiconductor material film used for forming a semiconductor layer of the TFT. The display device in which each of the conductive film, the insulating film, and the semiconductor material film interposed between the first video signal lines has a shape similar to that of the video signal lines when viewed in plan. .

  (2) In the display device of (1), one video signal line is divided every two adjacent scanning signal lines, and is flat with the two adjacent scanning signal lines. The two video signal line segments that are divided into a plurality of video signal line segments that do not overlap each other and are arranged with one scanning signal line interposed therebetween are made of the fourth conductive material, and the 1 A display device connected through a through-hole with a connection wiring that three-dimensionally intersects a scanning signal line.

  (3) In the display device of (2), the connection wiring is connected to the pixel electrode of the drain electrode and the source electrode through a different through hole from the through hole connected to the two video signal line segments. Display device connected to the electrode that is not.

  (4) In the display device according to any one of (1) to (3), a conductive film made of the first conductive material is interposed between the insulating substrate and the scanning signal line. The conductive film interposed between the insulating substrate and the scanning signal line is electrically different from the conductive film made of the first conductive material interposed between the common electrode and the insulating substrate and the video signal line. Display device insulated.

  (5) In the display device of (4), one scanning signal line is divided into a plurality of scanning signal lines, and the plurality of scanning signal lines includes the insulating substrate and the scanning signal. A display device electrically connected by a conductive film made of the first conductive material interposed between lines.

  (6) In the display device of (5), the one scanning signal line includes a plurality of scanning signal lines larger than the number of the plurality of TFTs whose gates are connected to the scanning signal line. The display device in which the gates of the TFTs are connected to different scanning signal line segments.

  (7) In the display device of any one of (1) to (6), the plurality of scanning signal lines, the plurality of video signal lines, and the plurality of TFTs and pixels arranged in the matrix form The display device, wherein the insulating substrate having an electrode and the common electrode is one of the pair of substrates in a liquid crystal display panel in which liquid crystal is sandwiched between the pair of substrates.

  (8) Manufacturing a display device in which a plurality of scanning signal lines, a plurality of video signal lines, a plurality of TFTs and pixel electrodes arranged in a matrix, and a common electrode are formed on the surface of the insulating substrate. A first step of sequentially forming a first conductive film, a second conductive film, a first insulating film, a semiconductor film, and a third conductive film on a surface of the insulating substrate; A second region whose thickness in the first region is a first thickness and a thickness in a second region different from the first region is smaller than the first thickness; A thickness of a third region different from the first region and the second region is a third thickness smaller than the second thickness, and the first region and A first shape having a thickness of 0 (zero) in the second region and a fourth region different from the third region A second step of forming an etching resist; and using the etching resist of the first shape as a mask, the third conductive film, the semiconductor film, the first insulating film, the second conductive film, and A third step of sequentially etching the first conductive film to form the video signal line; and thicknesses of the first region, the second region, and the third region of the etching resist of the first shape Is reduced by the third thickness to change the etching resist having the first shape into a second shape in which the thickness in the third region is zero, and The third conductive film, the semiconductor film, the first insulating film, and the second conductive film are sequentially etched using the etching resist having the shape 2 as a mask to form the common electrode. A process and the second shape The thickness of the first region and the second region of the ching resist is reduced by the thickness of the second region in the second shape, and the etching resist having the second shape is changed to the second shape. Etching the third conductive film and the surface portion of the semiconductor layer with the sixth step of changing to a third shape with a thickness of 0 in the region of 3 and the third shape etching resist as a mask Forming the scanning signal line and the drain electrode and the source electrode of the TFT, removing the drain region and the source region of the semiconductor layer, and removing the third shape etching resist; And a eighth step of sequentially forming a second insulating layer and a fourth conductive film and etching the fourth conductive film to form the pixel electrode.

  (9) In the method for manufacturing a display device according to (8), in the third step, one video signal line is divided into two video signal lines divided between two adjacent scanning signal lines. In the eighth step, the fourth conductive film is etched to form the two video signal lines formed by sandwiching one scanning signal line together with the pixel electrode and the drain electrode or source of the TFT. A method of manufacturing a display device, wherein a connection wiring for connecting any one of the electrodes through a through hole is formed.

  (10) In the method for manufacturing a display device according to (8) or (9), the fifth step includes forming one scanning signal line as a plurality of scanning signal lines, and forming the first conductive film. A method of manufacturing a display device in which the plurality of scanning signal line segments are electrically connected to form the one scanning signal line.

  According to the display device and the manufacturing method of the display device of the present invention, the process of forming the etching resist can be minimized, and the manufacturing cost of the display device can be reduced.

  In addition, since the etching resist forming process can be performed a minimum number of times, it is difficult for the image signal lines and the like formed on the surface of the insulating substrate to be displaced. Therefore, for example, image quality unevenness due to positional deviation of the video signal line or the like can be reduced. In addition, further high definition is facilitated.

Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same function are given the same reference numerals and their repeated explanation is omitted.

FIGS. 1-1 and 1-2, FIGS. 2-1 and 2-2 are schematic views showing an example of a schematic configuration of a liquid crystal display device according to the present invention.
FIG. 1-1 is a schematic block diagram illustrating an example of a schematic configuration of a liquid crystal display device. FIG. 1-2 is a schematic circuit diagram illustrating an example of a circuit configuration of one pixel of the liquid crystal display panel.
FIG. 2A is a schematic plan view illustrating an example of a schematic configuration of a liquid crystal display panel. FIG. 2-2 is a schematic cross-sectional view taken along the line AA ′ in FIG.

  The present invention is applied to a liquid crystal display device having a liquid crystal display panel 1, a data driver 2, and a gate driver 3, for example, as shown in FIG. Although omitted in FIG. 1A, the liquid crystal display device of course includes, for example, a printed circuit board having a control circuit for controlling the operations of the data driver 2 and the gate driver 3, and the like. It is.

  The liquid crystal display panel 1 has a plurality of scanning signal lines GL and a plurality of video signal lines DL. The display area DA of the liquid crystal display panel 1 includes a set of pixels each having a TFT used as an active element (switching element) and a pixel electrode connected to the source electrode of the TFT. At this time, the circuit configuration of one pixel in the display area DA is, for example, as shown in FIG.

One pixel in the display area DA includes two adjacent scanning signal lines GL _n and GL _{n + 1} (n is an integer of 1 or more) and two adjacent video signal lines DL _m and DL _{m + 1} (m is 1 or more). The TFT (Tr) and the pixel electrode PX are arranged in each region. At this time, in the TFT (Tr), for example, the gate (G) is connected to the scanning signal line GL _{n + 1} , and the drain (D) is connected to the video signal line DL _m . The source (S) of the TFT (Tr) is connected to the pixel electrode PX. Further, the pixel electrode PX forms a liquid crystal capacitor (sometimes referred to as a pixel capacitor) C _LC together with the common electrode CT and the liquid crystal LC. Further, the common electrode CT of each pixel is connected to, for example, a common wiring CL.

  The data driver 2 is connected to the video signal line DL of the liquid crystal display panel 1, and generates a video or image display data (sometimes referred to as a gradation voltage signal) and applies it to each video signal line DL. It is. The gate driver 3 is connected to the scanning signal line GL of the liquid crystal display panel 1 and generates a signal (scanning signal) for selecting a pixel for writing the display data applied to each video signal line DL to the pixel electrode PX. The drive circuit is applied to each scanning signal line GL. As the data driver 2 and the gate driver 3, for example, a semiconductor package such as TCP or COF may be connected to the liquid crystal display panel 1, or a chip-like driver IC may be connected to the liquid crystal display panel 1. It may be implemented directly.

  By the way, the liquid crystal display panel 1 has a configuration in which the liquid crystal LC is sandwiched between a pair of substrates of the TFT substrate 101 and the counter substrate 102 as shown in FIGS. 2-1 and 2-2. At this time, the TFT substrate 101 and the counter substrate 102 are bonded by an annular sealing material 103 outside the display area DA, and the liquid crystal LC is a space surrounded by the TFT substrate 101, the counter substrate 102, and the sealing material 103. Sealed.

  When the liquid crystal display panel 1 is a transmissive or transflective type, a pair of polarizing plates 104A and 104B are provided on the surface facing the outside of the TFT substrate 101 and the surface facing the outside of the counter substrate 102. Yes. At this time, for example, one or more phase difference plates may be provided between the TFT substrate 101 and the polarizing plate 104A and between the counter substrate 102 and the polarizing plate 104B, respectively.

  When the liquid crystal display panel 1 is a reflection type, for example, the polarizing plate 104A on the TFT substrate 101 side may not be provided.

  In the liquid crystal display device (liquid crystal display panel 1) to which the present invention is applied, the pixel electrode PX and the common electrode CT shown in FIG. 1-2 are both formed on the TFT substrate 101 side.

FIGS. 3-1 to 3-4, FIGS. 4-1 to 4-3, FIGS. 5-1 and 5-2 are schematic views showing an example of a schematic configuration of a TFT substrate to which the present invention is applied.
FIG. 3A is a schematic plan view illustrating an example of a schematic configuration of one pixel in the TFT substrate to which the present invention is applied. 3-2 is a schematic cross-sectional view taken along line BB ′ of FIG. 3-1. FIG. 3C is a schematic cross-sectional view taken along the line CC ′ of FIG. FIG. 3-4 is a schematic cross-sectional view taken along the line DD ′ in FIG.
FIG. 4A is a schematic plan view illustrating an example of a schematic configuration of a scanning signal line and a signal input end of a common electrode in a TFT substrate to which the present invention is applied. FIG. 4-2 is a schematic cross-sectional view taken along the line EE ′ of FIG. FIG. 4C is a schematic cross-sectional view taken along the line FF ′ in FIG.
FIG. 5A is a schematic plan view illustrating an example of a schematic configuration of a signal input end of a video signal line in a TFT substrate to which the present invention is applied. FIG. 5-2 is a schematic cross-sectional view taken along the line GG ′ of FIG. 5-1.

  In the present invention, in the case where the pixel electrode PX and the common electrode CT for driving the liquid crystal LC are provided on the TFT substrate 101, more specifically, the common electrode CT, the insulation is provided on the surface of an insulating substrate such as a glass substrate. This is applied when the layers are stacked in the order of the pixel electrode PX. The TFT substrate 101 to which the present invention is applied has, for example, a configuration as shown in FIGS. 3-1 to 3-4, FIGS. 4-1 to 4-3, FIGS. 5-1 and 5-2. It has become.

  First, the configuration of one pixel in the display area DA of the TFT substrate 101 is, for example, as shown in FIGS. 3-1 to 3-4, and is common on the surface of the insulating substrate SUB such as a glass substrate. An electrode CT, a scanning signal line GL, a first insulating layer PAS1, a semiconductor layer SC, a video signal line DL, a drain electrode SD1, a source electrode SD2, a second insulating layer PAS2, and a pixel electrode PX are formed.

  In the TFT substrate 101 to which the present invention is applied, a conductive film 401g made of the same material as the common electrode CT is interposed between the insulating substrate SUB and the scanning signal line GL. Further, a first insulating layer PAS1, a semiconductor layer SC, a drain electrode SD1, and a source electrode SD2 having a function as a gate insulating film of the TFT are formed on the scanning signal line GL when viewed from the insulating substrate SUB. The source electrode SD2 is connected to the pixel electrode PX formed through the second insulating layer PAS2 through the through hole TH1.

  When the TFT is an n-channel MOS transistor, the semiconductor layer SC is, for example, the first n-type semiconductor layer SC1 and the second n-type semiconductor layer SC2, and an n-type or p-type semiconductor material having a low intrinsic or low concentration. And a third semiconductor layer SC3. At this time, the first n-type semiconductor layer SC1 corresponds to the drain region, and the second n-type semiconductor layer SC2 corresponds to the source region. Further, the third semiconductor layer SC3 has a function as a channel region.

  Further, in the TFT substrate 101 to which the present invention is applied, the planar shape of the conductive film 401g interposed between the insulating substrate SUB and the scanning signal line GL, and the first insulation layered on the scanning signal line GL. The planar shapes of the layer PAS1 and the third semiconductor layer SC3 are similar to the planar shape of the scanning signal line GL. In addition, the said planar shape is a shape seen in the plane shown to FIGS. 3-1. Also in the following description, when there is no special notice, the planar shape means the shape seen in the plane shown in FIG.

  In addition, in the TFT substrate 101 to which the present invention is applied, one video signal line DL is divided every two adjacent scanning signal lines GL. At this time, if one video signal line between two adjacent scanning signal lines GL is a video signal line segment DLp, two video signal line segments arranged with one scanning signal line GL interposed therebetween. Each DLp is formed on the video signal line segment DLp through the second insulating layer PAS2 as viewed from the insulating substrate SUB, and is a connection wiring that crosses the one scanning signal line GL in three dimensions. It is connected to BR through through holes TH2 and TH3. That is, the two video signal line segments DLp arranged with one scanning signal line GL interposed therebetween are electrically connected via the connection wiring BR that sterically intersects with the one scanning signal line GL. ing.

  At this time, the connection wiring BR is also connected to the drain electrode SD1 formed on the one scanning signal line GL by the through hole TH4.

  Note that the connection wiring BR is formed of, for example, the same material (for example, an ITO film) as the pixel electrode PX.

  Further, between the insulating substrate SUB and the video signal line DLp, the conductive layer 401d made of the same material as the common electrode CT, the conductive layer 402d made of the same material as the scanning signal line GL, and the same as the first insulating layer PAS1. An insulating film 403d made of a material, a semiconductor film 404d made of the same material as the semiconductor material used to form the third semiconductor layer SC3, and an n-type semiconductor film 405d made of the same material as the first n-type semiconductor layer SC1 are interposed. Yes. In the TFT substrate 101 to which the present invention is applied, the planar shapes of the two conductive layers 401d and 402d and the insulating layer 403d and the two semiconductor films 404d and 405d interposed between the insulating substrate SUB and the video signal line segment DLp are as follows. The shape is similar to the planar shape of the video signal line segment DLp.

  Further, the common electrode CT of the plurality of pixels arranged in the extending direction (x direction) of the scanning signal line GL is integrated with, for example, a portion passing between the scanning signal line GL and the video signal line segment DLp. Yes. In addition, a common wiring CL made of the same material as the scanning signal line GL is provided in a portion where the common electrodes CT of a plurality of pixels arranged in the extending direction (x direction) of the scanning signal line GL are integrated. An insulating film 403c made of the same material as the insulating layer PAS1 and a semiconductor film 404c made of the same material as the semiconductor material used for forming the third semiconductor layer SC3 are stacked. At this time, the planar shapes of the insulating film 403c and the semiconductor film 404c stacked on the common wiring CL are similar to the planar shape of the common wiring CL.

  Next, the configuration of the portion of the TFT substrate 101 where the scanning signal lines GL and the signal input ends of the common electrode CT are arranged is configured as shown in FIGS. 4A to 4C, for example. A conductive film 401g used as a signal input terminal of the scanning signal line GL, a signal input terminal of the common electrode CT, the second insulating layer PAS2, and the through hole TH5 are provided on the surface of the insulating substrate SUB such as a substrate. Alternatively, connection terminals CPg and CPc connected to one of the signal input ends of the common electrode CT are formed.

  The conductive film 401g used as the signal input terminal of the scanning signal line GL is a conductive film made of the same material as the common electrode CT interposed between the insulating substrate SUB and the scanning signal line GL. The connection terminals CPg and CPc are terminals made of the same material (for example, ITO film) as the pixel electrode PX, for example.

  Finally, the configuration where the signal input ends of the video signal lines DL are arranged on the TFT substrate 101 is, for example, as shown in FIGS. 5A and 5B, and the video signal line DLp A connection terminal CPd connected to the video signal line segment DLp is formed by the second insulating layer PAS2 and the through hole TH6. In addition, even in a place where the signal input ends of the video signal lines DL are arranged, the conductive layer 401d made of the same material as the common electrode CT, the scanning signal lines GL, and the insulating substrate SUB and the video signal line DLp are disposed between the insulating substrate SUB and the video signal line DLp. Conductive layer 402d made of the same material, insulating film 403d made of the same material as the first insulating layer PAS1, semiconductor film 404d made of the same material as the semiconductor material used to form the third semiconductor layer SC3, and the first n-type semiconductor An n-type semiconductor film 405d made of the same material as the layer SC1 is interposed.

  Further, the connection terminal CPd is a terminal made of the same material (for example, ITO film) as the pixel electrode PX, for example.

  Hereinafter, an example of a manufacturing method of the TFT substrate 101 having the structure as shown in FIGS. 3-1 to 3-4, FIGS. 4-1 to 4-3, FIGS. 5-1 and FIGS. -1 to FIG. 6-14.

FIGS. 6-1 to 6-14 are schematic views for explaining a method of manufacturing a TFT substrate according to an embodiment of the present invention.
FIG. 6A is a schematic cross-sectional view for explaining a portion illustrated in the description of the manufacturing method of the TFT substrate of one embodiment according to the present invention.
FIG. 6B is a schematic cross-sectional view for explaining the first step in the manufacturing method of the TFT substrate of this example. FIG. 6C is a schematic cross-sectional view for explaining a second step in the manufacturing method of the TFT substrate of this example. FIG. 6-4 is a schematic cross-sectional view for explaining a specific example of the exposure method in the etching resist forming method in the second step. 6-5 is a schematic cross-sectional view showing an example of the shape of an etching resist formed by exposure with the exposure method shown in FIG. 6-4.
FIG. 6-6 is a schematic cross-sectional view for explaining a third step in the manufacturing method of the TFT substrate of this example. 6-7 is a schematic cross-sectional view for explaining a fourth step in the manufacturing method of the TFT substrate of this example. FIG. 6-8 is a schematic cross-sectional view for explaining a fifth step in the manufacturing method of the TFT substrate of this example. FIG. 6-9 is a schematic cross-sectional view for explaining a sixth step in the manufacturing method of the TFT substrate of this example. FIG. 6-10 is a schematic cross-sectional view for explaining a seventh step in the manufacturing method of the TFT substrate of this example.
FIG. 6-11 is a schematic cross-sectional view for explaining an eighth step in the manufacturing method of the TFT substrate of this example. FIG. 6-12 is a schematic cross-sectional view for explaining a ninth step in the manufacturing method of the TFT substrate of this example. FIG. 6-13 is a schematic cross-sectional view for explaining a tenth step in the manufacturing method of the TFT substrate of this example. FIG. 6-14 is a schematic cross-sectional view for explaining an eleventh step in the manufacturing method of the TFT substrate of this example.

  Processing (processing) in each step of the manufacturing method of the TFT substrate 101 having the structure shown in FIGS. 3-1 to 3-4, FIGS. 4-1 to 4-3, FIGS. 5-1 and 5-2. Referring to the six regions shown in FIG. 6A as an example, what kind of processing (processing) is performed in each region will be described.

  The cross-sectional configuration of the region AR1 among the six regions shown in FIG. 6A shows the cross-sectional configuration of the region where the scanning signal lines GL and TFT are formed, and among the cross-sectional configurations shown in FIG. This corresponds to the cross-sectional configuration of the portion where the scanning signal line GL and TFT are formed. Further, the cross-sectional configuration of the area AR2 is a cross-sectional configuration of an area connecting two video signal line segments DLp arranged with one scanning signal line GL interposed therebetween, and is shown in FIG. It corresponds to a cross-sectional configuration. The cross-sectional configuration of the area AR3 indicates the cross-sectional configuration of the signal input end of the video signal line DL, and corresponds to the cross-sectional configuration illustrated in FIG. The cross-sectional configurations of the region AR4 and the region AR5 indicate the cross-sectional configuration of the signal input end of the scanning signal line GL (and the common electrode CT), and the cross-sectional configuration of the region AR4 is the cross-sectional configuration illustrated in FIG. Correspondingly, the cross-sectional configuration of the area AR5 corresponds to the cross-sectional configuration shown in FIG. Further, the cross-sectional configuration of the area AR6 shows the cross-sectional configuration of the area where the common electrode CT and the pixel electrode PX are formed, and the common electrode CT and the pixel electrode PX of the cross-sectional configuration shown in FIG. 3-4 are formed. This corresponds to the cross-sectional configuration of the portion.

  In FIGS. 6A and 6B, FIGS. 6-6 to 6-14 show the etching end faces of the stacked conductive films and insulating films in order to make the processing (processing) in each process easy to understand.

  In the manufacturing method of the TFT substrate 101 of the present embodiment, first, as a first step, for example, as shown in FIG. 6B, the first conductive film 401, the first conductive film 401, the surface of the insulating substrate SUB such as a glass substrate. The second conductive film 402, the first insulating film 403, the first semiconductor film 404, the second semiconductor film 405, and the third conductive film 406 are formed (deposited) in this order. The first conductive film 401 is a conductive film for forming the common electrode CT and the like, and is a conductive film having a high light transmittance such as an ITO film or an IZO film. The second conductive film 402 is a conductive film for forming the scanning signal lines GL and the like, for example, an Al (aluminum) film. The first insulating film 403 is an insulating film for forming a gate insulating film of the TFT, and is a silicon nitride film or a silicon oxide film, for example. The first semiconductor film is a semiconductor film for forming a channel region of the TFT, and is, for example, an n-type or p-type amorphous silicon film having intrinsic or low concentration. The second semiconductor film is a semiconductor film for forming the drain region and the source region of the TFT, and is, for example, an n-type amorphous silicon film having a high concentration. The third conductive layer is a conductive film for forming the video signal line DL (video signal line segment DLp), the drain electrode SD1 and the source electrode SD2 of the TFT, and is an Al film, for example.

Next, as a second step, for example, as shown in FIG. 6-3, the first region ER1 ₁ , which is the first thickness, is formed on the third conductive film 406 more than the first thickness. A first etching resist ER1 having three regions, a second region ER1 _{2 having} a thin second thickness and a third region ER1 ₃ having a third thickness thinner than the second thickness is formed. To do.

  The first shape etching resist ER1 can be formed relatively easily by applying an exposure technique called half exposure, for example. That is, for example, as shown in FIG. 6-4, on the surface of the glass substrate SUBm, the first region A1 where the transmittance of the light 6 is almost 0 and the transmittance of the light 6 is T1 (<1). There are four regions: a second region A2, a third region A3 in which the transmittance of light 6 is T2 (1> T2> T1), and a fourth region A4 in which the transmittance of light 6 is approximately 1. The photosensitive resist 5 applied on the third conductive film 406 is exposed using an exposure mask on which the light shielding film M is formed as obtained.

  At this time, for example, when the photosensitive resist 5 in the fourth area A4 is exposed for a time period for which almost all the photosensitive resist 5 is exposed, the photosensitive resist 5 in the second area A2 and the photosensitive resist 5 in the third area A3 Is partially exposed in accordance with the ratio of the transmittance of light 6. Therefore, when the photosensitive resist 5 exposed using such an exposure mask is developed, for example, in the first region A1, the second region A2, and the third region A3 as shown in FIG. 6-5. A resist film ER having a different thickness and a thickness of 0 in the fourth region A4 is obtained.

  Next, as a third step, for example, as shown in FIGS. 6-6, the third conductive film 406, the second semiconductor film 405, and the first semiconductor are formed using the etching resist ER1 having the first shape as a mask. Etching is performed in the order of the film 404, the first insulating film 403, the second conductive film 402, and the first conductive film 401. By this third step, the first conductive film 401d, the second conductive film 402d, the first insulating film 403d, the first conductive film 401d are formed between the third conductive film 406 and the insulating substrate SUB. A video signal line DL (video signal line segment DLp) in which the semiconductor film 404d and the second semiconductor film 405d are interposed is formed. In addition, the planar shape of the common electrode CT is completed by the third step.

Next, as a fourth step, for example, as shown in Figure 6-7, the entire first etching resist ER1, an amount corresponding to the thickness of the third region ER1 ₃ (third thickness) thin to, the first etching resist ER1, second shape having the first shape as shown in Figure 6-3, only the first region ER1 ₁ and the second region ER1 ₂ of the two regions To. In order to change the first etching resist ER1 from the first shape to the second shape, for example, O ₂ ashing may be performed.

  Next, as a fifth step, for example, as shown in FIGS. 6-8, the third conductive film 406, the second semiconductor film 405, and the first etching resist ER1 having the second shape are used as a mask. Etching is performed in order of the first semiconductor film 404, the first insulating layer 403, and the second conductive film 402. By this fifth step, the unnecessary third conductive film 406, the second semiconductor film 405, the first semiconductor film 404, the first conductive film 401, which are formed of the first conductive film 401 and are stacked in the region AR6. The common electrode CT from which the first insulating layer 403 and the second conductive film 402 are removed is formed.

Next, as the sixth step, for example, as shown in Figure 6-9, the entire first etching resist ER1, and as thin as the second region ER1 min of ₂ thickness of the second shape , the first etching resist ER1, from the second shape shown in Figure 6-7, to third shape having only the first region ER1 _1. In order to change the first etching resist ER1 from the second shape to the third shape, for example, O ₂ ashing may be performed.

  Next, as a seventh step, for example, as shown in FIG. 6-10, the third conductive film 406 and the second semiconductor film 405 are formed using the first etching resist ER1 having the third shape as a mask. Etching is performed in order. By the seventh step, the drain electrode SD1 and the source electrode SD2 made of the third conductive film 406 and the drain region SC1 and the source region SC2 of the semiconductor layer SC made of the second semiconductor film 405 are formed in the regions AR1 and AR2. Is formed. In the seventh step, the first conductive film 401g is interposed between the second conductive film 402 and the insulating substrate SUB, and the first insulating film 403g and the first semiconductor film 404g are formed. A common wiring in which the first conductive film 401c is interposed between the stacked scanning signal line GL and the insulating substrate SUB, and the first insulating film 403c and the first semiconductor film 404c are stacked. CL is also formed.

  Thus, in the manufacturing method of the TFT substrate 101 of the present embodiment, the common electrode CT made of the first conductive film 401 and the second conductive film 402 are made by performing the first to seventh steps. A plurality of scanning signal lines GL and a common wiring CL, a semiconductor layer SC of a TFT composed of the first semiconductor film 404 and the second semiconductor film 405, and a video signal line DL (video signal line composed of the third conductive film 406) Min DLp), the drain electrode SD1 and the source electrode SD2 of the TFT are formed.

  In the case of a conventional general TFT substrate manufacturing method, a step of forming a common electrode CT made of a first conductive film 401, a plurality of scanning signal lines GL and a common wiring CL made of a second conductive film 402 are formed. A step of forming, a step of forming a semiconductor layer SC of a TFT comprising the first semiconductor film 404 and the second semiconductor film 405, a video signal line DL (video signal line DLp) comprising the third conductive film 406, a TFT In each step of forming the drain electrode SD1 and the source electrode SD2, the step of forming an etching resist by, for example, photolithography using an exposure mask, and the step of removing (stripping) the etching resist after etching are performed.

  On the other hand, in the manufacturing method of the TFT substrate of the present embodiment, the shape of the etching resist ER1 formed by one photolithography is changed from the first shape to the second shape and from the second shape to the third shape. By performing the etching, the common electrode CT made of the first conductive film 401, the plurality of scanning signal lines GL and the common wiring CL made of the second conductive film 402, the first semiconductor film 404 and the second semiconductor are formed. A TFT semiconductor layer SC made of the film 405, a video signal line DL (video signal line DLp) made of the third conductive film 406, a drain electrode SD1 and a source electrode SD2 of the TFT can be formed.

  Next, as an eighth step, for example, as shown in FIG. 6-11, a second insulating layer PAS2 is formed. The second insulating layer PAS2 is, for example, a silicon nitride film, a silicon oxide film, or an organic insulating film.

  Next, as a ninth step, for example, as shown in FIG. 6-12, a second etching resist ER2 is formed on the second insulating layer PAS2, and through-holes TH1, TH1 are formed in the second insulating layer PAS2. TH2, TH3, TH4, TH5, TH6 are formed.

  Next, after removing (stripping) the second etching resist ER2, as a tenth step, for example, as shown in FIG. 6-13, a fourth conductive film 407 is formed on the second insulating layer PAS2. Form. The fourth conductive film 407 is a conductive film having a high light transmittance, such as an ITO film or an IZO film.

  Next, as an eleventh step, for example, as shown in FIG. 6-14, a third etching resist ER3 is formed on the fourth conductive film 407, and the fourth conductive film 407 is etched. By this eleventh step, the pixel electrode PX connected to the TFT source electrode SD2, the two video signal line segments DLp arranged across the one scanning signal line GL, and the connection wiring connected to the drain electrode SD1 of the TFT The connection terminal CPd of the BR, the video signal line DL, the connection terminal CPg of the scanning signal line GL, and the connection terminal CPd of the common electrode CT are formed.

  After the eleventh step, when the third etching resist ER3 is removed (peeled), the TFT substrate 101 as shown in FIG. 6A is obtained.

  As described above, according to the manufacturing method of the TFT substrate 101 of this embodiment, the number of etching resists formed by photolithography can be reduced to three. That is, the step of forming an etching resist by photolithography and the step of peeling off can be minimized. As a result, the manufacturing cost of the TFT substrate 101 can be reduced. Further, it is possible to reduce the positional deviation of the video signal line DL, the pixel electrode PX, and the like due to the positional deviation of the exposure mask when forming the etching resist, and to reduce the occurrence of image quality unevenness due to the positional deviation. Further, since the positional deviation is less likely to occur, high definition is facilitated.

FIGS. 7A to 7C are schematic views for explaining a modification of the manufacturing method of the TFT substrate 101 of this embodiment.
FIG. 7-1 is a schematic plan view showing a schematic configuration of a modified example of the TFT substrate to which the present invention is applied. FIG. 7-2 is a schematic cross-sectional view taken along the line HH ′ of FIG. FIG. 7C is a schematic cross-sectional view for explaining the manufacturing method of the TFT substrate shown in FIGS. 7C shows a cross-sectional configuration at the same location as FIG.

  In the manufacturing method of the TFT substrate of the present embodiment, the first etching resist ER1 formed by one photolithography is changed from the first shape to the second shape and from the second shape to the third shape. The third conductive film 406, the second semiconductor film 405, the first semiconductor film 404, the first insulating film 403, the second conductive film 402, and the first conductive film 401 are etched. Therefore, for example, the first insulating film 403 and the first semiconductor film 404 having a planar shape similar to the planar shape of the scanning signal line GL remain on the scanning signal line GL when viewed from the insulating substrate SUB. At this time, in the first semiconductor film 404, only the region in the vicinity of the second semiconductor film (drain region SC1 and source region SC2) functions as the channel region SC3 of the TFT. However, when the first semiconductor film 404 is an amorphous silicon film, for example, carriers may move between adjacent TFTs, or current may flow due to external light or the like.

  Therefore, when forming the scanning signal line GL by the manufacturing method of the TFT substrate 101 of the present embodiment, for example, as shown in FIGS. The scanning signal lines GLp may be electrically connected by the first conductive film 401g that is divided into the signal line segments GLp and remains between the insulating substrate SUB and the scanning signal lines GL.

  At this time, one scanning signal line GL is divided into scanning signal line segments GLp larger than the number of TFTs whose gates are connected to the one scanning signal line GL, and is divided into one scanning signal line segment GLp. It is desirable that only the gate of one TFT is connected. In this way, since the first semiconductor film remaining on the scanning signal line GL is also divided in the same manner as the scanning signal line segment GLp, carrier movement between adjacent TFTs can be prevented.

When the scanning signal line GL is divided as shown in FIGS. 7A and 7B, in the second step, for example, as shown in FIG. 7C, the region where the scanning signal line GL is formed. The first etching resist ER1 having the _third region ER13 may be formed therein. In this manner, when the first etching resist ER1 in the fourth step was changed from a first shape to a second shape, the etching resist of the third region ER1 ₃ is eliminated. Therefore, in the fifth step, the third conductive film 406, the second semiconductor film 405, the first semiconductor film 404, the first insulating film 403, and the second conductive film 402 are removed, and a plurality of scan signals Divided into line segments GLp.

  The present invention has been specifically described above based on the above-described embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. is there.

  For example, in each of the drawings used for the description of the above embodiment, when the second insulating layer PAS2 is formed, a case where the film thickness is uniform in each region is described as an example. Of course, for example, the second insulating layer PAS2 may be formed so that the surface on which the fourth conductive film 407 used for forming the pixel electrode PX and the like is formed is flat.

  In the above embodiment, the first conductive film 401d interposed between the insulating substrate SUB and the video signal line segment DLp is electrically insulated (isolated) in a pattern independent of the common electrode CT. Although the case has been described as an example, the present invention is not limited thereto, and the first conductive film 401d interposed between the insulating substrate SUB and the video signal line segment DLp may be part of the common electrode CT. It is.

It is a schematic block diagram which shows an example of schematic structure of a liquid crystal display device. It is a schematic circuit diagram which shows an example of the circuit structure of 1 pixel of a liquid crystal display panel. It is a schematic plan view which shows an example of schematic structure of a liquid crystal display panel. It is a schematic cross section in the A-A 'line of FIGS. It is a schematic top view which shows an example of schematic structure of 1 pixel in the TFT substrate to which this invention is applied. It is a schematic cross section in the B-B 'line of Drawing 3-1. It is a schematic cross section in the C-C 'line of FIGS. It is a schematic cross section in the D-D 'line of FIGS. It is a model top view which shows an example of schematic structure of the scanning signal line in the TFT substrate to which this invention is applied, and the signal input end of a common electrode. It is a schematic cross section in the E-E 'line of FIGS. It is a schematic cross section in the F-F 'line | wire of FIG. 4-1. It is a schematic top view which shows an example of schematic structure of the signal input end of the video signal line in the TFT substrate to which this invention is applied. It is a schematic cross section in the G-G 'line of FIGS. It is a schematic cross section for demonstrating the location shown in order to demonstrate the manufacturing method of the TFT substrate of one Example by this invention. It is a schematic cross section for demonstrating the 1st process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 2nd process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating one specific example of the exposure method in the formation method of the etching resist in a 2nd process. It is a schematic cross section which shows an example of the shape of the etching resist formed by exposing with the exposure method shown to FIGS. 6-4. It is a schematic cross section for demonstrating the 3rd process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 4th process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 5th process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 6th process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 7th process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 8th process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 9th process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 10th process in the manufacturing method of the TFT substrate of a present Example. It is a schematic cross section for demonstrating the 11th process in the manufacturing method of the TFT substrate of a present Example. It is a model top view which shows schematic structure of the modification of the TFT substrate to which this invention is applied. It is a schematic cross section in the H-H 'line of FIGS. It is a schematic cross section for demonstrating the manufacturing method of the TFT substrate shown to FIGS. 7-1 and FIGS. 7-2.

Explanation of symbols

1 ... liquid crystal display panel 101 ... TFT substrate 102 ... facing substrate 103 ... sealing material 104A, 104B ... polarizer SUB ... insulating substrate _{GL, GL n, GL n +} 1 ... scanning signal lines GLp ... scanning signal line _DL, DL _m, DL _{m + 1} ... Video signal line DLp ... Video signal line segment SC ... Semiconductor layer SC1 ... Drain region SC2 ... Source region SC3 ... Channel region SD1 ... Drain electrode SD2 ... Source electrode PX ... Pixel electrode CT ... Common electrode CL ... Common wiring CPd, CPg, CPc: connection terminal PAS1: first insulating layer PAS2: second insulating layer 2 ... data driver 3 ... gate driver 401, 401g, 401d ... first conductive film 402, 402d ... second conductive film 403, 403d, 403c: first insulating film 404, 404d, 404c: first semiconductor film 4 5, 405d ... second semiconductor film 406 ... third conductive film 407 ... fourth conductive film 5 ... photosensitive resist 6 ... light ER ... etching resist ER1 ... first etching resist ER2 ... second etching resist ER3 ... Third etching resist

Claims (10)

The surface of the insulating substrate has a plurality of scanning signal lines, a plurality of video signal lines, a plurality of TFTs and pixel electrodes arranged in a matrix, and a common electrode,
The TFT is stacked on a gate insulating film stacked on the scanning signal line as viewed from the insulating substrate, a semiconductor layer stacked on the gate insulating film, and a drain region of the semiconductor layer. A MIS transistor having a drain electrode and a source electrode stacked on the source region of the semiconductor layer;
The pixel electrode is connected to the source electrode or the drain electrode through a through hole,
The pixel electrode and the common electrode are laminated on the surface of the insulating substrate in the order of the common electrode, an insulating layer, and the pixel electrode.
The common electrode is made of a first conductive material, the scanning signal line is made of a second conductive material, the video signal line, the drain electrode and the source electrode of the TFT are made of a third conductive material, and the pixel electrode Consists of a fourth conductive material,
The gate insulating film is made of a first insulating material, and the insulating layer interposed between the common electrode and the pixel electrode is a display device made of a second insulating material,
Between the insulating substrate and the video signal line, a conductive film made of the first conductive material, a conductive film made of the second conductive material, an insulating film made of the first insulating material, and the TFT The semiconductor material film used for forming the semiconductor layer is interposed,
The conductive film, the insulating film, and the semiconductor material film interposed between the insulating substrate and the first video signal line have substantially the same shape as viewed in the plane of the video signal line. A display device characterized by being identical to each other. One video signal line is divided into every two adjacent scanning signal lines, and is divided into a plurality of video signal lines that do not overlap with the two adjacent scanning signal lines in plan view. Has been
The two video signal line segments arranged with one scanning signal line interposed therebetween are made of the fourth conductive material and have a connection wiring and a through hole that three-dimensionally intersects the one scanning signal line. The display device according to claim 1, wherein the display device is connected to the display device.   The connection wiring is connected to an electrode not connected to the pixel electrode of the drain electrode and the source electrode through a through hole different from the through hole connected to the two video signal line segments. The display device according to claim 2. A conductive film made of the first conductive material is interposed between the insulating substrate and the scanning signal line,
The conductive film interposed between the insulating substrate and the scanning signal line is electrically different from the conductive film made of the first conductive material interposed between the common electrode and the insulating substrate and the video signal line. The display device according to claim 1, wherein the display device is electrically insulated.   One scanning signal line is divided into a plurality of scanning signal lines, and the plurality of scanning signal lines are provided between the insulating substrate and the scanning signal line. The display device according to claim 4, wherein the display device is electrically connected by a conductive film made of a material.   The one scanning signal line includes a number of scanning signal lines larger than the number of the plurality of TFTs whose gates are connected to the scanning signal line, and the gates of the plurality of TFTs are different from each other. The display device according to claim 5, wherein the display device is connected to a minute.   The insulating substrate having the plurality of scanning signal lines, the plurality of video signal lines, the plurality of TFTs and pixel electrodes arranged in a matrix, and the common electrode is between a pair of substrates. 7. The display device according to claim 1, wherein the display device is one of the pair of substrates in a liquid crystal display panel having a liquid crystal sandwiched therebetween. This is a method for manufacturing a display device in which a plurality of scanning signal lines, a plurality of video signal lines, a plurality of TFTs and pixel electrodes arranged in a matrix, and a common electrode are formed on the surface of an insulating substrate. And
A first step of sequentially forming a first conductive film, a second conductive film, a first insulating film, a semiconductor film, and a third conductive film on the surface of the insulating substrate;
On the third conductive film, the thickness in the first region is the first thickness, and the thickness in the second region different from the first region is thinner than the first thickness. A third thickness that is a second thickness and that is different from the first region and a third region different from the second region, and is a third thickness that is less than the second thickness, A second step of forming an etching resist of a first shape having a thickness of 0 (zero) in a region, the second region, and a fourth region different from the third region;
Using the first shape etching resist as a mask, the third conductive film, the semiconductor film, the first insulating film, the second conductive film, and the first conductive film are sequentially etched. A third step of forming the video signal line;
The thickness of the first region, the second region, and the third region of the first shape etching resist is reduced by the third thickness, and the etching resist of the first shape is A fourth step of changing to a second shape in which the thickness in the third region is zero;
The third conductive film, the semiconductor film, the first insulating film, and the second conductive film are sequentially etched using the second shape etching resist as a mask to form the common electrode. 5 steps,
Etching the second shape by reducing the thickness of the first region and the second region of the etching resist of the second shape by the thickness of the second region in the second shape. A sixth step of changing the resist into a third shape in which the thickness in the second region is zero;
Etching the third conductive film and the surface portion of the semiconductor layer using the third shape etching resist as a mask to form the scanning signal line, the drain electrode and the source electrode of the TFT, and A seventh step of separating the drain region and the source region of the semiconductor layer;
An eighth step of removing the third-shaped etching resist, sequentially forming a second insulating layer and a fourth conductive film, and etching the fourth conductive film to form the pixel electrode; A method for manufacturing a display device, comprising: In the third step, one video signal line is formed as a video signal line segment divided every two adjacent scanning signal lines,
In the eighth step, any one of two video signal lines formed by sandwiching one scanning signal line and the TFT drain electrode or source electrode together with the pixel electrode by etching the fourth conductive film. The method for manufacturing a display device according to claim 8, wherein a connection wiring for connecting either one of the electrodes through a through hole is formed.   In the fifth step, one scanning signal line is formed as a plurality of scanning signal line segments, and the plurality of scanning signal line segments are electrically connected by the first conductive film. 10. The method of manufacturing a display device according to claim 8, wherein the scanning signal line is a single line.

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